Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses

Transcription

1 Eliminting Non-Determinism During of High-Speed Source Synchronous Differentil Buses Abstrct The t-speed functionl testing of deep sub-micron devices equipped with high-speed I/O ports nd the synchronous nture of such I/O trnsctions poses significnt chllenges. In this pper, the problem of nondeterminism in the output response of the device-under-test (DUT) is described. This cn rise due to limited utomted test equipment (ATE) edge plcement ccurcy (EPA) in the source synchronous of the stimulus strem to the high-speed I/O port from the tester. A simple yet effective solution tht uses trigger signl to initite deterministic trnsfer of test inputs into the core domin of the DUT from the high-speed I/O port is presented. The solution llows the ppliction of t-speed functionl ptterns to the DUT, while incurring very smll hrdwre overhed nd trivil increse in test ppliction time. An nlysis of the probbility of non-determinism s function of speed nd EPA is presented. It shows tht s the frequency of opertion of high-speed I/Os continues to rise, non-determinism will become significnt problem tht cn result in n uncceptble yield loss.. Introduction The incresing demnd for throughput hs ccelerted the move wy from hierrchicl shred bus rchitectures like PCI nd PCI-X towrds high performnce, pcket switched rchitectures like RpidIO TM [Bouvier 00], Infinibnd TM [Infinibnd 0], nd HyperTrnsport TM [HyperTrnsport 0]. These protocols spn wide rnge of pplictions, both generl purpose nd otherwise. Hierrchicl shred bus topologies hve filed to meet the dt bndwidth requirements nd incresed system concurrency needs in tody s demnding high-speed, high-performnce processing environments. The fct tht device hs to wit for the bus rbiter to complete n existing trnsction before serving the next request poses severe limittion on the vilble bndwidth on shred buses. Improvements like incresing the bus width nd the bus frequency not only counter ech other due to skew between signls but lso increse the pin count on the device. Moreover, routing issues Krtik Mohnrm nd Nur A. Toub Computer Engineering Reserch Center Deprtment of Electricl nd Computer Engineering University of Texs t Austin, Austin, TX E-mil: {kmrm, toub}@ece.utexs.edu constrin the number of devices tht cn directly communicte with ech other s the complexity of shred bus protocols increses. It is interesting to note tht tody s 33 MHz PCI-X stndrd llows only devices per bus segment, nd is for ll prcticl purposes pointto-point connection [Jenicke 0]. These limittions hve led to the emergence of high-speed, source synchronous, low power-low voltge differentil signling (LP-LVDS) prllel (or seril) buses such s the RpidIO TM interconnect rchitecture (optimized for intr-system interconnections). Such high-performnce interconnect technologies employ pcket switching to trnsfer dt from source to destintion thereby providing high degree of sclbility nd re projected to ttin performnce levels scling to 0 Gbps nd beyond. Other exmples of emerging high-speed interconnect rchitectures include Infinibnd TM (optimized for system re networks) nd HyperTrnsport TM (optimized for system level interconnections). The development of pcket switched interconnect rchitectures is not without its shre of chllenges for the test community. The chllenges re mnifold, requiring innovtive ides not only from n utomted test equipment (ATE) hrdwre perspective but lso from design-for-test (DFT) nd test genertion perspective. There hs been some work in the re of ATE hrdwre development to meet the requirements of supply nd cpture of high-speed differentil stimuli to the device-under-test (DUT). In [Oshim 0], pin electronics integrted circuit cpble of testing high-speed differentil buses up to 3 Gbps is presented. In [Keezer 0], multiplexing / de-multiplexing pproch to relize higher performnce from existing ATE is presented. Despite high levels of structured testbility provided by scn nd built-in self test, deep sub-micron designs, with multiple domins nd internl synchronous boundries generlly require full complement of t-speed functionl tests to be exercised in test mode. This is importnt not only for speed binning but lso for detecting complex defects tht re only uncovered when the full cpbilities of the DUT re exercised [Mxwell 00].

2 Functionl tests for high-speed I/O ports use strem of stimulus pckets sent to the receive port of the DUT. The DUT processes these pckets nd the tester monitors the response pcket strem from the DUT. However, non-determinism cn be introduced by externl inputs s well s the presence of synchronous boundries internl to the DUT such tht the output from the DUT is not cycle deterministic. One such synchronous boundry inherent to the DUT is between the receive logic domin of the high-speed I/O port nd the core logic domin. The receive logic is driven by the source synchronous (henceforth the ) from the tester, tht is synchronous with respect to the core of the DUT. It is importnt tht the tester not clssify defect-free device s filure just becuse the received response did not mtch the expected one due to non-determinism. Non-determinism cn be introduced due to jitter nd limited ATE edge plcement ccurcy (EPA) in the source synchronous of the stimulus strem to the DUT from the tester. The frequency of opertion of high-speed differentil buses hs incresed t rte much fster thn the rte of improvement in ATE EPA, eroding lrge mrgins of comfort tht were previously vilble. As this trend continues, the mbiguity of just when the ATE generted is cptured by the DUT s core domin is incresing nd gurnteeing cycle-for-cycle deterministic behvior of the DUT is becoming chllenge. In this pper, we present DFT technique imed t removing the non-deterministic behvior in the response strem from the DUT t high performnce rtes. We lso provide n nlysis of the probbility of non-determinism s function of speed nd EPA nd show tht s the frequency of opertion of high-speed I/Os continues to rise, non-determinism will become significnt problem tht cn result in n uncceptble yield loss. The rest of the pper is orgnized s follows. In Sec., we describe the test environment for high-speed I/O port nd discuss the problem of non-determinism in greter detil. In Sec. 3, we present the proposed solution to the problem. In Sec. 4, we present model for the EPA of tester, nd nlyze the problem of non-determinism using n nlyticl frmework. Section 5 is conclusion.. Problem of non-determinism The DUT in the test environment is shown in Fig.. The DUT hs core, Tx (trnsmit), nd n Rx (receive source synchronous). The core is creted by n on-dut from n ATE supplied source nd is phse ligned with the incoming reference from the ATE. The core nd the Tx my be integer multiples of ech other (including -) nd my lso include non-integer modes such s 3-, 5-, etc. It is usully the cse tht the core is slow one while the Tx, used by the DUT to trnsmit source synchronous dt, is fst one. The Tx going into the ATE from the DUT is used by the ATE to cpture the Tx dt from the DUT source synchronously. We ssume throughout tht the tester is ble to receive the source synchronous (the Tx of the DUT) of the response strem, cpture the Tx dt, nd tht there is no problem of resolution here. Some recent ATE provide the bility to cpture source synchronous bus with its own t frequencies up to.5gbps [Terdyne 00], [Agilent 0], [Schlumberger 0]. Ref Automted Equipment Primry Inputs Primry Outputs Trnsmit Port Tx Tx dt Receive Port FIFO Elsticity Buffer Figure. DUT in the test environment Device Under Slow Core Asynchronous Boundry Pckets to the high-speed I/O port cn be clssified into two types dt nd control. Control symbols re issued to initite request for nd to cknowledge the receipt of pckets in the system, s well s for system mintennce. Control symbols re lso used for flow control, when retry nd idle symbols re inserted to mnge the flow of pckets in the system. LP-LVDS buses re never tri-stted, but issue idle control symbols into the trnsmit strem when not processing ny dt. time A A A A idle idle B B B B idle idle Figure. Smple input strem from ATE to DUT Most pcket switched I/O rchitectures use n elsticity buffer in the receive circuitry to temporrily store pckets before trnsferring them into the core domin. The source synchronous dt () tht is embedded in the stimulus strem from the ATE is de-serilized s it is ed into the elsticity buffer with the source synchronous (). Severl cycles lter, once the dt is stble, it is pulled out of the 3 4

3 elsticity buffer using the slow core. An synchronous boundry is explicitly crossed when the pcket is trnsferred into the slow core domin of the DUT. Figure shows smple input strem to the DUT from the tester. Note tht the I/O port functions in double-dt-rte (DDR) mode, since pckets re ed on the rising s well flling edges of the. The pcket switched nture of the I/O protocol cn complicte test response nlysis in the presence of synchronous boundries internl to the DUT. In n idel environment, s modeled in simultion, ll events on the tester nd the DUT occur t known bsolute times. However, in the rel world, there is the issue of ATE EPA which cuses vribility in when exctly events occur. The EPA is mesure of the ccurcy with which the ATE cn plce n input drive edge t exctly the sme point in time reltive to common reference. While these problems hve lwys existed, they were never cuse for concern becuse the EPA of the ATE ws so smll compred to cycle times such tht sweet spot ws lwys found for timing edge sets where the DUT would respond in deterministic mnner. However, in [ITRS 0], it is estimted tht off-chip I/O speeds hve improved t rte of 30% per yer, while ATE EPA hs improved t rte of % per yer. Thus, s cycle times of high-speed buses re rpidly decresing nd EPAs re not decresing t the sme rte, we re pproching point where non-determinism becomes n issue. A detiled nlysis of the probbility of non-determinism with respect to frequencies nd tester EPA is provided in Sec. 4. Non-determinism due to limittions in tester EPA occurs becuse of mbiguity in just when the source synchronous from the tester rrives t the DUT. When crossing the synchronous boundry internl to the DUT, the cycle in which the pcket is red from the elsticity buffer by the core logic could be misligned by one internl core cycle. This vribility in when the pcket is received cn cuse the subsequent output strem to be different thn expected (without the presence of defect). Non-determinism is illustrted in Fig. 3. Pcket is ed into the core domin in cycle s expected. Now consider pcket b from the tester, which is expected to be ed in from the elsticity buffer in cycle 3 of the DUT s slow core. Limittions in the EPA of the tester cuse it to rrive lter such tht it is ed into the elsticity buffer in cycle 4 of the DUT s core (insted of cycle 3 s originlly expected). This cuses the test stimuli tht re synchronized to the core of the DUT when pcket b is received to be offset by one core cycle something tht simultion did not predict, nd something tht cn cuse devition from the expected response (s will be elborted on shortly). The ATE cn end up clssifying the prt s defective simply becuse the pcket ws received cycle lter thn intended. Vribility in pcket rrivl times is not problem in norml opertion becuse the functionl logic cn hndle pckets in ny order nd will provide correct output response for the order it receives the pckets in. The problem exists in test becuse it is necessry tht the output response mtch wht is expected by the tester so tht the prt cn be correctly clssified. () Simultion predicted order of events b b b b Pcket 3 Pcket 3 Pcket b (b) Non-determinism due to limittions in ATE EPA b b b b Pcket b not redy Figure 3. Exmple of non-determinism where pcket b is red in different core cycle. Types of non-determinism Two forms of the non-determinism in the output strem re possible. The first is tht the response from the DUT occurs in the sme order s the expected response, but is simply delyed by n extr idle in the Tx strem. This cn be hndled by mtch mode on testers tody where they utomticlly compre nd synchronize the ctul nd expected dt strems. The second, nd more difficult, cse to hndle is when the DUT issues ll the test response pckets nd controls correctly, but in n order other thn tht predicted by simultion. This cn occur becuse the order in which things re processed by the core logic is ltered due to the vribility in when the pcket is received with respect to the other test stimuli synchronized to the core.. Possible solutions A nïve solution to this problem would be to test the DUT t slower speed so tht the input strem is less likely to be ffected by ny jitter in the fst source synchronous from the tester nd the slow core of the DUT. Although vible option, direct testing of

4 the DUT s cpbilities through t-speed functionl tests is indispensble especilly since such tests cn uncover complex defects undetectble t lower speeds of opertion. A second option would be to include n explicit post-processing phse, where n lgorithm is used to exmine the contents of the cpture RAM of the ATE to determine if the response strem cn be mtched to tht from non-defective prt. The lgorithm would try to mtch the ctul response to one tht could hve been obtined from non-defective prt by exmining the plces where mismtch occurred, nd try to fit tht with possible sequence of vlid events in the DUT. Depending on the extent of non-determinism in the response, the test dt volume (both input nd output), nd the complexity of the lgorithm used, the costs ssocited with this pproch could be prohibitive. 3. Proposed solution The bsic ide is to ensure tht the DUT receives dt from the tester on deterministic cycle boundries of the slow core, i.e., to ensure tht the DUT s in pckets from the elsticity buffer into the slow core domin in deterministic fshion. Since the DUT processes test pckets in deterministic wy once they enter the slow core domin, the output response sent to the tester will lso be deterministic. Trigger () Simultion predicted order of events Pcket b b b b Pcket b boundry, the trigger signl is sserted fixed number of cycles before the desired event. When the trigger is sserted, counter is strted on the DUT tht prompts the reding of the elsticity buffer fixed number of cycles lter. The timing of the trigger signl is computed so tht the pcket will lwys be redy in the elsticity buffer even with the worst-cse rrivl time tking the EPA of the source synchronous from the tester to the DUT into considertion. If the pcket rrives erlier, it is just held in the elsticity buffer until the predetermined core cycle. The trigger signl ensures tht the pcket crosses the synchronous boundry in deterministic fshion. Figure 4 shows how the proposed solution will work to resolve the problem presented in Fig. 3. In this cse, the trigger is sserted such tht pckets re ed in cycles nd 4 of the slow core of the DUT. If the pcket rrives t the expected time, it is held in the elsticity buffer for one core cycle before it is red (s shown in the upper prt of the digrm). However, if jitter nd limited tester EPA cuse the pcket rrivl time to be delyed, it is still red in during the sme core cycle s the previous cse (s shown in Fig. 4(b)). Hence the behvior is deterministic irregrdless of the pcket rrivl time. 3. Overhed of the proposed solution The DFT hrdwre for implementing the trigger is shown in Fig. 5. The trigger signl initites the counter, nd the counter gtes the pcket-redy signl when in test mode. The dely in ing pckets cross the synchronous boundry leds to the introduction of extr idle symbols in the response strem from the DUT. However, this is something thn cn be deterministiclly predicted. Note tht there is minor ltency penlty to be pid for using the trigger scheme (one extr core cycle for ech pcket red). An dditionl drwbck is tht the DUT opertion is not completely norml (b) Actul order of events Pcket b b b b Pcket b Figure 4. Use of the trigger signl to synchronize the reding of pckets into the core domin to eliminte non-determinism We propose the use of trigger signl between the DUT nd the tester tht is nother primry input synchronized to the slow core. Whenever test pcket is to be ed in cross the synchronous Ref Automted Equipment Trigger mode Primry Inputs Primry Outputs Trnsmit Port Tx Tx dt Counter Pcket redy Figure 5. Proposed solution + & Device Under Slow Core

5 functionl mode, but the difference in the logic used in norml nd test mode is miniml. This scheme lso comes t the expense of incresed hrdwre complexity on the DUT. The receive circuitry of the high-speed I/O port of the DUT hs to be modified to relize the proposed solution in test-mode. A counter tht initites the trnsfer of test pckets fixed number of cycles fter the trigger is sserted needs to be implemented. Note tht n extr pin is not required on the DUT to support the trigger signl since one of the primry inputs of the DUT cn be multiplexed internlly to function s the trigger signl in test mode. 4. Anlysis of probbility of non-determinism In this section, we nlyze the probbility of nondeterminism in the output response of the DUT s function of the frequency nd the EPA of the ATE. We ddress the importnt issue of when the problem of non-determinism becomes significnt enough to wrrnt the implementtion of the proposed solution. 4. EPA model Since the EPA of the tester is mesure of the ccurcy with which the tester cn position ny driven edge with respect to n bsolute reference in time, it is possible to model the distribution of the plcement of the driven edge by Gussin distribution bout the reference point [Dll 99]. The EPA of the tester is equl to three times the vrince () of this Gussin distribution. Note tht this trnsltes to very high probbility (greter thn 0.99) tht the driven edge is within ±3 of the reference point. This is illustrted in Fig. 6. Clock Poor EPA Good EPA Reference Figure 6. Gussin distribution for driven edge nd EPA Thus, it is pprent tht high vrince for this distribution corresponds to poor tester EPA nd vice vers. The Gussin distribution for both the (supplied by the ATE) nd the core (of the DUT) cn be used to tbulte the probbility of occurrence of non-determinism s function of both tester EPA nd the speed of opertion of the high-speed I/O port. Note tht the core is derived from the reference which comes directly from the tester nd hence is ffected by the EPA of the tester. 4. Probbility of non-determinism Consider the finl pcket f of n input strem tht is to be ed in with the flling edge A in Fig. 7. The corresponding core cycle in which this pcket will be red from the elsticity buffer will depend on the reltive position of the flling edges A nd A. If, sy, A occurs before A, the pcket will be red into the core domin on core cycle i. However, if A occurs fter A, the pcket will be red into the core domin on core cycle i+. Thus there is one cycle vribility in the core cycle on which the pcket enters the core domin which cn led to non-determinism. As the bsolute time difference between the occurrence of the flling edges A nd A shrinks (nd becomes comprble to the EPA of the tester), the probbility tht the order of occurrence of the flling edges A nd A differs from run to run increses. Slow Core Clock A f A Figure 7. Anlysis of non-determinism Let the bsolute time displcement between the occurrence of the two events A nd A (in the simultion environment) be. σ Rx nd σ core re the vrince of the Rx nd the core probbility distributions (Gussin), respectively. Let the order of events in the simultion environment be A precedes A (A A ). Then, the probbility distribution (Gussin) of the plcement of the edge A (ssumed to occur t n instnt y), reltive to the plcement of the edge A (which is used s the reference, with men µ = 0), is given by: ( y ( )) P ( A = occurs t y) exp σ Rx If the event A occurs t n instnt x, the probbility tht A occurs fter x (nd hence, in n order other thn the simultion predicted one) is given by the integrl: y+ P A occurs fter x ( ) ( ) = exp dy x σ Rx The bove integrl is then evluted over the intervl [-, + ] to compute the totl probbility of interchnge of the events A nd A. Thus: y P A A dy x ( + ) ( = ) exp exp dx x σ Rx σ core When is 0, i.e., when the time difference between the events A nd A in the simultion environment is 0, P(A A ) evlutes to 0.5. We show the vlue of

6 P(A A ) s function of the time difference in the semi-log plot in Fig. 8. Probbility of Non determinism (5ps, 5ps) (00ps, 00ps) (50ps, 50ps) EPA = Core EPA (00ps, 00ps) Displcement (ps) Figure 8. Semi-log plot of P(A A ) s function of displcement. ( EPA, core EPA) vries from (5ps, 5ps) to (00ps, 00ps) To plot the grph in Fig. 8, the EPA of both the Rx nd the core ws vried from 5ps to 00ps. On the X-xis, the displcement ws vried from 0ps to 600ps in increments of ps. For ech pir of vlues of the EPA of the nd the core, the log (bse 0) of the probbility of interchnge of events A nd A s function of incresing displcement is grphed. Note tht the probbility of non-determinism (i.e., P(A A )) diminishes rpidly s the displcement between the events A nd A increses. In ddition, for fixed vlue of, there is significnt increse in the probbility of non-determinism s the EPA becomes less precise. Probbility of Non determinism (50ps, 50ps) ATE supplied EPA = 50ps (50ps, 00ps) (50ps, 00ps) Displcement (ps) Figure 9. Semi-log plot of P(A A ) s function of, when EPA is 50ps nd core EPA vries from 50ps to 00ps Often the ATE hs only limited number of pins tht hve very precise EPA, while the other pins hve less precise EPA. In some cses, it my not be possible to use the very precise EPA pins to drive both the nd the core. In tht cse, the core is driven with less precise EPA. We show semi-log plot in Fig. 9 where the EPA is 50ps while the core EPA vries from 50ps to 00ps. In Fig. 0, the EPA is 5ps while the core EPA vries from 5ps to 00ps. Note tht the probbility of non-determinism is significntly incresed s the core EPA becomes less precise. Probbility of Non determinism (5ps, 50ps) (5ps, 5ps) ATE supplied EPA = 5ps (5ps, 00ps) (5ps, 00ps) Displcement (ps) Figure 0. Semi-log plot of P(A A ) s function of, when EPA is 5ps nd core EPA vries from 5ps to 00ps 4.3 Probbility of non-determinism for the test session Pckets re ltched on both edges of the (since it is DDR). There re severl edges on the during ech core period. The edge tht is nerest the flling edge of the core will hve the smllest displcement (such edges will be referred to s criticl edges). All the other edges during the core period will hve much lrger displcement nd hence negligible probbility of non-determinism. The best-cse vlue for the displcement for the criticl edges is equl to hlf the period of the. Let P nd be the probbility tht pcket on criticl edge cuses non-determinism. Then the probbility of non-determinism for the entire test session is is equl to [ ( P nd ) m ] where m is the totl number of pckets tht re received on criticl edges. Probbility of Non Determinism for Session GHz 0GHz 7GHz 5GHz GHz GHz Edge Plcement Accurcy (ps) Figure. Probbility of non-determinism for test session s function of EPA for different I/O frequencies

7 In Figs. nd, we show the probbility of non-determinism for the entire test session if m is 00 nd the displcement for the criticl edges is equl to hlf the period of the. Figure shows how the probbility of non-determinism for the test session vries with EPA for given I/O frequency. As the I/O frequency continues to increse, the EPA must rpidly improve to keep the probbility of non-determinism low. Probbility of Non Determinism for Session 0.9 (00ps, 00ps) (00ps, 00ps) (50ps, 50ps) (5ps, 5ps) Frequency of I/O Port (GHz) Figure. Probbility of non-determinism for test session s function of I/O frequency for different EPAs Figure shows how the probbility of non-determinism for the test session vries with I/O frequency for given EPA. If tester with prticulr EPA is to be used to test successive genertions of chips, the probbility of non-determinism will rpidly increse s the I/O frequency improves. Tble. Probbility of non-determinism for test session if m = 00 Rx Clk Freq. EPA (Rx Clock, Core Clock) (ps, ps) ps (5, 5) (50, 50) (00,00) (50,50) (00,00) GHz GHz GHz GHz GHz GHz Tble gives the probbility of non-determinism for test session (m = 00) for few exmple cses. As cn be seen from the Tble, if tester with 50ps EPA is used to test chip with 7 GHz I/O port, the probbility of non-determinism is 0.6. This could result in significnt yield loss. From this dt, it is pprent tht s the rpid increse in I/O frequencies continues to outstrip improvements in tester EPA, non-determinism in the output response of the DUT will be significnt problem. The DFT technique presented in this pper cn be used to ddress this problem. 5. Conclusion As the I/O frequencies for high-speed source synchronous differentil buses continue to rise nd ATE EPA becomes reltively less precise, techniques for limiting sources of non-deterministic behvior in the DUT will be needed. In this pper, we hve proposed DFT technique for the elimintion of non-determinism tht rises due to limited ATE EPA in the source synchronous of the stimulus strem to high-speed I/O port from the tester. It llows the ppliction of t-speed functionl ptterns to the DUT while voiding yield loss due to nondeterminism. The proposed DFT scheme requires very smll hrdwre overhed nd trivil increse in test ppliction time. Acknowledgements The uthors would like to thnk Crol Pyron t Motorol for suggesting this topic nd for her help in prepring this pper. This mteril is bsed on work supported in prt by the Ntionl Science Foundtion under Grnt No. MIP References [Agilent 0] Technicl Specifictions, Agilent SOC Series NP-models, Agilent Technologies, 00. [Bouvier 00] Bouvier, D., RpidIO TM : An Embedded System Component Network Architecture, RpidIO TM Trde Assocition, 00. [Dll 99] Dll, W., nd Mio, S., The Vlue of er Accurcy, Proc. Interntionl Conference, pp , 999. [HyperTrnsport 0] HyperTrnsport TM Technology I/O Link: A High Bndwidth I/O Architecture, Advnced Micro Devices, Inc., 00. [Infinibnd 0] Infinibnd TM Architecture Specifiction, Vols. nd, Infinibnd TM Trde Assocition, 00. [ITRS 0] The Interntionl Technology Rodmp for Semiconductors, nd Equipment, 00. [Jenicke 0] Jenicke, R., RpidIO rises PCI stture in the box, EETIMES, April 00. [Keezer 0] Keezer, D. C., Zhou, Q., Bir, C., Kun, J., nd Poole, B., Terbit-per-second Automted Digitl ing, Proc. Interntionl Conference, pp. 43-5, 00. [Mxwell 00] Mxwell, P., Hrtnto, I., nd Bentz, L., Compring functionl nd structurl tests, Proc. Interntionl Conference, pp , 000. [Oshim 0] Oshim, A., Ponitowski, J., nd Nomur, T., Pin Electronics IC for High Speed Differentil Devices, Proc. Interntionl Conference, pp 8-33, 00. [Schlumberger 0] Technicl Specifictions, ITS9000ZX System, Schlumberger Semiconductor Solutions, 00. [Terdyne 00] Technicl Specifictions, J VLSI System, Terdyne, Inc., 000.