IP MACRO Datasheet Rev 1.0 Process: 65nm CMOS. Figure 1. PMCC_REFS Block Diagram

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1 Band-gap Reference IP MACRO Datasheet Rev 1.0 Process: 65nm CMOS DESCRIPTION The IP block combines two modules of GM current references and one module of BG (band-gap) current reference. Each module provides up to twelve of each: 50µA, 20µA and 10µA stabilized current outputs. The Band-gap reference and one of the GM references provide output current proportional to 1/Rinternal. Another GM referenced provides output current proportional to 1/Rexternal. The biasing currents are programmable within +/-30% permitting the block parameter changing, power minimization for given performance or operational margin estimation in production. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement. FEATURES Band-gap and GM currents Currents proportional to 1/Rint and 1/Rext 12 of each outputs: 50µA, 20µA and 10µA 106 independent current outputs Fast start up Low power consumption (0.6mW) Stand-by mode 1.2V Power Supply Adjustable (+/-30%) output current APPLICATIONS Analog, mixed-signal, RF ICs and ASICs Figure 1. Block Diagram 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 1 of 9

2 VDD OUT VSS Figure 2. REF_GM module equivalent schematics VDD OUT VSS Figure 3. REF_BG module equivalent schematics Table 1. Pin Descriptions Name Pin # Description Type i_ref_dn Biasing current adjustment polarity switch DI i_ref_ctrl<1:0> Biasing current adjustment DI i_pd Power down DI IGM50U_0<1:12>, IGM50U_1<1:12> IGM20U_0<1:12>, IGM20U_1<1:11> IGM10U_0<1:12>, IGM10U_1<1:12> 50µA reference current output AO 20µA reference current output AO 10µA reference current output AO IBG50U<1:12> 50µA reference current output (temperature compensated) AO IBG20U<1:12> 20µA reference current output (temperature compensated) AO IBG10<1:10> 10µA reference current output (temperature compensated) AO REXT_GM B2 Connection pad for GM reference external resistor. Connect 3.5kΩ resistor to this pad VSS_SENSE A2 RX ground return path for external resistor of the GM reference block AI VDD B1 1.2V analog power supply PW VSS A1 Common node for analog blocks GD Note: AO Analog output, AI Analog input, DI digital input, PW power, GD ground/common. 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 2 of 9 AI

3 Table 2. Electrical absolute maximum ratings Description Min Max Units Power supply VDD V Junction temperature ºC End Of Life (EOL) 10 years DC Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. DC Electrical Specifications Parameter Min Typ Max Units Notes Power Supply Power Supply (VDD) V Power Supply Current Consumption ma Inputs Logic control high level V Logic control low level V IGM_0 (with external resistor) Current Reference Outputs Current Accuracy % Over process corners Output Impedance kω 0.2V to 0.8V, 50µA current output Noise 188 pa/ Hz f = 10kHz IGM_1 (with internal resistor) Current Reference Outputs Output Impedance kω 0.2V to 0.8V, 50µA current output Noise 188 pa/ Hz f = 10kHz IBG Current Reference Outputs Current Accuracy over temperature ±0.35 ±0.6 % Temperature change -25 to 125 Output Impedance kω 0.2V to 0.8V, 50µA current output Temperature Drift 51 ppm/ C Noise 238 pa/ Hz f = 10kHz NOTE: Main operation mode. 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 3 of 9

4 Table 4. Reference Current Adjustment Truth Table i_ref_ctrl<0> i_ref_ctrl<1> i_ref_dn i_pd Current Adjustment, % Figure 4. Macro schematic symbol Figure 5. Bump-out diagram 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 4 of 9

5 Output current, µa Output current, µa Output current, µa IGM Current Reference With External Resistor max typical min Temperature, ºC IGM Current Reference With Internal Resistor Temperature, ºC 65 IBG Current Reference max typical min max typical min Temperature, ºC Figure 6. 50µA output current dependency vs temperature (typical and marginal corners) 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 5 of 9

6 Output current, µa Outputs Current vs Outputs Voltage, T=75ºC IGM50U_0 IGM50U_1 IBG50U Output voltage, V Figure 7. Outputs current dependency on outputs voltage (50µA current output, T=75 C) Figure 8. Reference current adjustment (T=75 C) 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 6 of 9

7 Figure 9. Output current reaction to voltage changes of the power supply 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 7 of 9

8 Figure 10. IP block simulation and test schematics 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 8 of 9

9 MACRO LAYOUT VIEW macro layout is optimally designed taking symmetry, parasitic capacitances, inductance and reliability into account. Layout design leverages all 8 metal layers available in the IBM10LPE process 5_01_00_01_LD metal stack. Compact layout ensures minimum parasitic capacitance, inductance, device mismatch and minimum die area. Layout considerations for macro integration: OA metal is used for ground connections to minimize ground bounce effects. BA metal is used for VDD connection. Other layout features incorporated by customer into or adjacent to macro can affect macro performance and should be carefully analyzed. Upon request, PMCC can provide IP for different metal stack, can change the macro block shape or migrate the macro block to different process. Figure 11. IP macro layout view. Some of the details and/or layers might be omitted. Layout size is 414μm x 323μm. Table 4. Version Control Revision Date Author Changes V1.0 05/18/10 PMCC Initial version of the document 2010Pacific Microchip Corp. Specifications are subject to change without notice. No circuit patents licenses are implied. Page 9 of 9