Student s Handbook B.Tech (EEE VI Sem)

Transcription

1 2018 Student s Handbook B.Tech (EEE VI Sem) Subject Power System Analysis Control System Power Electronics VLSI Circuit Design Data Structure Using C++ Principle of Management 18

2 Student s Handbook B.Tech (EEE VI Sem) 2018 FOREWORD Dear Student, We, at DBGI, are committed to facilitate all aspiring students in their selection of different streams of B.Tech. by putting our efforts in terms of commitment, providing the services of quality and skill oriented education. The exponential expansion in the field of technology has offered a plethora of job opportunities in emerging sectors. It has also resulted in innumerable demand for qualified skilled manpower in these sectors. At this crossroads of your life where a wrong turn can take you miles away from your goal. Choosing your career path is an important step because your future is at stake. It is generally observed that a large section of students are unaware of what they want to achieve in their life. This amounts to a situation like boarding a train without knowing one s destination. Undoubtedly it may result in waste of precious time and money. Student Handbook is purposely designed for the students. We have been planning for some time to provide collective information about academics as well as Institute to our new comers. It comprises complete information of syllabi of all subjects, Lecture Plans, assignments, question bank, tutorials, marking scheme etc. However in addition to this, if students have any problem or query they can contact Student Information Cell. We are living in a competitive world; the key to edging out of competition is information and preparation. We hope that this booklet gives you enough leverage to understand about the institute and academics. Success to a large extent depends on your attitude which includes your sincerity and strong will to vigorously pursue your goal. It s your determination to fulfill the requirements that are needed to enable you achieve your goal. It means you have to acquire the required academic qualification and skills followed by professional qualification and training in your particular field. Once you have these, you will be able to compete. With Best Wishes Mr. Rohit Dobriyal (C.O.D) Department of Electrical & Electronics Engg. Dev Bhoomi Group of Institutions

3 Student s Handbook B.Tech (EEE VI Sem) 2018 CONTENTS 1 Evaluation Scheme 2 Syllabus 2.1 Power System Analysis 2.2 Control System 2.3 Power Electronics 2.4 VLSI Circuit Design 2.5 Data Structure Using C Principle of Management 2.7 Control System Lab 2.8 Power Electronics Lab 2.9 Data Structure Using C++ Lab 2.10 Discipline 3 Lesson Plan 3.1 Power System Analysis 3.2 Control System 3.3 Power Electronics 3.4 VLSI Circuit Design 3.5 Data Structure Using C Principle of Management 4 Assignment 4.1 Power System Analysis 4.2 Control System 4.3 Power Electronics 4.4 VLSI Circuit Design 4.5 Data Structure Using C Principle of Management 5 Tutorial 5.1 Power System Analysis 5.2 Control System 5.3 Power Electronics 5.4 VLSI Circuit Design 5.5 Data Structure Using C Principle of Management 6 Question Bank 6.1 Power System Analysis 6.2 Control System 6.3 Power Electronics 6.4 VLSI Circuit Design 6.5 Data Structure Using C Principle of Management

4 Student s Handbook B.Tech (EEE VI Sem) Evaluation Scheme

5 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Title: ANALYSIS Course Level: Beginner Course Type: Credit: 4 Core Total Contact Hours: 40 LTP External Marks/Internal Marks: 100/50 POWER SYSTEM Course Code: TEE-601 Duration of External Exam: 3 Hours Prerequisite: Knowledge of Elements of power system Unit I: (10L) Representation of power system components: Synchronous machines, Transformers, Transmission lines, One line diagram, Impedance and reactance diagram, per unit system. Symmetrical Components: Symmetrical components of unbalanced phasors, power in terms of symmetrical components, sequence impedances and sequence networks. Symmetrical fault analysis: Transient in R-L series circuit, calculation of 3-phase short circuit current and reactance of synchronous machines, internal voltage of loaded machines under transient conditions. Unit II: (8L) Analysis of single line to ground fault, line to line fault and double line to ground fault on an unloaded generator and power system network with and without fault impedance. Formation of Zbus using singular transformation and algorithm, computer method for short circuit calculations. Unit III: (8L) Load flows: Introduction, bus classifications, nodal admittance matrix (YBUS), development of load flow equations, load flow solution using Gauss Siedel and Newton-Raphson method, approximation to N-R method, line flow equation and fast decoupled method. Unit IV: (8L) Power system Stability: Stability and stability limit, steady state stability study, derivation of Swing equation, transient stability studies by equal area criterion and step by step method. Factors affecting steady sate and transient stability and methods of improvement. Unit V: (6L) Wave equation for uniform transmission lines, velocity propagation, surge impedance, reflection and transmission of traveling waves under different line loadings, Bewlay s Lattice diagram, protection of equipments and line against traveling waves. Reference Books: 1. L.P. Singh, Advanced Power System Analysis & Dynamics, New Age International 2. Hadi Sadat, Power System Analysis, Tata Mc Graw Hill. A.R. Bergen and V. Vittal, Power System Analysis, Pearson Publication. Course Outcome CO1 CO2 CO3 CO4 CO5 Description Principles in the modelling and analysis of power systems subject to symmetrical and unsymmetrical faults To study implementation of symmetrical components for the analysis of unbalanced system To understand the various computer methods for load flow solution. Understanding the effect of faults on the stability of the system and methods to improve it To study the concept of travelling waves in the transmission lines.

6 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Title: SYSTEM Course Level: Course Type: Credit: 4 Intermediate Core Total Contact Hours: 40 LTP External Marks/Internal Marks: 100/50 CONTROL Course Code: TEE602 Duration of External Exam: 3 Hours Prerequisite: Knowledge of system engineering Unit I: (7L) The Control System: Open loop & closed control; servomechanism, Physical examples. Transfer functions, Block diagram algebra, Signal flow graph, Mason s gain formula Reduction of parameter variation and effects of disturbance by using negative feedback Unit II: (8L) Time Response analysis: Standard test signals, time response of first and second order systems, time response specifications, steady state errors and error constants Design specifications of second order systems: Derivative error, derivative output, integral error and PID compensations, design considerations for higher order systems, performance indices Unit III: (8L) Control System Components: Constructional and working concept of ac servomotor, synchros and stepper motor Stability and Algebraic Criteria concept of stability and necessary conditions, Routh-Hurwitz criteria and limitations Root Locus Technique: The root locus concepts, construction of root loci Unit IV: (9L) Frequency response Analysis: Frequency response, correlation between time and frequency responses, polar and inverse polar plots, Bode plots Stability in Frequency Domain: Nyquist stability criterion, assessment of relative stability: gain margin and phase margin, constant M&N circles Unit V: (8L) Introduction to Design: The design problem and preliminary considerations lead, lag and lead-lag networks, design of closed loop systems using compensation techniques in time domain and frequency domain. Reference Books: 1. Norman S. Mise, Control System Engineering 4th edition, Wiley Publishing Co. 2. M.Gopal, Control System; Principle and design, Tata McGraw Hill. 3. M.Gopal, Modern Control system, Tata McGraw Hill. 4. D.Roy Choudhary, Modern Control Engineering, Prentice Hall of India. Course Outcome CO1 CO2 CO3 CO4 CO5 Description Acquire a working knowledge of system science-related mathematics Determine the response of different order systems for various inputs signal Analysis of stability & criteria for which the system is stable for different system Analysis and correlation between the time domain and frequency domain analysis To study the concept of designing using various techniques

7 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Level: Course Type: Credit: 4 Intermediate Core Total Contact Hours: 40 LTP External Marks/Internal Marks: 100/50 Course Title: POWER Course Code: TEE-603 Duration of External Exam: 3 ELECTRONICS Hours Prerequisite: Knowledge of Network Analysis & Synthesis Unit I: (7L) Power semiconductor devices: Power semiconductor devices their symbols and static characteristic, characteristics and specifications of switches, type of power electronic circuits, Thyristor operation, V-I characteristic, two transistor model, methods of turn-on operation of GTO, MCT and TRIAC. Unit II: (8L) Power semiconductor devices (contd): protection of devices, series and parallel operation of thyristors, commutation techniques of thyristor. DC-DC convertors: Principles of step -down chopper, step down chopper with R-L load, principle of step up chopper, and operation with R-L load, classification of choppers. Unit III: (9L) Phase controlled converters: Single phase half wave controlled rectifier with resistive and inductive loads, effect of freewheeling diode, single phase fully controlled and half controlled bridge converters. Performance parameters, three phase half wave converters, three phase fully controlled and half controlled bridge converters, Effect of source inductance, single phase and three phase dual converters. Unit IV: (9L) AC Voltage controllers: Principle of on-off and phase controls, single phase ac voltage controller with resistive and inductive loads, three phase ac voltage controllers (various configuration and comparison). Cyclo converters: Basic principle of operation, single phase to single phase, three phase to single phase and three phase to three phase cyclo converters, output voltage equation. Unit V: (7L) Inverters: Single phase series resonant inverter, single phase bridge inverters, three phase bridge inverters, introduction to & mode of operation, voltage control of inverters, harmonics reduction techniques, single phase and three phase current source inverters. Reference Books: 1. M.S. Jamil Asghar, Power Electronics Prentice Hall of India Ltd., A. Chakrabarti, Rai & Co. Fundamental of Power Electronics & Drives Ghanpat Rai & Co. 3. K. Hari Babu, Power Electroncis Switch Publications. Course Outcome CO1 CO2 CO3 CO4 CO5 Description To understand the importance of power electronics in field of industries and introduction of various power electronic devices Familiarization of commutation techniques and the principle of buck & boost converter understand the working of various types of converter To describe various ac voltage controllers and get an insight of the working principle of cycloconverters To get and overview of inverter application.

8 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Title: DESIGN Course Level: Course Type: Credit: 4 Intermediate Cross Deptt. Total Contact Hours: 40 LTP External Marks/Internal Marks: 100/50 VLSI CIRCUIT Course Code: TEC602 Duration of External Exam: 3 Hours Prerequisite: Knowledge of VLSI Technology UNIT 1 (7L) REVIEW: Current conduction in MOSFET, Electrical Properties of MOS and BiCMOS, The Pass Transistor, CMOS. UNIT 2 (10L) CMOS Inverter: Static CMOS inverter, layout, switching threshold and noise margin concepts and their evaluation,dynamic behavior, power consumption. NMOS MOS pass transistor inverter. COMBINATIONAL LOGIC: Static CMOS design, rationed logic, pass transistor logic, dynamic logic, cascading dynamic gates, CMOS transmission gate logic. UNIT 3 (9L) SEQUENTIAL LOGIC: Static latches and registers, bi-stability principle, MUX based latches, static SR flip-flops, master-slave edge-triggered register, dynamic latches and registers, concept of pipelining, Timing issues. UNIT 4 (7L) MEMORY AND ARRAY STRUCTURE: ROM, RAM, peripheral circuitry, memory reliability and yield, SRAM and DRAM design, flash memory, PLA,PAL, FPGA. UNIT 5 (7L) DESIGN FOR TESTABILITY: Logic Testing, sequential Logic Testing, Guidelines to be adopted in Design for Test, Scan Designing Techniques, Built-In self Test(BIST)Techniques. REFERENCE BOOKS: 1. Basic VLSI Design by D.A. Pucknell & Eshraghian (PHI) 2. Modern VLSI Design Systems on Silicon by Wayne Wolf (Pearson Pub.) 3. R. K. Singh «VLSI DESIGN (With VHDL), Kataria &Sons», 2 nd Edition, Course Outcome CO1 CO2 CO3 CO4 CO5 Description Analyze various IC Designing Phase involved in IC Designing through designing Flow chart Designing of various Digital System using CMOS Mosfet with different scaling. Design a combinational circuit for any complex problems and implement it using MOS/Transmission gate/cpl Apply the knowledge of CMOS technology to design a sequential circuit for any problems which can be simplified using Boolean algebra and draw the lay out using any modern tool. Evaluate how GaAs technology enhances the performance of the digital device design.

9 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Level: Course Type: Credit: 4 Intermediate Cross Deptt. Total Contact Hours: 40 LTP External Marks/Internal Marks: 100/50 Course Title: DATA Course Code: TCS607 Duration of External Exam: 3 STRUCTURES USING C++ Hours Prerequisite: knowledge of fundamentals of computer programming UNIT 1 (7L) COMPLEXITY ANALYSIS: Time and Space complexity of algorithms, asymptotic analysis, big O and other notations, importance of efficient algorithms, program performance measurement, data structures and algorithms. LINEAR LISTS: Abstract data type, sequential and linked representations, comparison of insertion, deletion and search operations for sequential and linked lists, list and chain classes, exception and iterator classes for lists, doubly linked lists, circular lists, linked lists through simulated pointers, lists in STL, skip lists, applications of lists in bin sort, radix sort, sparse tables. UNIT 2 (7L) STACKS AND QUEUES: Abstract data types, sequential and linked implementations, exception handling in classes, representative applications such as parenthesis matching, towers of Hanoi, wire routing in a circuit, finding path in a maze, simulation of queuing systems, equivalence problem. UNIT 3 (7L) HASHING: Search efficiency in lists and skip lists, hashing as a search structure, hash table, collision avoidance, linear open addressing, chains, uses of hash tables in text compression, LZW algorithm. UNIT 4 (7L) TREES: Binary trees and their properties, terminology, sequential and linked implementations, tree traversal methods and algorithms, heaps as priority queues, heap implementation, insertion and deletion operations, heapsort, heaps in Huffman coding, leftist trees, tournament trees, use of winner trees in mergesort as an external sorting algorithm, bin packing. UNIT 5 (7L) GRAPHS: Definition, terminology, directed and undirected graphs, properties, connectivity in graphs, applications, implementation adjacency matrix and linked adjacency chains, graph traversal breadth first and depth first, spanning trees. REFERENCE BOOKS: 1. T. H. Cormen, C. E. Leiserson, R. L. Rivest and C. Stein, Introduction to Algorithms, MIT Press, Aho, J. E. Hopcroft and J. D. Ullman, The Design and Analysis of Computer Algorithms, Addison- Wesley, M. T. Goodrich and R. Tamassia, Algorithm Design: Foundations, Analysis and Internet Examples, John Wiley & Sons, Course Outcome CO1 CO2 CO3 CO4 CO5 Description Ability to develop programs to implement linear data structures such as stacks, queues, linked lists To understand the concept of queuing system and its simulation To introduce the concept of hashing and its application Application of trees and graphs in real world scenarios Implementation of sorting and searching algorithms.

10 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Level: Beginner Course Type: Credit: 2 Cross Deptt. Total Contact Hours: 30 LTP External Marks/Internal Marks: 50/25 Course Title: PRINCIPLES Course Code: THU608 Duration of External Exam: 2 OF MANAGEMENT Hours UNIT 1 (6L) INTRODUCTION TO MANAGEMENT: Theories of management: Traditional behavioral, contingency and systems approach. Organization as a system. UNIT 2 (8L) MANAGEMENT INFORMATION: Interaction with external environment. Managerial decision making and MIS. UNIT 3 (8L) PLANNING APPROACH TO ORGANIZATIONAL ANALYSIS: design of organization structure; job design and enrichment; job evaluation and merit rating. UNIT 4 (8L) MOTIVATION AND PRODUCTIVITY: Theories of motivation, leadership styles and managerial grid. Co-ordination, monitoring and control in organizations. Techniques of control. Japanese management techniques. Case studies. REFERENCE BOOK: 1. Hirschey: Managerial Economics, Cengage Learning. 2. T. R. Banga and S.C. Sharma: Industrial Organisation and Engineering Economics, Khanna Publishers. 3. O.P. Khanna: Industrial Engineering and Management, Dhanpat Rai. 4. Joel Dean: Managerial Economics, PHI learning. Course Outcome CO1 CO2 CO3 CO4 Description Knowledge of Management principles To develop decision making skills of the students Planning approach to organizational behavior Developing leadership skills among students

11 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Title: SYSTEM LAB Course Level: Beginner Course Type: Credit: 2 Core Total Contact Hours: 20 LTP External Marks/Internal Marks: 25/25 CONTROL Course Code: PEE652 Duration of External Exam: 1 Hr : Note: The minimum of 10 experiments are to be performed from the following, out of which at least three should be software based. 1. To determine response of first order and second order systems for step input for various values of constant K using linear simulator unit and compare theoretical and practical results. 2. To study P, PI and PID temperature controller for an oven and compare their performance. 3. To study and calibrate temperature using resistance temperature detector (RTD) 4. To design Lag, Lead and Lag-Lead compensators using Bode plot. 5. To study DC position control system 6. To study synchro-transmitter and receiver and obtain output V/S input characteristics 7. To determine speed-torque characteristics of an ac servomotor. 8. To study performance of servo voltage stabilizer at various loads using load bank. 9. To study behaviour of separately excited dc motor in open loop and closed loop conditions at various loads. 10. To study PID Controller for simulation proves like transportation lag. Software based experiments (Use MATLAB, LABVIEW software etc.) 11. To determine time domain response of a second order system for step input and obtain performance parameters. 12. To convert transfer function of a system into state space form and vice-versa. 13. To plot root locus diagram of an open loop transfer function and determine range of gain k for stability. 14. To plot a Bode diagram of an open loop transfer function. 15. To draw a Nyquist plot of an open loop transfer functions and examine the stability of the closed loop system.

12 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Level: Beginner Course Type: Credit: 2 Core Total Contact Hours: 20 LTP External Marks/Internal Marks: 25/25 Course Title: POWER Course Code: PEE653 Duration of External Exam: 1 ELECTRONICS LAB Hr Note: The minimum of 10 experiments is to be performed out of which at least three should be software based. 1. To study V-I characteristics of SCR and measure latching and holding currents. 2. To study UJT trigger circuit for half wave and full wave control. 3. To study single-phase half wave controlled rectified with (i) resistive load (ii) inductive load with and without freewheeling diode. 4. To study single phase (i) fully controlled (ii) half controlled bridge rectifiers with resistive and inductive loads. 5. To study three-phase fully/half controlled bridge rectifier with resistive and inductive loads. 6. To study single-phase ac voltage regulator with resistive and inductive loads. 7. To study single phase cyclo-converter 8. To study triggering of (i) IGBT (ii) MOSFET (iii) power transistor 9. To study operation of IGBT/MOSFET chopper circuit 10. To study MOSFET/IGBT based single-phase series-resonant inverter. 11. To study MOSFET/IGBT based single-phase bridge inverter. Software based experiments(pspice/matlab) 12. To obtain simulation of SCR and GTO thyristor. 13. To obtain simulation of Power Transistor and IGBT. 14. To obtain simulation of single phase fully controlled bridge rectifier and draw load voltage and load current waveform for inductive load. 15. To obtain simulation of single phase full wave ac voltage controller and draw load voltage and load current waveforms for inductive load. 16. To obtain simulation of step down dc chopper with L-C output filter for inductive load and determine steady-state values of output voltage ripples in out put voltage and load current.

13 Dev Bhoomi Institute Of Technology SEMESTER: VI Course Level: Beginner Course Type: Credit: 2 Cross Deptt. Total Contact Hours: 20 LTP External Marks/Internal Marks: 15/10 Course Title: DATA Course Code: PCS657 Duration of External Exam: 1 STRUCTURE LAB Hr Problems in "C++" using Data Structures involving arrays, stacks, queues, strings, linked lists, trees, graphs. 1) Using STACK to check matching left and right characters such as parantheses, curly braces and square brackets in a given string. 2) Single server queuing system and gathering statistics. 3) Operations on Stacks. 4) Sparse Matrices 5) Linear linked list implementation 6) Operations on Doubly Linked List and Circular List with a test application 7) Operations on Ordered Binary Trees. 8) GraphTraversal Techniques 9) Implementation of Quicksort, Mergesort and Heapsort 10) Operations on Binary Trees 11) Shortest Path Problem

14 Student s Handbook B.Tech (EEE VI Sem) Lesson Plan 3.1 Power System Analysis DBIT DEHRADUN LESSON PLAN SEMESTER/YEAR: 5 th /3 rd DEPARTMENT: EEE COURSE: Power System Analysis CODE: TEE-601 Referenc No. Of Delivery Remar S. Topic Name e/ Text Lectur Method ks No. Book/ es Web (R/T/W) 1. Representation of power system components: T1,R1 2 Chalk & Talk Synchronous machines 2. Transformers, Transmission lines, One line diagram, T1,R1 2 Chalk & Talk Impedance and reactance diagram 3. Per unit system T1,R2 2 Chalk & Talk 4. Symmetrical components of unbalanced phasors T1,R1 2 Chalk & Talk 5. Power in terms of symmetrical components T1,R1 2 Chalk & Talk 6. Sequence impedances and sequence networks T1 2 Chalk & Talk 7. Transient in R-L series circuit T1,R1 2 Chalk & Talk 8. Calculation of 3-phase short circuit current T1,R1 2 Chalk & Talk 9. Reactance of synchronous machines T1,R1 2 Chalk & Talk 10. Internal voltage of loaded machines under transient T1,R1 2 Chalk & Talk conditions 11. Analysis of single line to ground fault T1,R1 2 Chalk & Talk 12 Line to line fault and double line to ground fault on an T1,R1 3 Chalk & Talk unloaded generator 13. Power system network with and without fault impedance T1,R1 2 Chalk & Talk 14. Formation of Zbus using singular transformation and T1 2 Chalk & Talk algorithm 15. Computer method for short circuit calculations T1,R1 2 Chalk & Talk 16. Load flows: Introduction, bus classifications T1,R1 1 Chalk & Talk 17. Nodal admittance matrix (YBUS) T1,R1 2 Chalk & Talk

15 Student s Handbook B.Tech (EEE VI Sem) Development of load flow equations T1,R1 2 Chalk & Talk 19. Load flow solution using Gauss Siedel T1,R1 2 Chalk & Talk 20. Approximation to N-R method T1 2 Chalk & Talk 21. Line flow equation and fast decoupled method T1,R1 2 Chalk & Talk 22. Power system Stability: Stability and stability limit T1 1 Chalk & Talk 23. Steady state stability study T1,R1 2 Chalk & Talk 24. Derivation of Swing equation T1 2 Chalk & Talk 25. Transient stability studies by equal area criterion and step T1,R1 2 Chalk & Talk by step method 26. Factors affecting steady sate and transient stability and T1 2 Chalk & Talk methods of improvement 27. Wave equation for uniform transmission lines T1 2 Chalk & Talk 28. Velocity propagation T1 1 Chalk & Talk 29. Surge impedance T1 1 Chalk & Talk 30. Reflection and transmission of traveling waves under T1 2 Chalk & Talk different line loadings 31. Bewlay s Lattice diagram T1 2 Chalk & Talk 32. Protection of equipments and line against traveling waves T1,R1 2 Chalk & Talk Total Lectures: 52 TEXT BOOKS: [T1] B.R. Gupta, Power System Analysis, S.Chand REFERENCE BOOKS: [R1] L.P. Singh, Advanced Power System Analysis & Dynamics, New Age International [R2] C.L.Wadhwa, Power System Analysis,New Age International Publication.

16 Student s Handbook B.Tech (EEE) Control System SEMESTER/YEAR: 6 th /3 rd COURSE: CONTROL SYSTEM DBIT DEHRADUN LESSON PLAN DEPARTMENT: EEE CODE:TEE-602 Reference/ No. Of Delivery Remarks S. Topic Name Text Book/ Lectures Method No. Web (R/T/W) 1. Control System R1&T1 2 Chalk & Talk 2. Open loop & closed control R2&T1 1 Chalk & Talk 3. servomechanism R2&T2 1 Chalk & Talk 4. Physical examples R1&T3 2 Chalk & Talk 5. Transfer functions R1&T2 1 Chalk & Talk 6. Block diagram algebra, R2&T3 2 Chalk & Talk 7. Signal flow graph, R2&T3 2 Chalk & Talk 8. Mason s gain formula R1&T1 1 Chalk & Talk 9. Reduction of parameter variation and effects of R1&T2 1 Chalk & Talk disturbance by using negative feedback UNIT 2- Time Response analysis 10. Standard test signals, R2&T2 1 Chalk & Talk 11. time response of first and second order systems, R1&T1 2 Chalk & Talk 12 time response specifications, R2&T1 2 Chalk & Talk 13. steady state errors and error constants R2&T2 1 Chalk & Talk 14. Design specifications of second order systems: R1&T3 2 Chalk & Talk 15. Derivative error, derivative output R1&T1 2 Chalk & Talk 16. Integral error and PID compensations, R2&T1 2 Chalk & Talk 17. design considerations for higher order systems, R1&T3 1 Chalk & Talk performance indices UNIT 3 - Control System Components: 18. Constructional and working concept of ac servomotor, R1&T3 1 Chalk & Talk synchros and stepper motor 19. Stability and Algebraic Criteria R1&T1 2 Chalk & Talk 20. concept of stability and necessary conditions R2&T2 2 Chalk & Talk

17 Student s Handbook B.Tech (EEE) Routh- Hurwitz criteria and limitations R1&T2 2 Chalk & Talk 22 Root Locus Technique: The root locus concepts, R2&T2 2 Chalk & Talk 23 construction of root loci R1&T1 2 Chalk & Talk UNIT 4- Frequency response Analysis 24 Frequency response, R2&T1 2 Chalk & Talk 25 correlation between time and frequency responses, R2&T2 2 Chalk & Talk 26 polar and inverse polar plots, R1&T3 2 Chalk & Talk 27 Bode plots Stability in Frequency Domain: R1&T1 3 Chalk & Talk 28 Nyquist stability criterion, R2&T1 2 Chalk & Talk 29 assessment of relative stability: gain margin and phase R1&T3 2 Chalk & Talk margin, 30 constant M&N circles R1&T3 1 Chalk & Talk UNIT 5 - Introduction to Design: 31 The design problem and preliminary considerations lead, R1&T1 2 Chalk & Talk lag and lead-lag networks, 32 design of closed loop systems using compensation R2&T2 3 Chalk & Talk techniques in time domain 33 design of closed loop systems using compensation R1&T2 3 Chalk & Talk techniques in frequency domain. Total Lectures: 59 TEXT BOOKS: [T1] Control system-hasan saeed. [T2] Automatic control system-k.k singh. [T3] Control system engineering-r.ananda natrajana. REFERENCE BOOKS: [R1] Norman S. Mise, Control System Engineering 4th edition, Wiley Publishing Co. [R2] M.Gopal, Control System; Principle and design, Tata McGraw Hill. [R3] M.Gopal, Modern Control system, Tata McGraw Hill. [R4] D.Roy Choudhary, Modern Control Engineering, Prentice Hall of India.

18 Student s Handbook B.Tech (EEE) Power Electronics DBIT DEHRADUN LESSON PLAN SEMESTER/YEAR: 6 th /3 rd DEPARTMENT: EEE COURSE: POWER ELECTRONICS CODE: TEE-603 Referenc No. Of Delivery Remar S. Topic Name e/ Text Lectur Method ks No. Book/ es Web (R/T/W) 1. Introduction to Power semiconductor devices T1,R1 2 Chalk & Talk 2. Power semiconductor devices, their symbols and T2,R1 2 Chalk & Talk static characteristic 3. Characteristics and specifications of switches T1,T2 2 Chalk & Talk 4. Type of power electronic circuits T1,R3 2 Chalk & Talk 5. Thyristor operation, V-I characteristic T1,R2 1 Chalk & Talk 6. Two transistor model T1,R3 1 Chalk & Talk 7. Protection of devices, series and parallel operation T1,T4 2 Chalk & Talk of thyristors 8. Commutation techniques of thyristor T1,R1 3 Chalk & Talk 9. DC-DC convertors:principles of step-down chopper, T1,R2 2 Chalk & Talk step down chopper with R-L load 10. Principle of step up chopper, and operation with R-L T1,R3 2 Chalk & Talk load 11. Classification of choppers T1,R4 2 Chalk & Talk 12 Single phase half wave controlled rectifier with T1,R2 2 Chalk & Talk resistive and inductive loads, effect of freewheeling diode 13. Single phase fully controlled and half controlled T1,T3 2 Chalk & Talk bridge converters 14. Performance parameters three phase half wave T1,T3 2 Chalk & Talk converters 15. Three phase fully controlled and half controlled T1,R4 3 Chalk & Talk bridge converters 16. Effect of source inductance, single phase and three T1,R1 2 Chalk & Talk phase dual converters 17. AC Voltage controllers:principle of on-off and T1,R3 1 Chalk & Talk phase controls 18. Single phase ac voltage controller with resistive and T1,T2 1 Chalk & Talk

19 Student s Handbook B.Tech (EEE) 2018 inductive loads 19. Three phase ac voltage controllers (various T2,T3 2 Chalk & Talk configuration and comparison) 20. Cyclo converters:basic principle of operation single T3,R4 1 Chalk & Talk phase to single phase 21. Three phase to single phase and three phase to three T2,R1 3 Chalk & Talk phase cyclo converters 22. Output voltage equation T1,T3 2 Chalk & Talk 23. Single phase series resonant inverter T2,R3 2 Chalk & Talk 24. Single phase bridge inverters T1,T2 1 Chalk & Talk 25. Three phase bridge inverters T1,R1 2 Chalk & Talk 26. Introduction to 120 & 180 degree mode of T1,T2 3 Chalk & Talk operation,voltage control of inverters 27. Harmonics reduction techniques T1,T2 2 Chalk & Talk 28. Single phase and three phase current source T1,T3 2 Chalk & Talk inverters Total Lectures: 54 TEXT BOOKS: [T1] P.S.Bhimbra, Power Electronics ;Khanna Publications. [T2] Muhammad H. Rashid Power electronics-circuits,devicers and Applications Pearson Publication. [T3] G.K.Dubey Thyristor Power Controllers New Age International Publication. REFERENCE BOOKS: [R1]. Philip T. Krein Elements of Power Electronics Oxford Publication. [R 2]. Robert W. Erickson Fundamentals of Power Electronics Springer International Publication. [R3]. V.R.Moorthi Power Electronics- Devices, Circuits and Industrial Applications Oxford Publication. [R4]. Jacob Power Electronics- Principles and Applications Cengage Learning.

20 3.4 VLSI Circuit Design Student s Handbook B.Tech (EEE) 2018 DBIT DEHRADUN LESSON PLAN SEMESTER/YEAR: 6 TH /3 RD DEPARTMENT: ECE COURSE: VLSI Design CODE: TEC-602 Referenc No. Of Delivery Remar S. Topic Name e/ Text Lectur Method ks No. Book/ es Web (R/T/W) 1. Current conduction in MOSFET, T1,R1 3 Chalk & Talk 2. Electrical Properties of MOS T1,R1 3 Chalk & Talk 3. Electrical Properties of BiCMOS T1,T2 2 Chalk & Talk 4. The Pass Transistor T1,R1 2 Chalk & Talk 5. CMOS T1,R1 3 Chalk & Talk 6. CMOS Inverter: Static CMOS inverter T1,T2 3 Chalk & Talk 7. layout, switching threshold and noise margin concepts and T1,R1 2 Chalk & Talk their evaluation 8. Dynamic behavior, power consumption T1,R1 2 Chalk & Talk 9 NMOS MOS pass transistor inverter. T1,R1 2 Chalk & Talk 10. COMBINATIONAL LOGIC: Static CMOS design, T1,R1 1 Chalk & Talk rationed logic,, 11. Pass transistor logic, dynamic logic T1,R1 2 Chalk & Talk 12 Cascading dynamic gates, CMOS transmission gate logic. T1,R1 2 Chalk & Talk 13. Sequential Logic: Static latches and registers T1,R1 3 Chalk & Talk 14. Bi- stability principle, MUX based latches T1,T2 2 Chalk & Talk 15. Static SR flip-flops, master-slave edge-triggered register T1,R1 2 Chalk & Talk 16 Dynamic latches and registers T Concept of pipelining,timing issues. T Memory And Array Structure: ROM, RAM, peripheral T1 3 circuitry 19. Memory reliability and yield T1,R1 2 Chalk & Talk

21 Student s Handbook B.Tech (EEE) SRAM and DRAM design T1,R1 3 Chalk & Talk 21. Flash memory, PLA,PAL, FPGA T1,R1 2 Chalk & Talk 22. Design For Testability: Logic Testing T2,R1 2 Chalk & Talk 23. Sequential Logic Testing, Guidelines to be adopted in T2 2 Chalk & Talk Design for Test 24. Scan Designing Techniques, Built-In self Test (BIST) T2,R1 2 Chalk & Talk Techniques Total Lectures: 53 TEXT BOOKS: [T1] Digital integrated circuit design using CMOS by Yusuf & Kang [T2] Digital circuit design by NEAL WASTE. REFERENCE BOOKS: [R1]. Basic VLSI Design by D.A. Pucknell & Eshraghian (PHI) [R2]. Modern VLSI Design Systems on Silicon by Wayne Wolf (Pearson Pub.) [R3]. R. K. Singh «VLSI DESIGN (With VHDL), Kataria & Sons», 2nd Edition, [R4]. S. Gandhi / VLSI Fabrication Principles / 2nd ED. John Willey 1994.

22 3.5 Data Structure using C++ Student s Handbook B.Tech (EEE) 2018 LESSON PLAN SEMESTER/YEAR: 6 th /3 rd DEPARTMENT: CSE COURSE: Data Structure using C++ CODE: TCS-607 Referenc No. Of Delivery Remar S. Topic Name e/ Text Lectur Method ks No. Book/ es Web (R/T/W) UNIT-1 1. Time and Space complexity of algorithms T1,R1 1 Chalk & Talk 2. Asymptotic analysis, Big O and T1,R1 1 Chalk & Talk other notations, 3. Importance of efficient algorithms, T1,T2 1 Chalk & Talk 4. Program performance measurement T1,R1 1 Chalk & Talk 5. Data structures and algorithms T1,R1 1 Chalk & Talk 6. Abstract data type, sequential and linked T1,T2 1 Chalk & Talk representations, 7. Comparison of insertion, T1,R1 2 Chalk & Talk deletion and search operations for sequential lists 8. Comparison of insertion, T1,R1 1 Chalk & Talk deletion and search operations for linked lists 9. List and chain classes T1,R1 1 Chalk & Talk 10. Exception T1,R1 2 Chalk & Talk and Iterator classes for lists 11. Doubly linked lists, circular lists, T1,R1 2 Chalk & Talk 12 Linked lists through simulated T1,R1 1 Chalk & Talk pointers, 13. Lists in STL, skip lists, T1,R1 1 Chalk & Talk 14. Applications of lists in bin sort, radix sort, T1,T2 1 Chalk & Talk 15. Sparese tables T1,R1 1 Chalk & Talk UNIT Abstract data types, sequential implementations T1,R1 2 Chalk & Talk 17. Linked implementations, T1,R1 1 Chalk & Talk 18. Exception T1,R1 2 Chalk & Talk handling in classes

23 Student s Handbook B.Tech (EEE) Representative applications such as parenthesis T2,R1 1 Chalk & Talk matching, towers of Hanoi, 20. Wire routing in a circuit, finding path in a maze T2 1 Chalk & Talk 21. Simulation of queuing systems, equivalence problem T2,R1 1 Chalk & Talk UNIT Search efficiency in lists and skip lists T2 1 Chalk & Talk 23. Hashing as a search structure, hash table T2,R1 1 Chalk & Talk 24. Collision avoidance T2 1 Chalk & Talk 25. Linear open addressing T2,R1 1 Chalk & Talk 26. Uses of hash tables in text compression T2 2 Chalk & Talk 27. LZW algorithm T1 2 Chalk & Talk Unit Binary trees and their properties, terminology 1 Chalk & Talk 29. Sequential and linked implementations T1,T2 1 Chalk & Talk 30. Tree traversal methods and algorithms T2 1 Chalk & Talk 31. Heaps as priority queues, T1 1 Chalk & Talk 32. Heap implementation, insertion T1,R1 2 Chalk & Talk and deletion operations 33. Heapsort T1,R1 1 Chalk & Talk 34. Heaps in Huffman coding T1 1 Chalk & Talk 35. Leftist trees, T2 1 Chalk & Talk 36. Tournament trees T2 1 Chalk & Talk 37. Use of winner trees in mergesort as an external T1,R1 1 Chalk & Talk sorting algorithm 38 Bin packing T1,R1 1 Chalk & Talk UNIT-5 39 Definition, terminology, directed and undirected T1,R1 1 Chalk & Talk graphs 40 Properties, connectivity in T1 1 Chalk & Talk graphs 41 Applications, implementation adjacency matrix T2 1 Chalk & Talk 42 Linked adjacency chains T2 1 Chalk & Talk 43 Graph traversal breadth first T1,R1 1 Chalk & Talk

24 Student s Handbook B.Tech (EEE) Depth first T1,R1 1 Chalk & Talk 45 Spanning trees. T1 1 Chalk & Talk Total Lectures: 53 TEXT BOOKS: [T1]T. H. Cormen, C. E. Leiserson, R. L. Rivest and C. Stein, Introduction to Algorithms, MIT Press, [T2]A. Aho, J. E. Hopcroft and J. D. Ullman, The Design and Analysis of Computer Algorithms, Addison-Wesley, 1974 REFERENCE BOOKS: [R1] M. T. Goodrich and R. Tamassia, Algorithm Design: Foundations, Analysis and Internet Examples, John Wiley & Sons, 2001.

25 3.6 Principle of Management Student s Handbook B.Tech (EEE VI Sem) 2018 DBIT DEHRADUN LESSON PLAN SEMESTER/YEAR: 6 th /3 rd DEPARTMENT: EEE COURSE: Principle of Management CODE: THU-601 Referenc No. Of Delivery Remar S. Topic Name e/ Text Lectur Method ks No. Book/ es Web (R/T/W) INTRODUCTION TO MANAGEMENT: T1,R1 2 Chalk & Talk 1 Theories of management: Traditional behavioral T1,R1 2 Chalk & Talk 2 contingency and systems approach T1,R1 2 Chalk & Talk 3 Organization as a system. T1,R1 2 Chalk & Talk MANAGEMENT INFORMATION: T1,R1 2 Chalk & Talk 4 Interaction with external environment T1,R1 2 Chalk & Talk 5 Managerial decision,making T1,R1 2 Chalk & Talk 6 MIS T1,R1 2 Chalk & Talk PLANNING APPROACH TO ORGANIZATIONAL T1,R1 2 Chalk & Talk ANALYSIS: 7 design of organization structure; T1,R1 2 Chalk & Talk 8 job design and enrichment T1,R1 2 Chalk & Talk 9 job evaluation T1,R1 1 Chalk & Talk 10 merit rating. T1,R1 2 Chalk & Talk MOTIVATION AND PRODUCTIVITY: T1,R1 2 Chalk & Talk 11 Theories of motivation T1,R1 2 Chalk & Talk 12 leadership styles T1,R1 1 Chalk & Talk

26 Student s Handbook B.Tech (EEE VI Sem) managerial grid T1,R1 2 Chalk & Talk 14 Co-ordination T1,R1 1 Chalk & Talk 15 Monitoring T1,R1 1 Chalk & Talk 16 control in organizations T1 1 Chalk & Talk 17 Techniques of control T1,R1 2 Chalk & Talk 18 Japanese management techniques. T1 1 Chalk & Talk Total Lectures: 40 TEXT BOOKS: [T1] Himanshu Aggarwal REFERENCE BOOKS: [R1] L M Parsad

27 Student s Handbook B.Tech (EEE VI Sem) Power System Analysis ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. 1 Course Code: TEE-601 Branch: EEE Semester: V Faculty :Mrs. Nandita Rana Unit/Title: 1/ Symmetrical Components, Fault Calculations Date of Issue: Date of Submission: 1. State Fortescue s Theorem. 2. Significance of positive, negative and zero sequence components. 3. Calculate average 3-phase power in terms of symmetrical components. 4. Explain the concept of Sequence Impedance. 5. Explain Types of Faults. 6. Show the calculation of 3-phase short circuit current. 7. What is a reactor. Explain type of Reactors. 8. Explain the concept of short circuit capacity of a bus.

28 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. 2 Course Code: TEE-601 Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: II/ Load Flow Analysis Date of Issue: Date of Submission: 1. How do you classify buses? 2.What is nodal Admittance matrix? 3.How do we develop load flow equations? 4.What are iterative methods for solving load flow analysis? 5.Explain Newton-Raphson method of solving load flow equations.

29 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. 3 Course Code: TEE-601 Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: III/ Power System Stability Date of Issue: Date of Submission: 1. Explain the concept of Reactive Power Flow. 2. What are difficulties associated with reactive power transmission. 3. Explain the concept short circuit capacity. 4. Explain the concept of voltage stability. 5. What is line drop compensation.

30 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. 4 Course Code: TEE-601 Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: IV/ Wave Equation Date of Issue: Date of Submission: 1. Calculate the wave equation for uniform transmission line. 2. Explain the concept of wave propagation. 3. What is surge impedance. 4. Explain the Bewley s Lattice Diagram. 5. How do we protect transmission lines against travelling lines.

31 Student s Handbook B.Tech (EEE) Control System ASSIGNMENT SHEET Course Name:Control system Assignment No. 1 Course Code:TEE-602 Branch: EEE Semester: VI Faculty :Mr. Saurabh Rajvanshi Unit/Title: 1/ Introduction Date of Issue: Date of Submission: UNIT 1 1 Compare the Open loop System with Closed loop System. 2 Define Transfer Function of the System. 3 What are the advantages of Closed loop System? 4 Write F-V Analogy for the elements of mechanical rotational system? 5 Name the two types of electrical analogous for mechanical system.

32 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name:Control system Assignment No. 2 Course Code:TEE-602 Branch: EEE Semester: VI Faculty :Mr. Saurabh Rajvanshi Unit/Title: 2/ Time Response analysis Date of Issue: Date of Submission: UNIT 2 1 How a Control system is classified depending on the value of damping ratio? 2 Why derivative controller is not used in Control systems? 3 Give steady state errors to a various standard inputs for type 2 systems. 4 What is meant by peak overshoot? 5 The damping ratio and natural frequency of a second order system are o.5 and 8 rad/sec respectively. Calculate resonant peak and resonant frequency. 6 What are the units of k p, k v, k a?

33 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name:Control system Assignment No. 3 Course Code:TEE-602 Branch: EEE Semester: VI Faculty :Mr. Saurabh Rajvanshi Unit/Title: 3/ Stability Analysis Date of Issue: Date of Submission: UNIT 3 1 State any two limitations of Routh-stability criterion. 2 Define Routh Hurwitz stability criterion. 3 What is Root locus? 4 How will you find the root locus on real axis? 5 How the roots of characteristic are related to stability? 6 What do you mean by dominant pole? 7 Sketch the Root Locus of the System whose open loop transfer function is G(S) = K / S (S+1) (S+3). Determine the Value of K for Damping Ratio equal to 0.5.

34 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name:Control system Assignment No. 4 Course Code:TEE-602 Branch: EEE Semester: VI Faculty :Mr. Saurabh Rajvanshi Unit/Title: 4/ Frequency response Analysis I Date of Issue: Date of Submission: UNIT 4 1What are the advantages of Frequency Response Analysis? 2Sketch shape of polar plot for the open loop transfer function G(s)H(s) = 1/ (1+ ). 3What are the specifications used in frequency domain analysis? 4Determine the Phase angle of the given transfer function G(S) = 10 / S (1+0.4S) (1+0.1S) 5Given G(s) = 0.2 /( + 2)( + 8) Draw the Bode plot and find K for the following two cases: (i) Gain margin equal to 6db (ii) Phase margin equal to 45.

35 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name:Control system Assignment No. 5 Course Code:TEE-602 Branch: EEE Semester: VI Faculty :Mr. Saurabh Rajvanshi Unit/Title: 5/ Frequency response Analysis II Date of Issue: Date of Submission: UNIT 5 1 State any two limitations of Routh-stability criterion. 2 State the advantages of Nyquist stability criterion over that of Routh s criterion. 3 State Nyquist stability criterion. 4 Draw the Nyquist plot for the System whose open loop transfer function is G(s) H(s) = K / S (S+2) (S+10). Determine the range of K for which the closed loop System is Stable.

36 4.3 Power Electronics Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power Electronics Assignment No. 1 Course Code: TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: I/Power Semiconductor Devices Date of Issue: Date of Submission: Q1. Discuss the various types of power electronic converters. Q2. Describe switching performance in a GTO with relevant voltage and current waveforms. Q3. List the different power semiconductor devices along with their circuit symbols and maximum ratings. Q4. Describe the basic structure of MCT. Give its equivalent circuit and explain turn-on and turn-off processes. Q5. Describe the different modes of operation of thyristor with the help of its static I-V characteristics.

37 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power Electronics Assignment No. 2 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: II/ Power Semiconductor Devices(Contd.) & Date of Issue: Date of Submission: DC-DC Converters Q1. Describe string efficiency for series/parallel connected SCRs. Show that the string efficiency of two series connected SCRs is usually less than one. Q2. Explain the methods adopted for the protection of SCRs against overcurrents. Q3. Distinguish clearly between voltage commutation and current commutation in thyristor circuits. Q4. Discuss the class B and Class E types of commutation employed for thyristor circuits. Q5. Describe the principle of operation of Step-up chopper. Derive an expression for the average output voltage in terms of input voltage and duty cycle. State assumptions made.

38 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power Electronics Assignment No. 3 Course Code: TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: III/ Phase Controlled Converters Date of Issue: Date of Submission: Q1. An RL load is fed from single-phase supply through a thyristor. Derive an expression for load current in terms of supply voltage, frequency, R, L etc. Indicate the time limits during which this solution is applicable. Q2. Describe how a freewheeling diode improves power factor in a converter system. Q3. Show that the performance of a single phase full-converter as effected by source inductance is given by the relation: Q4. Explain how two 3-phase full converters can be connected back to back to form a circulating current type of dual converter. Discuss its operation with the help of voltage waveforms across (a) each converter (b) load and (c) reactor, take α 1 =0 0. Q5. If the operation of inversion is not required from a line commutated ac to dc converter, a semiconverter possess better performance characteristics than the full converter. Justify this statement.

39 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power Electronics Assignment No. 4 Course Code: TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: IV/ AC Voltage Controllers & Cycloconverters Date of Issue: Date of Submission: Q1. What are the control strategies for the regulation of output voltage in ac voltage controllers? Q2. Discuss the principle of phase control in single-phase full-wave ac voltage controller. Derive expression for the rms value of its output voltage. Q3. What are the advantages and disadvantages of unidirectional as well as bidirectional controllers? Which one of these is preferred and why? Q4. Describe the basic principle of working of single-phase to single-phase step down cycloconverter for both continous and discontinuous conductions for a bridge type cycloconverter. Mark the conduction of various thyristors also. Q5. A single-phase bridge type cycloconverter feeds a load R. For an output frequency equal to one-third of the input frequency, sketch output voltage waveform for a firing angle of about Also derive an expression for the rms output voltage.

40 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power Electronics Assignment No. 5 Course Code: TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: V/ Inverters Date of Issue: Date of Submission: Q1. What are line-commutated inverters? Explain the difference between line-commuated and forcedcommutated inverters. Q2.What is the purpose of connecting diodes in antiparallel with thyristors in inverter circuit? Q3. For a three phase mode bridge inverter feeding a star connected resistive load, sketch line to neutral voltage waveform for a phase only. From this sketch, calculate the rms value of phase voltage. Q4. What is pulse width modulation? List the PWM techniques. How do these differ from each other? Q5. What is the need for controlling the voltage at the output terminals of an inverter?

41 Student s Handbook B.Tech (EEE) VLSI CIRCUIT DESIGN ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 1 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. What is body affect? Discuss different parameters on which threshold voltage depends? 2. Determine Zpu to Zpd ratio for nmos inverter driven through one or more pass transistor? 3. Discuss the gate source and gate drain capacitance of an N-Channel FET. 4. Clearly explain the y effect of a MOS FET. 5. Clearly explain channel lengbodth modulation of a MOS FET. 6. With neat sketches, explain the transfer characteristic of a CMOS inverter. 7. Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region. 8. Explain the operation of BiCMOS inverter? Clearly specify its characteristics. 9. Explain how the BiCMOS inverter performance can be improved. 10. Derive an equation for Ids of an n channel enhancement MOSFET operating in saturation region.

42 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 2 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. Design a stick diagram for two input n-mos NAND and NOR gates. 2. What is a stick diagram and explain about different symbols used for components in stick diagram. 3. Draw the stick diagram and layout for a) NMOS inverter. b). P-Well CMOS inverter. 4. Draw the stick diagram and layout for (a) NMOS inverter. (b) P-Well CMOS inverter. 5. Draw the following transistors using lambda based design rules (a). NMOS enhancement (b). NMOS depletion (c) PMOS enhancement. 6. Discuss the design rules for wires (both NMOS and CMOS) using lambda based design rule 7. What are design rules? Why is metal- metal spacing larger than poly poly spacing. 9

43 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 3 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. what are the differences between a gate array chip and standard-cell chip? What benefits does each implementation style have? 2. Draw and explain the pseudo-nmos PLA schematic for full adder and what are the advantages and disadvantages of it. 3. What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure. 4. Explain any one chip architecture that used the antifuse and give its advantages 5. Draw a self timed dynamic PLA and what are the advantages of it compared to footed dynamic PLA. 6. Explain the tradeoffs between using a transmission gate or a tristate buffer to implement an FPGA routing block. 7. Draw the structure, explain the function and write the applications characteristics of the following programmable CMOS devices: (a) PLA (b) PAL (c) FPGA (d) CPLD

44 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 4 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. Draw the typical standard-cell structure showing low-power cell and explain it 2. Sketch a diagram for two input XOR using PLA and explain its operation with the help of truth table. 3. Explain different fault models in detail. 4. Explain how function of system can be tested. 5. Explain any one of the method of testing bridge faults. 6. What type of faults can be reduced by improving layout design? 7. Why the chip testing is needed? At what levels testing a chip can occur? 8. What is the drawback of serial scan? How to overcome this? 9.. What is the percentage fault coverage? How it is calculated. 10. Explain the following with respect to CMOS testing: (a) ATPG (b) Fault simulation (c) Statistical Fault Analysis (d) Fault Sampling.

45 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 5 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. Explain the gate level and function level of testing. 2. A sequential circuit with in? inputs and m storage devices. To test this circuit how many test vectors are required. 3. What is sequential fault grading? Explain how it is analyzed. 4. Explain how the cost of chip can effect with the testing levels, 5.. Explain how observability is used to test the output of a gate within a larger circuit. 6. How the Iterative Logic Array Testing can be reduced number of tests 7. What type of defects is tested in manufacturing testing methods? 8. What is the Design for Autonomous Test and what is the basic device used in this? 9. What type of tests is used to check the noise margin for CMOS gates? 10. Explain the manufacturing test of a chip with suitable examples. 11. Explain the gate level and function level of testing. 12. A sequential circuit with n inputs and m storage devices. To test this circuit how many test vectors are required? 13. What is sequential fault grading? Explain how it is analyzed

46 4.5 Data Structure using C++ Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: Data Structure using C++ Assignment No.1 Course Code:TCS-607 Branch:CSE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title: UNIT-I Date of Issue: Date of Submission: 1. What do you understand by worst case, average case and best case time complexity of an algorithm? 2. Write an algorithm to concatenate two circularly linked lists pointed by list 1 and list 2 in such a way that circular list pointed by list 2 is appended to the circular list pointed by list 1? 3. How can a polynomial in two variables be represented by a singly linked list? Write an algorithm to add two such polynomials?. 4. Define algorithm and data structure. Give the difference between linear and non-linear data structures with example? 5. Define time complexity. Explain Big oh (O) notation? 6. Write a C++ program to construct and delete elements in a circular queue using linked list? Department of Electrical & Electronics Engineeering

47 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: Data Structure using C++ Assignment No.2 Course Code:TCS-607 Branch:CSE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title: UNIT-II Date of Issue: Date of Submission: 1. What is an ADT? Show the insert and remove operations in/from the Queue ADT during the traversal in a tabular fashion? 2. Write a C++ program to implement stack and its operations, PUSH and POP? 3. Write a complete program in C to implement stack using liked list? 4. What is priority queue? How it is implemented? Take an example to show your implementation? 5. Devise function in C which check for Full and Empty for a circular queue. Also find out the number of elements in circular queue? Department of Electrical & Electronics Engineeering

48 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: Data Structure using C++ Assignment No.3 Course Code:TCS-607 Branch:CSE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title: UNIT-III Date of Issue: Date of Submission: 1. Write an algorithm for searching an algorithm using linear search method?. 2. Discuss various methods used for resolving hash collisions? 3. Explain linear probing and quadratic probing using a suitable example? 4. What is a hash table, explain its applications? 5. Show the working of Huffman algorithm. with an example. Also write the applications of huffman s algorithm? 6. What is the difference between indexing and hashing? Department of Electrical & Electronics Engineeering

49 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: Data Structure using C++ Assignment No.4 Course Code:TCS-607 Branch:CSE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title: UNIT-IV Date of Issue: Date of Submission: 1. What is a heap? Explain how an array of integers can be sorted using heap sort method. Given 20, 55, 46, 34, 13, 90, 87, 32 are elements of an array, show the different stages of sorting? 2. Write an algorithm to construct a binaty tree for the input 14, 15, 4, 9, 7, 18, 3, 5, 16, 4, 20, 17, 9 indicating a message for duplicate members? Draw the tree constructed by the above program? 3. Write a short note on external sorting method? How can we use winner trees in mergesort? 4. What do you mean by heap sort? Explain and write analysis of heap sort? 5. Write a recursive procedure which finds the number of nodes in a tree? Department of Electrical & Electronics Engineeering

50 Student s Handbook B.Tech (EEE) 2018 ASSIGNMENT SHEET Course Name: Data Structure using C++ Assignment No.5 Course Code:TCS-607 Branch:CSE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title: UNIT-V Date of Issue: Date of Submission: 1. Write an algorithm to check whether a graph is connected or not? 2. Write an algorithm which counts the number of connected components in a graph? 3. Define adjacency matrix corresponding to a diagraph? 4. Explain spanning tree and draw a spanning tree for the following graph 5. Explain the various graph representation techniques? Department of Electrical & Electronics Engineeering

51 Student s Handbook B.Tech (EEE VI Sem) Principle of Management ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 1 Course Code:THU-601 Branch: EEE Semester: VI Faculty :Ms. Manvi Chopra Unit/Title: 1/ Introduction of Management Date of Issue: Date of Submission: Q.1 What is Management and why is it important to learn about management? Q.2List the principles of scientific management. Q.3 How does the job of a top manger differ from those of the several levels of middle management? Q.4 What are the 14 principles given by Hennry Fayol related to modern management. Q.5 What are the essential skills of a manager? Q.6 What are the functions of managers? Explain the roles of managers as suggest by Henry Mintzberg. Q.7 What do you understand by bureaucracy? Discuss the characteristics of Max weber bureaucratic model. Q.8 The Neo Classical Theory is human Oriented. Discuss. State the characteristics of Neo Classical Theory.

52 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 2 Course Code:THU-601 Branch: EEE Semester: VI Faculty :Ms. Manvi Chopra Unit/Title: 2/ Management information system Date of Issue: Date of Submission: Q.1 Define and describe business process and their relationship to information systems. Q.2 What are business processes? What role do they play in organizations? How are they enhanced by information systems? Q.3 Explain the major constraints in operating the MIS. Q.4 Explain the role of organizations environment on the MIS and business processes? Q.5 What is Decision Support System? Briefly explain the characteristics of Decision Support System. Q.6 What do you understand by environmental analysis? Discuss the procedure of environmental analysis. Q.7 Explain the planning for implementation step in MIS. Q.8 Define an information system from both a technical and a business perspective.

53 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 3 Course Code:THU-601 Branch: EEE Semester: VI Faculty :Ms. Manvi Chopra Unit/Title: 3/ Planning Approach to organization Analysis Date of Issue: Date of Submission: Q.1 Explain the nature and significance of planning? Q.2 Explain the roles of planning function? Q.3 What is Job Evaluation Process Chart. Q.4 Define Performance Appraisal. What are its salient features? What are its merits & demerits. Q.5 What are the various methods of job Appraisal? Q.6 What is organizational analysis? Explain the models of organizational analysis? Q.7 Discuss the planning approach to organizational analysis? Q.8 What is merit rating and discuss its limitations.

54 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 4 Course Code:THU-601 Branch: EEE Semester: VI Faculty :Ms. Manvi Chopra Unit/Title: 4/ Motivation and Productivity Date of Issue: Date of Submission: 1. Name the steps involved in motivation process. 2. What is Motivation and how is Moslow s hierarchy of needs theory a theory of motivation? 3. What are McGregor s Theory X and Theory Y assumptions? 4. What are three needs Mc Clelland proposed which are present in work situation? 5. What is the relationship between planning and controlling in Organization control process? 6. Leadership is a driving force which gets things done by others. Examine and comment. 7. Good Leadership is an integral part of effectiveness direction. Discuss, bringing out clearly the qualities of an effective leader. 8. Define Leadership. Explain the various Styles and theories of leadership.

55 Student s Handbook B.Tech (EEE VI Sem) Power System Analysis TUTORIAL SHEET Course Name: Power system Analysis Tutorial No. 1 Course Code: TEE 601 Branch: EEE Semester: V Faculty :Mrs. Nandita Rana Unit/Title: 1/ Symmetrical Components, Fault Calculations Date of Issue: Date of Submission: 1. A 100 MVA 33KV 3-phase generator has a sub transient reactance of 15%. The generator is connected to the motors through a transmission line and transformers as shown in fig 1.1. The motor have a rated input of 30MVA, 20MVA and 50MVA at 30KV with 20% sub transient reactance. The 3-phase transformer are rated at 111MVA, 32KV /110KV with leakage reactance 8%. The line has a reactance of 50 ohms. Selecting the generator rating as the base quantities in other parts of the system and evaluate the corresponding p.u. values. 2. The line to- ground voltage on the high voltage side of a step up transformer are 100 KV, 33KV and 38 KV on phases a,b,c respectively. The voltage of phase a leads that of phases b by and lags that of phase c by Determine the analytically the symmetrical components of voltage. 3. The line current in ampere is phases a,b,c respectively are 500+j150, 100-j600 and -300+j600 are referred to the same reference vector. Find the symmetrical components of currents. 4. Determine the fault current and line to line voltage at the fault when a line to line fault occurs at the terminals of the alternator described in the fig Determine the fault current and the line to line voltages at the fault when a double-line to ground fault occur at the terminal of the alternator described in the above diagram.

56 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power system Analysis Tutorial No. 2 Course Code: TEE 601 Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: II/ Load Flow Analysis Date of Issue: Date of Submission: 1.The following is the system data for a load flow solution : The line admittance: Bus code Admittance j j j j j8 The schedule of active and reactive powers: Bus code P Q V Remarks Slack J0 PQ J0 PQ J0 PQ Determine the voltages at the end of first iteration using Gauss-Siedel. Take α= The load flow data for the sample power system are given below. The voltage magnitude at bus 2 is to be maintained at 1.04pu. The maximum and minimum reactive power limits of the generator at bus2 are 0.35 and 0 pu. Respectively. Determine the set of load flow equations at the end of first iteration by using Newton-Raphson method. Bus code Impedance Line charging Impedance j j j

57 Student s Handbook B.Tech (EEE VI Sem) 2018 Schedule of generation and loads: Bus code Assumed Generation Load Voltages MW MVAR MW MVAR j j j

58 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power system Analysis Tutorial No. 3 Course Code: TEE- 601 Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: III/ Power System Stability Date of Issue: Date of Submission: 1. Assume angular difference between the voltages at sending end and receiving end being Also assume sending end voltages 1.0 p.u. and receiving end as 0.9 p.u. Therefore we have significant voltage difference between the sending end receiving, a difference of 10% and hence we should except large reactive power flow over line. 2. A 230/34.5 KV transformer has 10% leakage reactance. Assume initial n=1. Determine the effect of tapping to raise the secondary voltage by 10%. 3. A generator is rated for 0.95 lag p.u. The turbine rating is specified to match the real power at rated p.f. Assuming the rating of turbine fixed, determine the generator rating if 0.8 lag p.f. is specified. Also, calculate the additional reactive power capability at full load.

59 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power system Analysis Tutorial No. IV Course Code: TEE- 601 Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: IV/ Wave Equation Date of Issue: Date of Submission: 1. A surge of 15KV magnitude travels along a cable towards its junction with an overhead line. The inductance and capacitance of the cable and overhead line are respectively 0.3mH, 0.4µF and 1.5mH, 0.012µF per km. Find the voltage rise at the junction due to the surge. 2. A 500KV 2µ sec rectangular surge on a line having a surge impedance of 350 ohms approaches a station at which the concentrated earth capacitance is 300pF. Determine the maximum value of the transmitted wave. 3. An overhead line with surge impedance 400 ohms bifurcates into two lines of surge impedance 400 ohms and 40 ohms respectively. If a surge of 20KV is incident on the overhead line, determine the magnitude of voltages and current which enter the bifurcated lines.

60 5.2 Control System Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name:Control system Tutorial No. 1 Course Code:TEE-602 Branch: EEE Semester: VI Faculty :Mr. Saurabh Rajvanshi Unit/Title: 1/ Introduction Date of Issue: Date of Submission: UNIT 1 1 Draw the Electrical analogous network for the mechanical system shown in the fig. using Force- Voltage Analogy. 2 Determine the Transfer function of the electrical network shown in the fig. 3 Consider the Mechanical system show below and write the Differential equation.

61 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name:Control system Tutorial No. 2 Course Code:TEE-602 Branch: EEE Semester: IV Faculty :Mr. Saurabh Rajvanshi Unit/Title: 2/ Time Response analysis Date of Issue: Date of Submission: UNIT 2 1 With the Suitable block diagrams and Equations, Explain the following type of controllers employed in Control Systems. i. Proportional controller, ii. Proportional plus integral controller, iii. PID Controller,iv. Integral controller. 2 The Unity feedback system is characterized by the open loop transfer function G( ) = / ( +10). Determine the gain K, so that the system will have the damping ratio of 0.5. For this value of K, Determine the settling times, peak overshoot, and time to peak overshoot for a unit step input. 3 Derive Expression for Rise time, fall time, settling time, peak overshoot.

62 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name:Control system Tutorial No. 3 Course Code:TEE-602 Branch: EEE Semester: IV Faculty :Mr. Saurabh Rajvanshi Unit/Title: 3/ Stability Analysis Date of Issue: Date of Submission: UNIT3 1 Check the stability of a stability of a system with characteristics equation S 4 +S 3 +20S 2 +9S+100 = 0 using Routh Hurwitz criterion. 2 Sketch the root locus of the system whose open loop transfer function is G(S)=K/S(S+2) (S+4) Find the value of K so that the damping ratio of the Closed loop system is Construct Routh array and determine the stability of the system whose characteristic equation is left S 6 +2S 5 +8S 4 +12S 3 +20S 2 +16S+16=0. Also determine the number of roots lying on right half of S-plane, half of S-plane and on imaginary axis.

63 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name:Control system Tutorial No. 4 Course Code:TEE-602 Branch: EEE Semester: IV Faculty :Mr. Saurabh Rajvanshi Unit/Title: 4/ Frequency response Analysis I Date of Issue: Date of Submission: UNIT 4 1 Determine the Phase angle of the given transfer function G(S) = 10 / S (1+0.4S) (1+0.1S). 2 Sketch shape of polar plot for the open loop transfer function G(s)H(s) = 1/ (1+ ). 3 A unity feedback control system has G(s) = 1/ 2( +1)(1+2 ) Sketch the polar plot and Find the gain and phase margin.

64 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name:Control system Tutorial No. 5 Course Code:TEE-602 Branch: EEE Semester: IV Faculty :Mr. Saurabh Rajvanshi Unit/Title: 5/ Frequency response Analysis II Date of Issue: Date of Submission: UNIT 5 1 Draw the Nyquist plot for the System whose open loop transfer function is G(s) H(s) = K / S (S+6) (S+11). Determine the range of K for which the closed loop System is Stable. 2 Construct the Nyquist plot for a system, whose open loop transfer function is given by G(S) H(S) = K(1+S) 2 / S 3. Find the range of K for stability.

65 5.3 Power Electronics Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power Electronics. Tutorial Sheet No. 1 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: 1/ Power Semiconductor Devices Date of Discussion: Q1. A bipolar transistor with current gain = 50, has load resistance R c = 10ohm, dc supply voltage V cc = 120V and input voltage to base circuit, V B = 10V. For V CES = 1.2 V and V BES = 1.6V, calculate (a) The value of R B for operation in the saturated state. (b) The value of R B for an or drive factor (c) Forced current gain and (d) Power loss in the transistor for both parts (a) and (b). Q2. For the circuit shown in figure, the capacitor is initially charged to a voltage V 0 with upper plate positive. Switch S is closed at t=0. Derive expressions for the current in the circuit and voltage across capacitor C. What is the peak value of diode current? Find also the energy dissipated in the circuit.

66 Student s Handbook B.Tech (EEE VI Sem) 2018 Q3. In the diode and LC network shown in figure, the capacitor is initially charged to voltage V with upper plate positive. Switch is closed at t = 0. Derive expressions for current through and voltage across C. Q4. Find the conduction time of diode, peak value of current through the diode and final steady state voltage across C in case Vs= 400V, Vo=100V, L=100μH and C= 30μF. Determine also the voltage across the diode after it stops conduction. Q5. For an SCR the gate-cathode characteristic has a straight line slope of 130. For trigger source voltage of 15 V and allowable gate power dissipation of 0.5W, compute gate source resistance.

67 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power Electronics Tutorial Sheet No. 2 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: II/Power semiconductor Devices & DC-DC converters Date of Discussion: Q1. For type-a chopper, dc source voltage=230v, load resistance=10ohm. Take a voltage drop of 2V across chopper when it is on. For a duty cycle of 0.4, calculate average and rms values of output voltage and chopper efficiency. Q2. A step up chopper has input voltage of 220V and output voltage of 660V. If the conducting time of thyristor-chopper is 100μs, compute the pulse width of output voltage. In case output voltage pulse width is halved for constant frequency operation, find average value of new output voltage. Q3. An RLE load is operating in a chopper circuit from a 500Volt dc source. For the load, L=0.06H, R=0 and constant E. For a duty cycle of 0.2, find the chopper frequency to limit the amplitude load current excursion to 10A. Q4. It is required to operate 250A SCR in parallel with 350A SCR with their respective on-state voltage drops of 1.6V and 1.2V. Calculate the value of resistance to be inserted in series with each SCR so that they share the total load of 600A in proportion to their current ratings.

68 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power Electronics Tutorial Sheet No. 3 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: III/ Phase controlled Converters Date of Discussion: Q1. A dc battery is charged through a resistor with the assumption that SCR is fired continuously. (a) For an ac source voltage of 230V, 50Hz, find the value of average charging current for R=8ohm and E=150V. (b) Find the power supplied to battery and that dissipated in the resistor. (c) Calculate the supply pf. Q2. A 230V, 50Hz, one-pulse SCR controlled converter is triggered at a firing angle of 40 0 and the load current extinguishes at an angle of Find the circuit turn off time, average output voltage and average load current for (a) R= 5ohm and L= 2mH (b) R=5 ohm, L=2mH and E=110V Q3. A single phase transformer, with secondary voltage of 230V, 50Hz, delivers power to load R = 10ohm through a half wave controlled rectifier circuit. For a firing angle delay of 60 0, determine (a) the rectification efficiency (b) form factor (c) voltage ripple factor (d) transformer utilization factor (e) PIV of thyristor. Q4. A single phase full converter, connected to 230V, 50Hz source, is feeding a load R = 10ohm in series with a large inductance that makes the load current ripple free. For a firing angle of 45 0, calculate the input and output performance parameter of this converter.

69 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power Electronics Tutorial Sheet No. 4 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: IV/ AC Volatge Controllers & Cycloconverters Date of Discussion: Q1. A single phase half wave ac voltage controller feeds a load of R= 20ohm with an input voltage of 230V, 50Hz. Firing angle of thyristor is Determine (a) rms value of output voltage (b) power delivered to load input pf and (c) average input current. Q2. A single phase full wave ac voltage controller feeds a load of R = 20ohm with an input voltage of 230V, 50Hz. Firing angle for both the thyristors is Calculate (a) rms value of output voltage (b) load power and input pf (c) average and rms current of thyristors. Q3. A single phase voltage controller has input volate of 230V, 50Hz and a load of R = 15 ohm. For 6 Cycles on and 4 cycles off, determine (a) rms output voltage, (b) input pf and (c) average and rms thyristors currents. Q4. A single phase bridge type cycloconverter has input voltage of 230V, 50Hz and load of R= 10ohm. Output frequency is one-third of the input frequency. For a firing angle delay of 30 0, calculate (a) rms value of output voltage (b) rms current of each converter (c) rms current of each thyristor and (d) input power factor.

70 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name: Power Electronics Tutorial Sheet No. 5 Course Code: TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: V/ Inverters Date of Discussion: Q1. A single phase bridge inverter delivers power to a series RLC load with R= 2ohm and ωl = 10ohm. The periodic time T= 0.1 msec. What value of C should the load have in order to obtain load commutation for the SCRs. The thyristor turn off time is 10μsec. Take circuit turn off time as 1.5 t q. Assume that load current contains only fundamental component. Q2. A single phase full bridge inverter is fed from a dc source such that the fundamental component of output voltage is 230V. Find the rms value of thyristor and diode currents for the following loads: (a) R = 2ohm (b) R = 2ohm, X L = 8ohm, X c =6ohm Q3. A three-phase bridge inverter delivers power to a resistive load from a 450V dc source. For a starconnected load of 10Ω per phase, determine for both (a) mode and (b) mode, (i) (ii) (iii) Rms value of load current Rms value of thyristor current Load power. Q4. A single-phase bridge inverter is fed from 230Vdc. In the output voltage wave, only fundamental component of voltage is considered. Determine the rms current ratings of an SCR and a diode of the bridge for the following types of loads: (i) R= 20ohm (ii) ωl = 2ohm

71 Student s Handbook B.Tech (EEE VI Sem) 2018

72 Student s Handbook B.Tech (EEE) VLSI CIRCUIT DESIGN TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN TUTORIAL No. 1 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. A CMOS inverter is built in a process where k n = 100μA/V2, V tn = +0.7V, k'p = 42 μa/v2, Vtp=-0.8V, and a power supply of V DD = 3.33V is used.find midpoint voltage VM if (W/L)n =10 and (W/L)p= Discuss the CMOS invertors transfer characteristics. 3. Find gm for an n-channel transistor with V gs =1.2V: V tn =0.8V; (W/L) = 10μn C ox = 92μA/V2. 4. Define the term threshold voltage of MOSFET and explain its significance. 5. Derive an equation for Transconductance of an n channel enhancement MOS-FET operating in active region. 6. A PMOS transistor is operated in triode region with the following parameters. VGS= - 4.5V, Vtp= -1V; V DS = -2.2 V, (W/L) = 95, μnc ox = 95μA/V2. Find its drain current and drain source resistance.

73 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN TUTORIAL No. 2 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. Calculate the gate capacitance of an nfet with following parameter. W = 8μm, L= 0.5μm, Cox = F/cm2. 2. Design a stick diagram and layout diagram for the CMOS logic shown below Y = (A + B) (C + D). 3. What is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. 4. What are the effects of scaling on VT? 5. What are design rules? Why is metal- metal spacing larger than poly -poly spacing. 6. What is a stick diagram? Draw the stick diagram and layout for a CMOS inverter.

74 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN TUTORIAL No. 3 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. Write the equations for a full adder in SOP form. Sketch a 3-input, 2- output PLA implementing this logic. 2. Draw the typical architecture of PAL and explain the operation of it. 3. What is CPLD? Draw its basic structure and give its applications. 4. Draw and explain the Antifuse Structure for programming the PAL device. 5. Explain how the I/O pad is programmed in FPGA. 6. What are different classes of Programmable CMOS devices? Explain them briefly. 7. What is the basis for standard-cell? What are basic classes of circuits for Library cells? 8. Draw the typical standard-cell structure showing regular-power cell and explain it.

75 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN TUTORIAL No. 4 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: I Date of Issue: Date of Submission: 1. Explain the gate level and function level of testing. 2. A sequential circuit with n inputs and m storage devices. To test this circuit how many test vectors are required? 3. What is sequential fault grading? Explain how it is analyzed. 4. Explain how the cost of chip can effect with the testing levels, 5. Explain how observability is used to test the output of a gate within a larger circuit. 6. How the Iterative Logic Array Testing can be reduced number of tests. 7. Explain how the cost of chip can effect with the testing levels, a. Fault Analysis b. Fault Sampling.

76 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN TUTORIAL No. 5 Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Unit/Title: V Date of Issue: Date of Submission: 1. Explain how an Ad-hoc test technique used to test long counters. November 2008 set4 2. Explain the gate level and function level of testing. 3. A sequential circuit with n inputs and m storage devices. To test this circuit how many test vectors are required? 4. What is sequential fault grading? Explain how it is analyzed. 5. Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout. 6. Draw a schematic for a CMOS edge-sensitive scan-register and also draw some circuit level diagrams of its implementation. 7. Explain how function of system can be tested. 8. Explain any one of the method of testing bridge faults. 9. What type of faults can be reduced by improving layout design? 10. Explain the functionality test of a chip with suitable examples. 11. What are the categories of Design for testability? Explain them briefly

77 5.5 Data Structure using C++ Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 1 Course Code:TCS-607 Branch:EEE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title:UNIT-1 Date of Discussion: Q1. What is a data structure? Explain the characteristics of Data Structure. Q2. What do you mean by Asymptotic Notation? Explain its type. Q.3 Explain about the types of linked lists. Write the programs for Linked List (Insertion and Deletion) operations Q4. If you are using C language to implement the heterogeneous linked list, what pointer type will you use? Q5. A two dimensional array TABLE [6] [8] is stored in row major order with base address 351. What is the address of TABLE [3] [4]?

78 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 2 Course Code:TCS-607 Branch: EEE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title:UNIT-2 Date of Discussion: Q1. Evaluate the following prefix expression " " (Similar types can be asked). Q2. How is it possible to insert different type of elements in stack? Q.3. Which data structure is needed to convert infix notations to post fix notations? Q4. Write an algorithm to evaluate a postfix expression. Execute your algorithm using the following postfix expression as your input : a b + c d +*f. Q5. What are circular queues? Write down routines for inserting and deleting elements from a circular queue implemented using arrays.

79 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 3 Course Code:TCS-607 Branch: EEE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title:UNIT-3 Date of Discussion: Q.1 Given a set of input representing the nodes of a binary tree, write a non recursive algorithm that must be able to output the three traversal orders. Write an algorithm for checking validity of the input, i.e., the program must know if the input is disjoint, duplicated and has a loop. Q.2 What is a Binary Search Tree (BST)? Make a BST for the following sequence of numbers 45, 36, 76, 23, 89, 115, 98, 39, 41, 56, 69, 48 Traverse the tree in Preorder, Inorder and postorder. Q.3 Two Binary Trees are similar if they are both empty or if they are both nonempty and left and right sub trees are similar. Write an algorithm to determine if two Binary Trees are similar. Q.4 The degree of a node is the number of children it has. Show that in any binary tree, the number of leaves are one more than the number of nodes of degree 2. Q.5 Taking a suitable example explains how a general tree can be represented as a Binary Tree.

80 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 4 Course Code:TCS-607 Branch: EEE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title:UNIT-4 Date of Discussion: Q.1 Draw the complete undirected graphs on one, two, three, four and five vertices. Prove that the number of edges in an n vertex complete graph is n(n-1)/2. Q.2 Draw the complete undirected graphs on one, two, three, four and five vertices. Prove that the number of edges in an n vertex complete graph is n(n-1)/2. Q.3 What are the different ways of representing a graph? Represent the following graph using those ways. Q.4 What are the different ways of representing a graph? Represent the following graph using those ways. Q.5 Write an algorithm which does depth first search through an un-weighted connected graph. In an un-weighted graph, would breadth first search or depth first search or neither find a shortest path tree from some node? Why?

81 Student s Handbook B.Tech (EEE) 2018 TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 5 Course Code:TCS-607 Branch: EEE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title:UNIT-5 Date of Discussion: Q.1Bubble sort algorithm is inefficient because it continues execution even after an array is sorted by performing unnecessary comparisons. Therefore, the number of comparisons in the best and worst cases are the same. Modify the algorithm in such a fashion that it will not make the next pass when the array is already sorted. Q.2 What are B-trees? Construct a B-Tree of order 3 for the following set of Input data: 69, 19, 43, 16, 25, 40, 132, 100, 145, 7, 15, 18. Q.3 Draw the 11 item hash table resulting from hashing the keys: 12, 44, 13, 88, 23, 94, 11, 39, 20, 16 and 5 using the hash function h(i) = (2i+5) mod 11. Q.4 What is the average number of comparisons in a sequential search? Q.5 1 Sort the following list using Heap Sort technique, displaying each step. 20, 12, 25 6, 10, 15, 13

82 Student s Handbook B.Tech (EEE VI Sem) Principle of Management TUTORIAL SHEET Course Name: Principles of Management Tutorial Sheet No. 1 Course Code:THU-608 Branch: EEE Semester: VI Faculty :Ms. Manvi Chopra Unit/Title: Date of Discussion: CASE -1 Managing by objective is nothing new here, said commissioner Gaurav of the metropolis Police Department. We have always had important objectives toward which every one in my department strives. Our job is to maintain law and order, firmly but fairly; to protect human lives and property; and to be the conscience and spirit of the general welfare of the millions of people who call our city home. Everyone in this department knows these objectives. Every man and woman knows that he or she must work toward them and that, if they do not, they will be replaced. I recognize that in a manufacturing concern you can measure objectives by profits, sales, costs and product output. We can t, of course, do that, for we are service operation. But this does not mean that we are not managing by objectives. Ask anyone in my department? Questions 1. (a) Is commissioner Gaurav engaging in managing by objectives? What, if anything, is missing? (b) What would you suggest the commissioner do?

83 Student s Handbook B.Tech (EEE VI Sem) 2018 TUTORIAL SHEET Course Name:Principles of Management Tutorial Sheet No. 2 Course Code:THU-608 Branch: EEE Semester: VI Faculty :Ms. Manvi Chopra Unit/Title: Date of Discussion: CASE - 2 The personnel Manager of Bushan steels, an engineering unit based at Kolkata has been banging the executive conference table of the company for some months asserting that the true function of Management is to take care of the needs of the staff and let the staff take care of the goals of the organization. The marketing Manager has, on the other hand, been expressing the view that the real function of management is to take care of the market and staff must fall in line with the objectives, plans and priorities of the company. Question Which of these views is correct and why?

84 Student s Handbook B.Tech (EEE VI Sem) Power System Analysis ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. 1 Course Code: Branch: EEE Semester: V Faculty :Mrs. Nandita Rana Unit/Title: 1/ Symmetrical Components, Fault Calculations Date of Issue: Date of Submission: 1. A 100 MVA 33KV 3-phase generator has a sub transient reactance of 15%. The generator is connected to the motors through a transmission line and transformers as shown in fig 1.1. The motor have a rated input of 30MVA, 20MVA and 50MVA at 30KV with 20% sub transient reactance. The 3-phase transformer are rated at 111MVA, 32KV /110KV with leakage reactance 8%. The line has a reactance of 50 ohms. Selecting the generator rating as the base quantities in other parts of the system and evaluate the corresponding p.u. values. 2. The line to- ground voltage on the high voltage side of a step up transformer are 100 KV, 33KV and 38 KV on phases a,b,c respectively. The voltage of phase a leads that of phases b by and lags that of phase c by Determine the analytically the symmetrical components of voltage. 3. The line current in ampere is phases a,b,c respectively are 500+j150, 100-j600 and -300+j600 are referred to the same reference vector. Find the symmetrical components of currents. 4. Determine the fault current and line to line voltage at the fault when a line to line fault occurs at the terminals of the alternator described in the fig Determine the fault current and the line to line voltages at the fault when a double-line to ground fault occur at the terminal of the alternator described in the above diagram. 6. State Fortescue s Theorem. 7. Significance of positive, negative and zero sequence components. 8. Calculate average 3-phase power in terms of symmetrical components. 9. Explain the concept of Sequence Impedance. 10. Explain Types of Faults. 11. Show the calculation of 3-phase short circuit current. 12. What is a reactor. Explain type of Reactors. 13. Explain the concept of short circuit capacity of a bus.

85 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. 2 Course Code: Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: II/ Load Flow Analysis Date of Issue: Date of Submission: 1.The following is the system data for a load flow solution : The line admittance: Bus code Admittance j j j j j8 The schedule of active and reactive powers: Bus code P Q V Remarks Slack J0 PQ J0 PQ J0 PQ Determine the voltages at the end of first iteration using Gauss-Siedel. Take α= The load flow data for the sample power system are given below. The voltage magnitude at bus 2 is to be maintained at 1.04pu. The maximum and minimum reactive power limits of the generator at bus2 are 0.35 and 0 pu. Respectively. Determine the set of load flow equations at the end of first iteration by using Newton-Raphson method. Bus code Impedance Line charging Impedance j j j

86 Student s Handbook B.Tech (EEE VI Sem) 2018 Schedule of generation and loads: Bus code Assumed Generation Load Voltages MW MVAR MW MVAR j j j How do you classify buses? 4.What is nodal Admittance matrix? 5.How do we develop load flow equations? 6.What are iterative methods for solving load flow analysis? 7.Explain Newton-Raphson method of solving load flow equations.

87 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. 3 Course Code: Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: III/ Power System Stability Date of Issue: Date of Submission: 1. Assume angular difference between the voltages at sending end and receiving end being Also assume sending end voltages 1.0 p.u. and receiving end as 0.9 p.u. Therefore we have significant voltage difference between the sending end receiving, a difference of 10% and hence we should except large reactive power flow over line. 2. A 230/34.5 KV transformer has 10% leakage reactance. Assume initial n=1. Determine the effect of tapping to raise the secondary voltage by 10%. 3. A generator is rated for 0.95 lag p.u. The turbine rating is specified to match the real power at rated p.f. Assuming the rating of turbine fixed, determine the generator rating if 0.8 lag p.f. is specified. Also, calculate the additional reactive power capability at full load. 4. Explain the concept of Reactive Power Flow. 5. What are difficulties associated with reactive power transmission. 6. Explain the concept short circuit capacity. 7. Explain the concept of voltage stability. 8. What is line drop compensation.

88 Student s Handbook B.Tech (EEE VI Sem) 2018 ASSIGNMENT SHEET Course Name: Power system Analysis Assignment No. IV Course Code: Branch: EEE Semester: VI Faculty : Mrs. Nandita Rana Unit/Title: IV/ Wave Equation Date of Issue: Date of Submission: 1. A surge of 15KV magnitude travels along a cable towards its junction with an overhead line. The inductance and capacitance of the cable and overhead line are respectively 0.3mH, 0.4µF and 1.5mH, 0.012µF per km. Find the voltage rise at the junction due to the surge. 2. A 500KV 2µ sec rectangular surge on a line having a surge impedance of 350 ohms approaches a station at which the concentrated earth capacitance is 300pF. Determine the maximum value of the transmitted wave. 3. An overhead line with surge impedance 400 ohms bifurcates into two lines of surge impedance 400 ohms and 40 ohms respectively. If a surge of 20KV is incident on the overhead line, determine the magnitude of voltages and current which enter the bifurcated lines. 4. Calculate the wave equation for uniform transmission line. 5. Explain the concept of wave propagation. 6. What is surge impedance. 7. Explain the Bewley s Lattice Diagram. 8. How do we protect transmission lines against travelling lines.

89 Student s Handbook B.Tech (EEE) Control System Question Bank Course Name: Control System Question Bank Course Code:TEE-602 Branch: EEE Semester: VI Faculty : Mr. Saurabh Rajvanshi Question bank Unit-I The control system 1. The sensitivity of a closed-loop system with respect to variation of a closed loop system with respect to variation in G is reduced by a factor (1+GH) as compared to that of an openloop system. Prove the statement Write the differential equations governing the Mechanical system shown in fig 3. Determine the transfer function Y2(S)/F(S) of the system shown in fig.

90 Student s Handbook B.Tech (EEE) Determine the overall transfer function C(S)/R(S) for the system shown in fig. 5. Obtain the closed loop transfer function C(S)/R(S) of the system whose block diagram is 6. Find the overall gain C(s) / R(s) for the signal flow graph shown below.

91 Student s Handbook B.Tech (EEE) Find the overall gain of the system whose signal flow graph is shown in fig. 8. Draw a signal flow graph and evaluate the closed loop transfer function of a system whose block is shown in fig. 9. Write the differential equations governing the mechanical systems shown below. Draw the forcevoltage and force-current electrical analogous circuits and verify by writing mesh and node equations.

92 Student s Handbook B.Tech (EEE) Derive the transfer function for Armature controlled DC motor. 11 What is mathematical model of a system and What are the two major type of control systems? Unit-II Time Response Analysis 12 What do you mean by an order and type of a system. Explain : (i) (ii) (iii) Type-0 system Type-1 system Type-2 system 13 Obtain the unit-step response of a unity feedback control system whose open-loop transfer function is G(s) = 4/s(s+5) 14 Discuss the time response of a general second order system. what are the various time response specification for a general second order system? give their expressions for a unit step input 15 Derive the expressions and draw the response of first order system for unit step input. 16 Draw the response of second order system for critically damped case and when input is unit step. 17 Derive the expressions for Rise time, Peak time, Peak overshoot, delay time. 18 Define damping ratio The closed loop transfer function of second order system is C(S)/R(S) =10/ S2 +6S +10.what is type of damping

93 Student s Handbook B.Tech (EEE) Sketch the inverse polar plot of G(s) = (1+sT)/sT Unit-III Control System Components 20 Define the minimum, non minimum and all-pass system. 21 When a pole at origin is added, the head and tail of the polar plot shift by 90 0 in clockwise direction. Prove it by taking an example. 22 The open loop transfer function of a unity feedback control system is given by: G(s) = k/s(s+1)(s=2) Determine the static error constants. Find the minimum value of k for which the steady state error is less than 0.1 for a unit ramp input. 23 Discuss the stability of a linear control system. How relative stability of a control system is determined? Discuss with suitable examples. 24 The characteristics equation of a system is given by : 5s 6 + 8s s 4 +20s s s = 0 Determine the stability of the system using Routh-Hurwitz criterion. 25 What are the following? Explain with examples : (a) PID controller (b) Stepper motor (c) Servo motor 26 Derive the steady state error for a same system using derivative and integral control action separately, compare their performance. 27 The closed loop transfer of a control system is: G(s) = 16/ (s s+ 16) Determine the derivative feedback constant K t and compare the rise time, peak time, maximum overshoot and steady state error for unit ramp input with and without derivative feedback control. If it is desired to have the damping ratio to be 0.8

94 Student s Handbook B.Tech (EEE) 2018 Unit-IV Frequency response Analysis 1. Consider a unity feedback system with open loop transfer function : G(s) = 20(s+1)/s(s+5)(s 2 +2s+10) Draw the Bode plot and determine the gain margin and phase margin. 2. Sketch the Root locus plot of a unity feedback system with open loop transfer function : G(s) = k/s(s+2)(s+4) Find the range of values of k for which the system has damped oscillatory response. What is the greatest value of k which can be used before continuous oscillations occur? also determine the frequency of continues oscillations. 3. Discuss the Nyquist stability criterion with suitable example. 4. Discuss the effect of adding (i)a pole and (ii) a zero, to the system transfer function. 5. Explain briefly constant Magnitude loci (M-circles) and constant phase angle loci (N-circles) 6. Sketch the Root-locus for the system : G(s)H(s) = k/(s+1)(s+3)(s 3 +4s+8) 7. Consider a unity feed back control system for the following open loop transfer function. G(s) = k/s(s 2 +4s+8)Plot the Root locus for the system 8. Sketch the Bode plot for the transfer function G(s) = 1000/(1+0.1s)( s) Determine the phase margin, gain margin, stability of the system. 9. Sketch the Bode plot for the transfer function G(s) = 1000/s(1+0.1s)( s) Determine the phase margin, gain margin, stability of the system. 10. Draw the Bode plot for the transfer function G(s) = 50/(1+0.25s)(1+0.1s) Determine the Gain crossover frequency, Phase cross over frequency, Phase margin, Gain margin, stability of the system 11. With suitable diagram define Phase crossover frequency, Phase cross over frequency, Phase margin, Gain margin.

95 Student s Handbook B.Tech (EEE) 2018 Unit-V Introduction to Design 1. Discuss the advantage of space state representation of system. Point out the significance of state transition matrix is solving question. 2) A system is characterised by the transfer function T(s)= 2/(s 3 + 6s 2 +11s+6) obtain state space model and determine whether or not the system is controllable and observable. 3) explain what do you understand by cascade-lead compensation of linear control system? 4) give the transfer function of a typical lead compensator and explain it s basic characteristics in reference to bode plot. 5) Design a lead compensator for a plant G(s) = 1/s(s+1) assume that the specification for the transient response and such that ζ = & ώ n =2 rad/sec for the desired closed loop poles will give a satisfactory response. 6) What are the various type of compensation schemes used in control systems? explain the concept of cascade-lead compensation of control system with help of an example. 7) design a lag compensator (root locus) for k v 5, ζ =0.707 & ώ n = 0.81 for G(s)H(s)=2.74/s(s+1)(s+4) 8) Find the stability of the system whose system matrix is given by ) What is the properties of state transition matrix and find the state transition matrix for dx 1 /dt = x 2 d x 2 /dt = -5 x 1-6 x 2 10) the transfer function of the system is G(s) = 2/(s+1)(s+2) obtain a state variable representation

96 6.3 Power Electronics Student s Handbook B.Tech (EEE VI Sem) 2018 QUESTION BANK Course Name: Power Electronics Question Bank No. 1 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: 1/ Power Semiconductor Devices Date of Discussion: Q1. Discuss the various types of power electronic converters with their circuit symbols and maximum ratings. Q2. Discuss the following terms for diodes: Softness factor, PIV, reverse recovery time, reverse recovery current. Q3. Give a comparison between an IGBT and a PMOSFET. Q4. Give I-V characteristics of an MCT. Compare it with the characteristics of other power semiconductor devices. Q5. Describe reverse recovery characteristics of diodes. Show that the reverse recovery time and peak inverse current are dependent upon storage charge and rate of change of current. Q6. Define input power factor, displacement factor DF and current distortion factor CDF for a rectifier system and show that input power factor = CDF *DF. Q7. Describe the two-transistor model of a thyristor. Q8. Write comparison between GTO and thyristor. Q9. Describe the methods employed for improving di/dt rating in a thyristor. Q10. Define latching and holding currents as applicable to an SCR. Show these currents on its static I-V characteristics.

97 Student s Handbook B.Tech (EEE VI Sem) 2018 QUESTION BANK Course Name: Power Electronics Question Bank No. 2 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: II/ Power Semiconductor Devices(contd.) & DC-DC converters Date of Discussion: Q1. Enumerate the abnormal conditions against which thyristors must be protected. Q2. Draw a circuit diagram illustrating the protection of anode and gate circuits of an SCR. Describe briefly the function of various components used. Q3. Explain the merits and demerits of self-commutation of SCR and its other methods of commutation. Q4. Describe Class C type of commutation used for thyristors with appropriate current and voltage waveforms. Q5. Enumerate the various commutation techniques used for thyristors. Q6. What is current limit control? How does it differ from time ratio control? Which of these control strategies is preferred over the other and why? Q7. For type-a chopper connected to RLE load, write the basic voltage equations and derive expressions for the maximum and minimum values Of load currents in terms of source voltage, R, E,V s etc. Q8. What is a dc chopper? Describe the working of type-b chopper. Does it operate as a step down or step-up chopper? Explain. Q9. A step-up chopper has a pulse width of 100μs is operating from 230V dc supply. Compute the average value of load voltage for a chopping frequency of 2000 Hz. Q10. A type-a chopper has input dc voltage of 200V and a load of R=10Ω in series with L=80mH. If the load current varies linearly between 12A and 16A, find the time ratio T on /T off for this chopper.

98 Student s Handbook B.Tech (EEE VI Sem) 2018 QUESTION BANK Course Name: Power Electronics Question Bank No. 3 Course Code: TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: III/ Phase Controlled Converters Date of Discussion: Q1. Power flow from 1-phase source to load R can be controlled through the use of a thyristor. Discuss why this method of power flow control is called phase-controlled converters. Q2. A single-phase half-wave SCR circuit feeds power to a resistive load. Draw waveforms for source voltage, load voltage, load current and voltage across the SCR for a given firing angle α. Hence obtain expressions for average and rms load voltage in terms of source voltage and firing angle. Q3. Describe the working of a single-phase one-pulse SCR controlled converter with RLE load through the waveforms of supply voltage, load voltage, load current and voltage across the SCR. Hence derive expression for the load current. Q4. Describe the working of a single-phase full-converter in the rectifier mode with RLE load. Q5. Describe how a freewheeling diode improves power factor in a converter system. Q6. Describe the effect of source inductance on the performance of a 3-phase full-converter with the help of phase voltage waveforms. Q7. Explain how two 3-phase full-converters can be connected back to back to form a circulating type of dual converter. Q8. A single phase full converter, connected to 230V, 50 Hz source, is feeding a load R=10Ω in series with a large inductance that makes the load current ripple free. For a firing angle of 45 0, calculate the input and output performance parameters of this converter. Q9. A three phase full-converter charges a battery from a three phase supply of 230V, 50Hz. The battery emf is 200V and its internal resistance is 0.5Ω. On account of inductance connected in series with the battery, charging current is constant at 20A. Compute the firing angle delay and the supply power factor. Q10. A single phase 230V, 1kW heater is connected across 1 phase, 230V, 50Hz supply through an SCR. For firing angle delays of 45 0 and 90 0, calculate the power absorbed in the heater element.

99 Student s Handbook B.Tech (EEE VI Sem) 2018 QUESTION BANK Course Name: Power Electronics Question Bank No. 4 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: IV/ AC Voltage Controllers/ Cycloconverters Date of Discussion: Q1. What is an ac voltage controller? List some of its industrial applications. Enumerate its merits and demerits. Q2. Describe the principle of phase control in single-phase half-wave ac voltage controller. Q3. What are the control strategies for the regulation of output voltage in ac voltage controllers? Q4. Discuss the principle of phase control in single-phase full-wave ac voltage controller. Derive expression for the rms value of output voltage. Q5. Compare the merits of controlling the heater power by a triac using integral cycle over the phaseangle control. Q6. Define the term power factor. Derive its expression for a single-phase voltage controller feeding a resistive load circuit. Q7. Discuss why 3-phase to 1-phase cycloconverter requires positive and negative group phase controlled converters. Q8. What are the advantages of 3-phase bridge circuit cycloconverter over 18-thyristor device. Q9. Describe the operating principle of single-phase to single-phase step up cycloconverter with the help of mid-point and bridge-type configurations. Q10. A single-phase full-wave ac voltage controller feeds a load of R=20Ω with an input voltage of 230V, 50Hz. Firing angle for both the thyristors is 45 0 Determine (a) rms value of output voltage (b) load power and input pf (c) average and rms current of thyristors.

100 Student s Handbook B.Tech (EEE VI Sem) 2018 QUESTION BANK Course Name: Power Electronics Question Bank No. 5 Course Code:TEE-603 Branch: EEE Semester: VI Faculty : Ms. Sonam Rawat Unit/Title: V/ Inverters Date of Discussion: Q1. What are the two main types of inverters? Distinguish between them. Q2. What is the purpose of connecting diodes in antiparallel with thyristors in inverter circuits? Explain how these diodes come into play. Q3. Write Fourier series expression for output voltages and currents obtained from single-phase halfbridge and full-bridge inverters. Q4. For a 3-phase mode bridge inverter feeding a delta-connected resistive load, sketch any line voltage waveform. From this waveform, calculate rms value of line voltage. Q5. Describe briefly and compare the various methods employed for the control of output voltage of inverters. Q6. What is pulse width modulation? List the PWM techniques. Q7. State some requirements of a good inverter. Q8. Write down the steady-state analysis of single-phase inverter. Q9. Describe the terms in relation to inverters: Harmonic factor, Total Harmonic Distortion, Distortion Factor Q10. Describe the working of three-phase bridge inverter in mode. Q11. Discuss the merits and demerits of 120-degree mode inverter over 180-degree mode inverter. Q12. A three-phase bridge inverter delivers power to a resistive load from a 450V dc source. For a starconnected load of 10Ω per phase, determine for both (a) mode and (b) mode, (i) (ii) (iii) Rms value of load current Rms value of thyristor current Load power.

101 Student s Handbook B.Tech (EEE) VLSI CIRCUIT DESIGN QUESTION BANK Course Name: VLSI CIRCUIT DESIGN QUESTION BANK Course Code:TEC-602 Branch: ECE Semester: 6 TH Faculty : K.C. Tyagi Question bank of VLSI Design: Unit-1 What is body affect? Discuss different parameters on which threshold voltage depends? Determine Zpu to Zpd ratio for nmos inverter driven through one or more pass transistor? Discuss the gate source and gate drain capacitance of an N-Channel FET. Calculate the gate capacitance of an nfet with following parameter. W = 8μm, L= 0.5μm, Cox = F/cm2. Clearly explain the body effect of a MOS FET. Clearly explain channel length modulation of a MOS FET. With neat sketches, explain the transfer characteristic of a CMOS inverter. Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region. Explain Accumulation, Depletion layers in MOs with Energy band diagram. Q.2. Derive an expression for Depletion depth and Max Depletion depth in MOS structure. Q.3. what do you mean by Scaling and small geometry effects in VLSI design for MOS? Find all the basic parameters of a MOS after constant Electric field scaling and constant voltage scaling. Q.4. Derive an expression for drain current in linear region, saturation region through gradual channel approximation and Channel length modulation. Q.5. what are physical limitations and parasitic effects in miniaturizing the circuits? Explain each in detail. Q.6. Describe the structure and operation of MOSFET with its characteristics. Q.7. Explain how computer aided design technology helps us to design VLSI circuits. Q.8. Write a Short note on spice for circuit simulation. Explain the VLSI Design flow diagram? Q.9. Explain and Draw the V-I characteristics of N - Depletion type-mosfet (D-MOS). Explain and Draw the V-I characteristics of P - Enhancement type-mosfet (E-MOS). Q.10 Explain and Draw the V-I characteristics of P - Depletion type-mosfet (D-MOS). Explain and Draw the V-I characteristics of N - Enhancement type-mosfet (E-MOS).

102 Student s Handbook B.Tech (EEE) 2018 Q.11. what are the basic components of Threshold voltage (V TO or V TH )? Derive an expression for the same with and without body or substrate effect. Q.12. Explain non-ideal I - V effects in MOS. Q.13. Discuss Gate capacitance model and diffusion capacitance model of MOS. Q.14. Consider the MOS transistor with following parameters: t OX = 200A o, Ф GC = V, N A = 2 x cm - 3, Q OX = q x 2 x C / cm 2.Determine (a) the threshold voltage V TH under zero body bias at room temperature (T = 300K o ) given that ε OX = 3.97 ε 0 and ε Si = 11.7 ε 0 (b) Determine the type of MOS transistor (N Type or P Type ) and amount channel Implant in N / cm required to change the threshold voltage to 0.8 V. Q.15. Derive Drain current equations of MOS transistors (Enhancement N-Type or P- Type) using Gradual Channel approximation theory or model operating in the following regions (i) Linear (ii) Saturation (iii) Cutoff Q.16. Derive Drain current equations of MOS transistors (Enhancement N-Type or P- Type) using Channel length modulation theory or model operating in the following regions (i) Linear (ii) Saturation (iii) Cutoff Q.17. Explain how and when an N channel MOSFET (Enhancement N- MOSFET) conduct current? Q.18. Explain how and when an P channel MOSFET (Enhancement P- MOSFET) conduct current? Q.19. Explain how a channel in MOSFET work for small values of V DS? Q.20. How much we will expect the static power dissipation of gate to be, if we set the inputs of a particular CMOS gate to voltages that correspond to valid logic levels? Q.21. Explain why the threshold voltage of Enhancement N-channel MOSFET is Positive quantity whereas the threshold voltage of Enhancement P-channel MOSFET is Negative quantity? Q.22. Consider the following N- channel MOS process, substrate doped N A = cm - 3, poly-silicon gate density; N A = 2x10 20 cm - 3, gate oxide thickness t OX = 500A o, and oxideinterface fixed charge density N OX = 4 x cm- 2.Determine (a) the threshold voltage V TH under zero body bias at room temperature (T = 300K o ) given that ε OX = 3.97 ε 0 and ε Si = 11.7 ε 0 (b) Determine the type of MOS transistor (N Type or P Type ) and amount channel Implant in N / cm required to change the threshold to 1V. Assume Ф F (gate ) = 0.55V. Q.23. Explain why we required BiCMOS circuits to derive large capacitive load (ON-chip loads and OFF chip loads)? Q.24. Explain the static behavior of basic BiCMOS inverter with resistive base pull-down. Also explain the Conventional BiCMOS inverter circuit with active base pull-down. Q.25. Compare the BiCMOS and CMOS with respect to basic designing parameters. What are the applications in complex logic circuits? Q.26 Design and implement the two input NAND and NOR gates Q.26. Explain the circuit operation of CMOS transmission gate (Pass gate). Q.27. Design and implement two input X-OR gate by using (i) Six transistor CMOS transmission gate (ii) Eight transistor CMOS transmission gate. Q.28. Explain why and how the effects that arise when the channel is taken SHORT in MOS structure (Devices)?

103 Student s Handbook B.Tech (EEE) 2018 Q.29. Explain why and how the effects that arise when the channel is taken NARROW in MOS structure (Devices)? Q.30. Compare voltage levels and noise margin for bipolar and CMOS logic family. Q.31. what is body affect? Discuss different parameters on which threshold voltage depends Q.32. Discuss the gate source and gate drain capacitance of a MOSFET.. Q.33.Calculate the gate capacitance of a MOSFET with following parameter. W = 8 μm, L = 0.5 μm, C ox = F/cm 2. Q.34. A CMOS inverter is built in a process where k n = 100 μa / V 2, V tn = +0.7V, k'p = 42 μa/ V 2, V tp =-0.8V, and a power supply of V DD =3.33V is used.find mid point voltage V M if (W/L)n =10 and (W/L)p = 14. Q.35. Find g m for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10; μn Cox = 92 μa/v 2. Q.36. A PMOS transistor is operated in triode region with the following parameters. VGS= - 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, μncox =95μA/V2. Find its drain current and drain source resistance. Q.37. Explain Accumulation, Depletion layers in MOs with Energy band diagram. Q.38. Derive an expression for Depletion depth and Max Depletion depth in MOS structure. Q.39. Describe the structure and operation of MOSFET with its characteristics. Q.40. Explain the static behavior of basic BiCMOS inverter with resistive base pull-down. Also Q.41. explain the Conventional BiCMOS inverter circuit with active base pull-down. Q.42. A PMOS transistor is operated in triode region with the following parameters. V GS = - 4.5V, V tp = -1V; VDS=-2.2 V, (W/L) =95, μn.cox =95μA/V2. Find its drain current and drain source resistance. Q.43. Explain and Draw the V-I characteristics of P - Depletion type-mosfet (D-MOS). Explain and Draw the V-I characteristics of N - Enhancement type-mosfet (E-MOS). Explain how inversion or channel is created in MOs with Energy band diagram. Derive an expression for offset Depletion depth and Max Depletion depth in MOS structure. Describe the structure and operation of Enhancement N- MOSFET with its characteristics. A NMOS transistor is operated in triode region with the following parameters. V GS = 4.5V, V tp = 1V; VDS=2.2 V, (W/L) =95, μn.cox =95μA/V2. Find its drain current and drain source resistance. Explain and Draw the V-I characteristics of N - Depletion type-mosfet (D-MOS). Explain and Draw the V-I characteristics of N - Enhancement type-mosfet (E-MOS). Explain why we required BiCMOS circuits to derive large capacitive load (ON-chip loads and OFF chip loads)? Explain and Draw the V-I characteristics of P - Depletion type-mosfet (D-MOS). Explain and Draw the V-I characteristics of P - Enhancement type-mosfet (E-MOS). Calculate the gate capacitance of a MOSFET with following parameter. W = 10 μm, L = 1 μm, C ox = F/cm 2. Findg m for an p-channel transistor with Vgs= -1.2V: Vtn = - 0.8V; (W/L) = 10; μn Cox = 90 μa/v 2.

104 Student s Handbook B.Tech (EEE) 2018 What are the basic components of Threshold voltage (V TO or V TH )? Derive an expression for the same with and without body or substrate effect. Explain how much short & narrow channel threshold voltage changes? Calculate and explain Design and implement two inputs dynamic CMOS transmission X-OR gate Explain the charging and discharging time and voltage across the parasitic capacitance Implement the followings using N-MOS dynamic logic function (i) Z = ( AB + CD + E ) o (ii) Z = {(D +E + A)(B + C)} Implement the followings using C-MOS dynamic logic function and (i) Z = ( AB + CD + E ) o (ii) Z= {(D +E + A)(B + C)} Draw the mask-layout diagram of two input NAND and NOR using CMOS. Draw the stick diagram of two input NAND and NOR using CMOS. Calculate junction capacitance with and without side walls between drain and substrate. What do you mean by Scaling and small geometry effects in VLSI design for MOS? What are advantages and disadvantages of constant Electric field scaling over constant voltage scaling. Derive an expression for drain current in linear region, saturation region through gradual channel approximation and Channel length modulation for NMOS. Unit 2 Q.1. Explain the VTC (Voltage transfer characteristics) of NMOS Inverter with (i) resistive load (ii) Active loads. Also calculate V IL, V IH, V OL, V OH, V TH,also analyze Power consumption, Chip area, Noise margins. Q.2. Design and implement 1-bit full adder logic circuit using C - MOS. Q.3. Short note on spice for circuit simulation. Explain the VLSI Design flow diagram? Q.4. Draw layout and stick diagram of the logic functions: (i) Z = ( AB + CD + E ) (ii) {(D +E + A)(B + C)} using CMOS. Q.5. Implement and explain two inputs NOR & NAND gate using N-MOS with resistive and active load. Q.6. Explain the static and dynamic behavior of CMOS Inverter. Also calculate V IL, V IH, V OL, V OH, V TH,also analyze Power consumption, Chip area, Noise margins. What is the criteria for threshold voltage for high level and low level in inverter characteristicss? Q.7. Implement the circuit diagram and the corresponding layout and stick diagram of a two inputs NOR & NAND gate using C-MOS technology. Q.8. Design and Implement the following with C-MOS transmission gate (i) Two input multiplexer circuit i.e. F = AS + BS (ii) Two input XOR gate i.e. F = AB +A B (iii) F = AB + A C + AB C Q.9. Explain the logical operation to transfer logic 0 or 1 though dynamic MOS logic. And Explain the concept of charge leakage and storage through the dynamic MOS logic. Also explain why we do require the voltage bootstrapping in dynamic MOS logic? Q.10. Differentiate between ratioed and ratioless dynamic logic explain with example. Q.11. Write a note on spice for VLSI circuits simulation.

105 Student s Handbook B.Tech (EEE) 2018 Q.12. Design and implement half adder logic circuit using C - MOS. Q.13. Explain CMOS inverter layout plan along with its cross-sectional diagram. What is a stick diagram? What do you mean by Lemda based design rule? Q.14. Explain the operation of CMOS inverter when V in = V th. Q.15. Explain What is the propagation delay limitations in the CMOS digital integrated circuits? Q.16. Implement and draw the circuit schematic of a (2 x 1)- multiplexer using CMOS transmission gates. Q.17. With the help of a neat circuit diagram show the implementation of the logic function:. Y = A + (B + C). (D +E) using Ratioed CMOS logic. Q.18. Design a circuit described by the function Y = A. (B + C). (D + E) using CMOS logic. Also find the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming that (W /L) P = 5 for all P - MOS transistors and (W /L) N = 2 for all N - MOS transistors and Q.19. Derive and calculate the switching threshold voltage V th of two-input CMOS NOR gate with the following parameters: (W /L) P = 4 for all P-MOS transistors and(w /L) N = 1 for all N - MOS transistors, (V TO ) for N = 0.7V, (V TO ) for P =- 0.7V, µ n C OX = 40 µa/ V 2, µ p C OX = 20 µa/ V 2, V DD = 5V. Q.20. Discuss how the charge sharing problem can be overcome in dynamic CMOS logic? Q.21. Calculate the values of V OH, V OL, V IH, V IL and noise margin NM L for a saturated Enhancement load N-MOS inverter circuit. Given V DD = 5V, V T = V TO = 0.8V and k driver / k load =10. Q.22. Determine Z pu to Z pd ratio for N-MOS inverter driven through one or more pass transistor. Q.23. Consider the MOS transistor with following parameters: t OX = 250A o, Ф GC = -0.95V, N D = 3 x cm - 3, Q OX = 4 x C / cm 2.Determine (a) the threshold voltage V TH under zero body bias at room temperature (T = 300K o ) given that ε OX = 3.97 ε 0 and ε Si = 11.7 ε 0 (b) Determine the type of MOS transistor (N Type or P Type ) and amount channel Implant in N / cm required to change the threshold voltage to -1.5 V. Q.24. Explain the VTC (Voltage transfer characteristics) of CMOS Inverter. Also calculate V IL, V IH, V OL, V OH, V TH, for N-MOS with depletion load. Also analyze Power consumption, Chip area, Noise margins. Q.25. Design and implement the following using NMOS, CMOS (i)z = ( AB + CD + E ) (ii) Z = {(D +E + A)(B + C)} (iii)z = ( AB + CD + E ) (iv) Z = {(D +E + A)(B + C)} Unit-3 Q.1. Design and implement clocked (positive edge trigger) J-K, S-R, T, D flip-flops sequential logic circuit using C MOS with timing diagrams. Q.2.Explain the design of standard cells for VLSI circuits. What are the design considerations for digital ICs? Q.3. Design and implement clocked (negative edge trigger) J-K, S-R, T, D flip-flops sequential logic circuit using C MOS with timing diagrams. Q.4. what do you understand by the term excitation table? Show the excitation tables for SR, JK, T, D flip-flops. Q.5. explain the time and phase behavior of a CMOS bistable element with circuit diagram. Q.6 Explain the operation of two input NOR and NAND based SR, JK, D, T latch using CMOS. Q.7. Explain the operation of two input NOR and NAND based SR, JK, D, T latch using NMOS with depletion load.

106 Student s Handbook B.Tech (EEE) 2018 Q.8.Design and implement JK latch using CMOS. Q.9.Design and implement Master-slave FF consisting NAND based JK latches with output timing waveforms. Q.10 Explain the CMOS D latch that showing the setup time and hold time. Q.11 Design and implement the schematic of CMOS negative (falling) edge triggered master slave based on D FF. Q.12. Design and implement three input NAND based positive (rising) edge triggered D FF with timing diagram of input and outputs. Q.13 Design and implement Enhancement-load dynamic shift register (ratioed logic). Q.14 Design and implement Enhancement-load dynamic shift register (ratioless logic). Q.15. Explain the operation of basic building block of a CMOS transmission gate dynamic shift register Q.16. Design and implement the following function using dynamic CMOS logic gate: F = (A.B.C + D.E). Unit-4 Q.1. Classify the memories on the basis of technology. Explain the read and write operation of Static RAM ( SRAM ) with schematic circuit diagram. How 1 bit cell is used for bigger memory systems Q.2. Discuss the architecture of CPLD in detail. State the advantages of FPGA and CPLD design methods. Q.3. Explain the ASIC design flow and different types of ASIC. Also explain the programmable structures for PLA. Q.4. Design and implement a BCD to Gray code convertor circuit using PAL. Q.5. Explain SRAM, DRAM, FLASH memories on the basis of technology. Explain the read and write operation of Dynamic RAM ( DRAM ). Q.6. Discuss the architecture of FPGA in Detail. Also differentiate between FPGA and CPLD. Q.7. Explain the function of CPLD with each block in detail. Q.8. Design and implement a circuit using PAL for the following functions: F 1 = X.Y.Z + X.Y F 2 = W.F + W.X.Y.Z Also explain the programmable structures for PAL. Q.9. Using an FPGA discuss the programming required for the implementation of following cases: (i) 2 input NOR gate (ii) 2 input NAND gate (iii) 2 input AND gate (iv) 2 input OR gate Q.10. With help of suitable diagram explain a typical CLB available in the FPGAs. Q.11. Explain the Read/write operation and equivalent circuits of following memory cells (i)dram (ii)sram (iii) Mask (fuse) ROM (iv) EPROM (v) EEPROM (vi) flash RAM Q.12. Explain RAM array memory organization with complete block diagram. Q.13 Explain the concept of leakage currents in DRAM. How DRAM are refreshed? Q.14 Explain the concept of leakage currents in SRAM. How SRAM are refreshed? Q.15. What are data programming and erasing technologies in flash memory? Q.16.Design and implement NAND and NOR based flash memory cell. Q.17. what is the basis for standard-cell? What are basic classes of circuits for Library cells? Q.18. Explain the methods of programming of PAL CMOS device. Draw and explain the architecture of an FPGA.

107 Student s Handbook B.Tech (EEE) 2018 Q.19. What are different classes of Programmable CMOS devices? Explain them briefly. Q.20. What are the advantages and disadvantages of the reconfiguration. Q.21. Mention different advantages of Anti fuse Technology. Q.22. Using PLA Implement Full-adder circuit. Q.23. Compare the Antifuse and Vialink programmable interconnections for PAL devices. Q.24. What are different typically available SSI Standard-cell types and compare them. Q.25. Draw the diagram of programmed I/O pad and explain how the antifuses are used in this. Q.26.Draw and explain the AND/OR representation of PLA. Q.27. what are the differences between a gate array chip and standard-cell chip? What benefits does each implementation style have? Q.28. Write the equations for a full adder in SOP form. Sketch a 3-input, 2- output PLA implementing this logic. Q.29. Draw the typical architecture of PAL and explain the operation of it. Q.30. what is CPLD? Draw its basic structure and give its applications. Q.31. Draw and explain the Antifuse Structure for programming the PAL device. Q.32. Explain how the I/O pad is programmed in FPGA. Q.33. what are different classes of Programmable CMOS devices? Explain them briefly. Q.34. Draw the typical standard-cell structure showing regular-power cell and explain it. Q.35. What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure. Q.36.Explain any one chip architecture that used the antifuse and give its advantage. Q.37. Draw the structure, explain the function and write the applications characteristics of the following programmable CMOS devices: (a) PLA (b) PAL (c) FPGA (d) CPLD Q.38. Draw the typical standard-cell structure showing low-power cell and explain it. Q.39. Sketch a diagram for two inputs XOR using PLA and explain its operation with the help of truth table. Unit-5 Q.1. What is need of VLSI testing at various levels? Explain the design strategies for VLSI testing with block diagram for various logic. Q. 2. Discuss in details testing and verification of VLSI circuits. Q.3. what do you mean by silicon debug principles? Explain briefly test benches and hardness. Q.5. Boundary scan test techniques are grouped by the IEEE standards organisation into standard access port and boundary scan architecture. Write down atleast four advantages of boundary scan test. Q.6. Explain in detail Built-in self test (BIST) for circuit testing in VLSI. Q.7 Explain the various Fault types and Fault models in VLSI circuits. Q.8 what do you mean by electric logical stuck-at-0 and stuck-at-1 faults, explain with suitable example. Q.9. Define the terms Controllability and Observability for VLSI circuits testing with example. Q.10. Explain Ad-Hoc testing techniques for VLSI circuits testing with example.

108 Student s Handbook B.Tech (EEE) 2018 Q.11. Explain Scan-Based techniques for VLSI circuits testing with example. Q.12. Explain Current monitoring I DDQ techniques for VLSI circuits testing with example. Q.13. Which testing techniques are used for sequential logic circuits. Explain with example Q.14. Explain how function of system can be tested. Q.15.Why the chip testing is needed? At what levels testing a chip can occur? Q.16. What is the drawback of serial scan? How to overcome this? Q.17. A sequential circuit with in? inputs and m storage devices. To test this circuit how many test vectors are require? Q.18. Explain the ATPG with respect to CMOS based chip testing: Q.19. Explain how the cost of chip can effect with the testing levels, Q.20. How the Iterative Logic Array Testing can be reduced number of tests. Q.21. What type of defects are tested in manufacturing testing methods? Q.22. Explain the manufacturing test of a chip with suitable examples. Q.23. Explain how an Ad-hoc test technique used to test long counters? Q.24.Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout.

109 Student s Handbook B.Tech (EEE) Explain how an Ad-hoc test technique used to test long counters. November 2008 set4 2. Explain the gate level and function level of testing. 3. A sequential circuit with n inputs and m storage devices. To test this circuit how many test vectors are required? 4. What is sequential fault grading? Explain how it is analyzed. 5. Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout. 6. Draw a schematic for a CMOS edge-sensitive scan-register and also draw some circuit level diagrams of its implementation. 7. Explain how function of system can be tested. 8. Explain any one of the method of testing bridge faults. 9. What type of faults can be reduced by improving layout design? 10. Explain the functionality test of a chip with suitable examples. 11. What are the categories of Design for testability? Explain them briefly

110 6.5 Data Structure using C++ Student s Handbook B.Tech (EEE) 2018 Course Name: Data Structure using C++ Question Bank Course Code:TCS-607 Branch: EEE Semester: VI Faculty :Mr. Himanshu Dewedi Unit/Title: UNIT- Date of Issue: Date of Submission: UNIT 1 1. Describe time and space complexity. Discuss best, average and worst case for finding a given number from an array of integers? 2. Explain the difference types of data structure. What data structure will you use to store the information of students of your class? Why? 3. Devise insertion and deletion function for doubly linked list? 4. How is a class declared in C++? 5. What do you understand by worst case, average case and best case time complexity of an algorithm? 6. Write an algorithm to concatenate two circularly linked lists pointed by list 1 and list 2 in such a way that circular list pointed by list 2 is appended to the circular list pointed by list 1? [JNTU 2007] 7. How can a polynomial in two variables be represented by a singly linked list? Write an algorithm to add two such polynomials?. 8. Define algorithm and data structure. Give the difference between linear and non-linear data structures with example? Define time complexity. Explain Big oh (O) notation? 9. Write a C++ program to construct and delete elements in a circular queue using linked list? 10. Write a program to delete a node in a doubly linked list? 11. Compare the dynamic implementation of a linear linked list? 12. Write an algorithm to merge two singly linked list whose elements are sorted in ascending order to produce a single singly linked list sorted in ascending order? 13. Discuss performance analysis and measurement of programs? [RTU 2008] 14. Discuss radix sort algorithm with an example? 15. Compare dynamic and array implementation of a linked list? 16. Write an algorithm to delete a node on the left of a given node of a doubly linked list? 17. What is the structure to represent a node in skip list? 18. How is a skip list different from linear list. Illustrate with suitable example the insertion and deletion operations on skip lists? 19. Write the constructor for skip list? 20. Illustrate using a suitable example to delete a given node in doubly linked list?

111 Student s Handbook B.Tech (EEE) 2018 UNIT-2: STACKS AND QUEUES 1. State the Towers of Hanoi problem. Write recursive algorithm to solve the problem? 2. Write an algorithm for matching different parantheses such as {, [, ( in an algebraic expression? 3. Explain the concept of Exception handling mechanism with example code? 4. Define abstract data type. Explain it briefly? [Differentiate between dequeue and priority queue? 5. What is an ADT? Show the insert and remove operations in/from the Queue ADT during the traversal in a tabular fashion? 6. Write a C++ program to implement stack and its operations, PUSH and POP? 7. Write a complete program in C to implement stack using liked list? 8. What is priority queue? How it is implemented? Take an example to show your implementation? 9. Devise function in C which check for Full and Empty for a circular queue. Also find out the number of elements in circular queue? 10. Write short notes on: a. Queue b. Circular queue c. Dequeue 11. Write down advantages of dynamic representation over static representation of queue? OR How queue can be represented in memory? 12. What is a stack, explain with its applications? 13. Write an algorithm which reverses the order of elements on stack using one additional stack and some additional variables? 14. Design a method for keeping two stacks within a single array so that neither stack overflows until all of the memory is used.write a procedure to perform PUSH(x,s) that pushes element x onto stack s, where s is one of the two stcks. Include all necessary error checks? UNIT-3: HASHING 1. What is hashing? Classify hashing functions based on the various method? 2. Define hash function. What do you mean by perfect hash function? 3. Write an algorithm for searching an algorithm using linear search method?. 4. Discuss various methods used for resolving hash collisions? 5. Explain linear probing and quadratic probing using a suitable example? 6. What is a hash table, explain its applications? 7. Show the working of Huffman algorithm. with an example. Also write the applications of huffman s algorithm? 8. What is the difference between indexing and hashing? 9. How many passes are required for k-way merging? 10. How can hash tables be used in text compression? 11. Explain LZW algorithm, for what purpose it is used? 12. Insert the following values into a hash table of size 10 using the hash equation (x2 +1) % 10 using the linear probing technique. Insert these values in sequential order: 1,2,5,6, 8? 13. Use linear probing to insert pairs whose keys in order are 7, 42, 25, 70, 14, 38, 8, 21, 34, 11 into a hash table with b = 13 buckets using the hash function f(k) = k mod b. start with an empty hash table and draw the hash table following each insert?

112 Student s Handbook B.Tech (EEE) 2018 UNIT-4: TREES 1. Show that the maximum number of nodes in a binary tree of height h is 2 h+1-1? Formulate an algorithm to find the number of leaf nodes in a binary tree. What is the time complexity of your algorithm? 1. What is a binary tree? Discuss various types of binary trees with suitable diagrams?. 2. Explain how an element is inserted in to a min-max heap with suitable example?. a. Define the following with respect to a tree b. Degree of a node c. Terminal node d. Siblings e. Degree of a tree f. Depth of a tree 3. What is a priority queue?. Explain how it can be implemented? 4. What is a heap? Explain how an array of integers can be sorted using heap sort method. Given 20, 55, 46, 34, 13, 90, 87, 32 are elements of an array, show the different stages of sorting? 5. Write an algorithm to construct a binaty tree for the input 14, 15, 4, 9, 7, 18, 3, 5, 16, 4, 20, 17, 9 indicating a message for duplicate members? Draw the tree constructed by the above program? 6. Write a short note on external sorting method? How can we use winner trees in mergesort? 7. What do you mean by heap sort? Explain and write analysis of heap sort? 8. Write a recursive procedure which finds the number of nodes in a tree? 9. A binary tree has 9 nodes. The inorder and preorder traversals yields follwing sequence Inorder: E A C K F H D B G Preorder: A E K C D H G B Draw the tree? 10. Traverse the following tree in inorder, preorder, postorder 10. Write applications of tree data structures? 11. What is a binary tree? Explain how it can be represented in memory? 12. The following keys are to be inserted in the order shown below into an B-tree (of order 5): a, g, f, b, k, d, h, m, j, e, s, i, r, x. Show how the tree appears after each insertion? 13. Define the heap? How a priority heap can be implemented using a heap? 14. The following keys are to be inserted in the order into a heap: 25, 57, 48, 37, 9, 97, 86, 33.Show how the tree appears after each insertion. 15. Draw all non similar trees with exactly 6 nodes?

113 Student s Handbook B.Tech (EEE) 2018 UNIT-5: GRAPHS 1. Write a short note on Tournament trees? 2. Write an algorithm to check whether a graph is connected or not? 3. Write an algorithm which counts the number of connected components in a graph? 4. Define adjacency matrix corresponding to a diagraph? 5. Explain spanning tree and draw a spanning tree for the following graph 6. For the following graph find (i) BFS traversal (ii) DFS traversal 7. Draw the graph corresponding to the following bit matrix: A= Explain the various graph representation techniques? 9. Define leftiest trees? 10. The following is the adjacency matrix A of an undirected graph G: A=