Ph.D. Defense. Broadband Power Amplifier

Transcription

1 Ph.D. Defense GaN HEMTs based Flip-chip Integrated Broadband Power Amplifier Jane Xu University of California at Santa Barbara Committee: Prof. Stephen Long Prof. Umesh Mishra Dr. Yi-feng Wu Prof. Bob York(Chairperson)

2 Outline GaN power HEMTs design Small device evaluation (100µm) Large device design Thermal management (Flip-chip mounting) GaN broadband power amplifier design Limit of conventional TWA GaN modified TWA GaN LCR-matched PA GaN 2 2 matrix modified TWA Conclusions

3 Why AlGaN/GaN HEMTs? Wide E g GaN High v s High V br High Power Level High Frequency (f t ) High I max High Efficiency (PAE) AlGaN/GaN HEMTs High n s High µ low R on (low V knee ) High Operating Temp Promising Microwave Power Device

4 Power Device Realization Flow (5-6 masks & dicing) MOCVD growth of Al x Ga 1-x N/GaN HEMTs Device Process Ohmic Contact (Source and Drain) Pad Isolation & Schottky Contact(Gate) Mesa Isolation DC & RF measurement on small device Power Density, Gain, PAE P out Large Area Device Process out > 3W/mm? Bonding Bumps Air-bridges Dicing Wafer Into Discrete Devices Ready for Bonding to Circuit No Dicing Flip-chip Bonding Yes Start Ready

5 Power Device Design Flow Evaluation of small FET DC & RF, Power Density, Gain Total gate width Power, Impedance Unit gate finger width Gain (loss,phase delay) Gate-gate pitch Thermal Issue, Bonding pad Number of fingers/pad Uniform operation, Parasitic Pattern layout Parasitic,Thermal Resistance

6 Evaluation of small devices (100µ( 100µm) 1) DC characterization 2) Dispersion 3) RF characterization 4) Immature GaN material

7 100 µm Unit FET S D Source Pad Ohmic Contact UID AlGaN Cap Si-doped AlGaN Electron gas Substrate Gate Pad Gate finger Gate Pad Isolation & Schottky Contact S G D UID AlGaN Cap Si-doped AlGaN Electron gas Substrate Drain Pad S G D Mesa Mesa Isolation Electron gas Substrate

8 P out DC Characterization Expected Power Density for GaN on Sapphire 1 = I max ( Vbr Vknee) P out = 5.6 W/mm 8 I d I max V knee +1.5 V V gs V V V d br V knee: ~ 5 V I max : ~ 1000mA/mm V pinch : ~ - 5 V V br : ~ 50 V G m-ext : ~ 200 ms/mm

9 Effect of Traps in GaN Materials RF I-V I max RF I-V: I max V knee RF I max V knee V knee V br P out PAE Reasons: Traps in AlGaN & GaN, Surface States,etc

10 Maximum Power Density and PAE (100 µm device) P out out = 4.6 W/mm, PAE = 40% V d = 25 V, I d = 200 ma/mm P out = 3.6 W/mm, PAE = 52% V d =18 V, I d = 200 ma/mm P out Gain PAE 60 P out (dbm) & Gain(dB) Pout Gain PAE PAE (%) B ) (d G ain & ) m B (d t P ou P A E( % ) P (dbm) in Freq (GHz)

11 Immaturity of GaN materials Material NonUniformity across Wafer Typical map of power density Power density: 1-4 W/mm 2 3 W/mm 3 4 W/mm Issues: Non-uniformity of the Wafer % Dispersion Variation % to 50-60% Breakdown Voltage Limit V High Dislocation Density 1 2 W/mm 2 3 W/mm ~ 10 8 cm -2 Poor Reliability Overdriven failure

12 f t and f max Gain(dB) L g = 0.7 µm, ds = 15 V, I ds = 400mA/mm MSG h 21 2 UPG MAG S 21 2 f t (20GHz) ff t =g gs )=v s /L t = g m /(2πC gs g )=v s /L g f max t (R ds /R in ) 1/2 max =0.5*f t * (R( ds /R in ) 1/2 Reduce L g g * Reduce R in * in Increase R ds ds f max * * R in = g +R gs +R s in = R g +R gs +R s f max (38GHz) f (GHz)

13 Large-periphery Device Design 1) Pattern layout 2) Thermal management 3) Results and problems 4) Optimum Load

14 Multi-finger FET Design How to choose L gg, W gu, n? Air-bridges Bonding Pads L gg W gu Number of Gate Pads (n-1)*l gg

15 Unit Gate Finger Width x r g l g r gs V 0 0 x c gs γ = α + jβ = Z Y = + 1/ V0 γ x γ (2 Wgu x) V( x) = ( e + e ) 2 wgu 1 wgu 2 P = P ( x) dx= P V( x) dx out out out _ ideal 0 4W 0 gu r gs r g + jwl g jwc gs, For gate length L g = 0.7µm: r g = 65 Ω/mm r gs =1.2 Ω /mm l =36 ph/mm g c gs =2.5 pf/mm Gain Degradation < 2 db: C-band:<200µm X-band:<100 µm Ku-band:<75 µm

16 Trade-off In Gate Spacing L gg Large (n-1)l gg Phase rotation Non-uniform operation Lower Gain (materials and process variation) Non-uniform channel temperature Additional parasitics & losses Large L gg Lower R th (n-1)*l gg (n-1)*l gg < λ / 16 (760 µm for GaN) N = 10 L gg = ~ 50 µm

17 Large-periphery Device Design 1) Pattern layout 2) Thermal management 3) Results and problems 4) Optimum load

18 Thermal Management of Power Devices More power dissipation Temperature Electron mobility Gain I max Output power S G D G S Back-side Heat-sink Via-holes Problems for Via-holes of GaN: GaN HEMTS on Sapphire very difficult to etch GaN HEMTS on SiC need develop complex process Introduce parasitic L S

19 Flip-chip Technology Advantages: Minimum parasitics S G S Better thermal management Sapphire: σ = 30 W/mK S D S AlN: σ = 180 W/mK Bonding Bumps Cost effective AlN Substrate

20 Flip-Chip Mounting E-beam evaporation of Au bonding bumps Align FET chip with circuit board using flip-chip bonder Bond with pressure and temp Heat & Pressure Sapphire Substrate D GaN Epi S AlN Substrate Good Heat Sink Gold Bumps Sapphire Substrate D GaN Epi S AlN Substrate Good Heat Sink Gold Bumps

21 Thermal Management using Flip-chip bonding T ( C) For 4 W/mm T>200C w/o flip-chip bonding T < 60 C with flip-chip bonding (Finite Element Simulation) Sapphire ( σ = 30W/mK) GaN (σ = 110 W/mK) Copper ( σ = 390 W/mK) SiC ( σ = 500 W/mK) T (C) µm GaN on SiC 2 µm thick GaN buffer 4 µm thick GaN buffer GaN Epi Thickness (µm) Au Layer Thickness (µm)

22 Experimental comparison of a device before/after flip-chip bonding Cur/Div. 200 ma/mm Volt/Div. 2 V Per Step 1.0V Offset 1.0 V gm/div. 10 ms 50 µm x 0.25 µm Gate MODFETs before bonding 1.1 A/mm, 200 ms/mm Cur/Div. 200 ma/mm Volt/Div. 2 V Per Step 1.0V Offset 1.0 V gm/div. 10 ms 50 µm x 0.25 µm Gate MODFETs after bonding 1.6 A/mm, 280 ms/mm Dramatic improvement in both I d,max and g m due to heat sinking d,max

23 Large-periphery Device Design 1) Pattern layout 2) Thermal management 3) Results and problems 4) Optimum load

24 Flip-chip Bonded 1-mm GaN HEMT(L g =0.75um) P out (dbm) P out = 4.4 W PAE = 35% V ds = 27V f = 8 GHz PAE(%) I max = 800 ma

25 Flip-chip Bonded 2-mm GaN HEMT P out = 6.3 Watt, PAE = 32 %, Gain = 13 db V ds = 25 V, f = 4 GHz, class AB B ) (d P out G ain & ) m B (d t P ou Gain PAE P A E( % ) P (dbm) in

26 Performance GaN vs. GaAs Jane s GaN HEMT (W g = 1mm, L g = 0.7 µm) Triquint s GaAs HFET (W g = 1.2mm, L g = 0.5 µm) V br (V) I max (A/mm) V knee (V) P out (dbm/w) PAE (%) Gain (@8GHz) R opt (Ω Ω mm) GaAs / GaN /

27 Mm-wide GaN HEMTs Power Performances Device size I max /DC (ma) Gain(dB) Power (Watt) PAE (%) 1mm * 800 ~ mm ** 1500 ~ mm 2800 ~ 3200??? *: RF measurement was performed at 8 GHz. **: RF measurement was performed at 4 GHz. Practical Issues: Flip-chip bonding limit ATN loadpull measurement power & biasing limit Low yield

28 Non-scalable Property of Large Devices 1mm to 2mm: DC I max : 10 20% drop Gain: 3dB drop Power: 2dB drop PAE: 5% drop 1mm device Connection parasitics & losses Non-uniform channel temperature Non-uniform operation Self-heating Phase rotation Conclusion: Use multiple small-area discrete devices

29 Large-periphery device design 1) Pattern layout 2) Thermal management 3) Results and problems 4) Optimum load

30 Optimum Load I d R=R opt R > R opt I max ½ I max bias point R < R opt Vbr Vknee Ropt = Idss 1 PRF,max = Imax ( Vbr V knee) 8 0 V knee V bias V br V d For R >R opt : For R < R opt : 1 ( V V ) R P P P 2 RF = 2 br knee opt = RF,max < RL RL RF,max 1 R P = I R = P < P 2 L RF max L RF,max RF,max 8 Ropt

31 Effect of C ds I dss 1/R opt R ds C ds R opt V knee V br Effect of C ds : Reducing maximum P out especially near f ~ 1/2πR opt C ds (15 GHz) GaN HEMT C ds must be compensated for optimum design

32 C ds Compensation From Loadpull Measurement: R opt =32! mm, C ds = 0.3 pf/mm R opt = 15 Ω R=15 Ω 2-section LC matching network C ds =0.6pF R=50 Ω 2mm-GaN C ds Compensation

33 Broadband power amplifier design 1) Limitation of conventional TWA 2) Modified TWA 3) LCR-matched PA 4) 2 2 matrix modified TWA

34 Conventional TWA Efficiency Limitation I d /2 I d /2 Z d,e Drain line dummy load R L Out Devices In Z g,e Gate line dummy load Output efficiency 50% Class-A efficiency 50% Maximum efficiency < 25% Pout Pin 1 PAE = = DE (1 ) P G G < 10 db PAE < 20% DC

35 Conventional TWA Power Limitation Largest Voltage across last FET < V br Maximum P out fixed by device technology (Z 0 = 50Ω): P RF max = ( Vdr Vknee) 8Z 0 2 For GaAs FET: V dgb = 20 V, V pinch = -2.5V, V knee = 1 V, then P RFmax = 0.7 W For GaN HEMT: V dgb = 50 V, V pinch = -5V, V knee = 5 V, then P RFmax = 4 W

36 Tapered Drain-line TWA Z1 Z1 2 Z1 3 Z1 4 Z1 Z1 4 Out Device Device Device Device In Zg, τ Zo Cin P out cannot be increased device technology limit Efficiency can be improved by: forcing more current to the real load using less devices

37 Broadband power amplifier design 1) Limitation of conventional TWA 2) Modified TWA 3) LCR-matched PA 4) 2 2 matrix modified TWA

38 Modified GaN TWA Design Goal: Bandwidth: 8:1 (1 8 GHz) Gain ~ 10 db PAE > 20 % P out 6 Watt (2W/mm) Approach : Input distributed match Capacitive division Corporate power combiner GaAs prototype circuits Bandwidth & gain flatness Broadband Broadband & power Topology verification

39 Schematic of GaN Modified TWA Fig. 1 Z d =R opt Z1 Z2 Z3 Z4 Z5 Out 0.75 mm GaN HEMTs In c1 c2 c3 c4 Zg,E Corporate Power Combiner 50 ohm Modified TWA: 1)Eliminate backward wave wave 3)High 3)High efficient corporate combiner 2)Broad band band 4)Avoid high high impedance lines lines

40 Equivalent of Tapered Drain-lines Zd =Ropt Out Z1 Z2 Z3 Z4 Z5 GaN HEMT Corporate Power Combiner In c1 c2 c3 c4 Zg,E 50 ohm Z1 Z1 2 Z1 3 Z1 4 Z1 Z1 4 Out Device Device Device Device In Zg, τ Zo Cin

41 Concept of the Capacitor-division TWA For power FETs, large C gs is limiting the bandwidth Z gate L gate = = 50Ω C gate Cgs Corporate combiner RF OUT f C brag gate = = π C in in L C C 1 gate gs + C C gs gate RF IN FET1 FET2 FET3 FET4 Cin1 Cin2 Cin3 Cin4 Lgate/2 Lgate Lgate Lgate Lgate/2 50 ohm Compensate the gate line loss by increasing the capacitance ( C in4 > C in3 > C in2 > C in1 ) C inx Vx = Vin x = 1, 2, 3... N C + C inx gs

42 Broadband Matching Define: Bandwidth > 3:1 (f High /f Low ) High Impedance Transformation Ratio High Impedance Transformation Ratio (4mm device): Input: 50 : 1 Distributed match (50 Ω / 1 Ω) LCR lossy match Output: 6:1 Corporate power divider (50 Ω / 8 Ω) Multi-section LC match

43 Single-section Wilkinson Power Combiner Bandwidth: 2:1 S 11 (db) Port 1-5 S 33 (db) Z 0 λ/4 2 Z 0 Z R B d -25 Port Z 0-35 Port 2 Z Freq (GHz)

44 Bandwidth of λ/4 Transformer To have bandwidth 3 to 1 λ/4 transformer ratio < 1.5: Ratio 4:1 Ratio 3:1 Ratio 2:1 Ratio 1.5:1 B ) (d S Freq(GHz)

45 N-way & Corporate Combiner (to extend bandwidth) 100 ohm 100 ohm ohm 50 ohm Multi-section λ/4 Transformers N-way Combiner 100 ohm 107Ω 107Ω 107 Ω 107 Ω 122Ω 122Ω 122 Ω 122 Ω 73Ω 73Ω 90Ω 90Ω 50Ω 50Ω Corporate Combiner

46 BW & Efficiency of Corporate Power Combiner Efficiency: > 80% 80% (1 (1 db db loss) loss) Bandwidth: ~ 10:1 10:1 (1 ( GHz) GHz) Disadvantage: Not Not Area-efficient (But (But AlN AlN carrier carrier cheap) cheap) Gain (db) Efficiency (%) f (GHZ) 64

47 1-8 GHz 1-watt GaAs Modified TWA Sparameters (db) S 11 S 12 S 21 S Freq (GHz) mm-wide 0.5µm-long GaAs PHEMT, out = 27 dbm,, PAE = 8GHz P out S G S S D S P out (dbm) and Gain(dB) P out Large-signal gain Small-signal gain Freq (GHz)

48 Delay Lines RF IN 17 mm Capacitor-division Modified TWA with Corporate Power Combiner Corporate Combiner RF OUT 12 mm B ) 10 0 d r ( -10 m ete a r -20 S -pa -30 P out (dbm) measured simulated S11 S22 S21 Fig. 1 S Freq (GHz) 35 Pout V ds =18 V I ds =400 ma PAE Freq (GHz) PAE (%)

49 Power Sweep at 4 GHz P out = 4.5 W, PAE = 14 ds = 22 V I ds = 400mA,f = 4GHz P out (dbm) & Gain (db) Pout PAE Gain P in (dbm) PAE (%)

50 Unequal Drive Problem Z α 1 = ω R C Z 2 2 g 2 c in gs 0 L Y R C L R C Z 0 Unequal drive: Reduce combing efficiency Reduce device reliability Gate attenuation is frequency dependent Compensated at one frequency

51 Broadband power amplifier design 1) Limitation of conventional TWA 2) Modified TWA 3) LCR-matched PA 4) 2 2 matrix modified TWA

52 LCR-matched PA Design Goal: Bandwidth: 3:1 (3 10 GHz) Gain ~ 10 db PAE > 20 % P out 8 Watt (2W/mm) Approach & Improvement: Input LCR lossy match Low Q LC match Corporate power combiner C ds compensation Gain flatness Broadband Broadband & power Higher power

53 Corporate Power Divider Schematic of LCR-matched Broadband GaN Power Amplifier L-C-R match S 11 * 1mm GaN HEMTs R opt Corporate Power Combiner Input LC Match Output LC Match Input LC Match Output LC Match In Z1 Z2 Z3 Z4 Z5 Z6 Out Input LC Match Output LC Match Input LC Match Output LC Match

54 Broadband Matching I Bandwidth > 3:1 (f High /f Low ) High Impedance Transformation Ratio (4mm device size): Input: 50 : 1 Distributed match (50 Ω / 1 Ω) LCR lossy match Output: 7:1 Corporate power divider (50 Ω / 8 Ω) Multi-section LC match

55 LCR Gain Compensation Network The network eliminates gain peaks at low band R also can be stabilizing resistor L C R Two-section LC network L L L LCR-network C C gs C R Equivalent of transmission line

56 Broadband Matching II Bandwidth > 3:1 (f High /f Low ) High Impedance Transformation Ratio (4mm device size): Input: 50 : 1 Distributed match (50 Ω / 1 Ω) LCR lossy match Output: 7:1 Corporate power divider (50 Ω / 8 Ω) Multi-section LC match

57 Single-section Lowpass LC Networks R S L R S L C R L C R L R L > R S R S > R L -X * P -X P R L R * L R S X S -X * P R * L

58 Define Q of LC Networks X R * P * L = = X R X 2 P L 2 2 P + RL X R X 2 P L 2 2 P + RL X S = X P * R S = R L * For R L > R S Q RL = 1 R S X S = ωl = R S Q, X P = 1/ ωc = R L /Q For R S > R L Q RS = 1 R L X P = 1/ ωc = R S /Q, X S = ωl =R L Q.

59 Multi-section(Low-Q) LC Matching Networks R 1 R 2 R 3 R N R S L L L L C C C C R L R s < R 1 < R 2 <...< R L R 1 / R s = R 2 / R 1 =...= R L / R N Q RL = 1 R S 1 RL N Q = ( ) 1 R S For Complex impedance,reactance can be absorbed into LC networks

60 LCR Matched 4mm GaN-based Power Amplifier 10 P out Gain : ~ 7dB, BW: 3-10 GHz out = 8. 5 W, PAE = 8 GHz 12 mm S-parameters (db) S21 S11 S22 S12 Input divider LC&LCR matching networks Output combiner Freq(GHz) 30 8 mm RF In RF Out P out (dbm) Pout(dBm) PAE(%) Flipped GaN HEMTs 15 PAE(%) Freq(GHz) 5

61 Power Sweep at 8 GHz P out out = 8.5 W, PAE 8 GHz (V d = 16 V, Id = 500 ma, class AB) P out (dbm)& Gain (db) P out Gain PAE PAE (%) P in (dbm) 0

62 Broadband power amplifier design 1) Limitation of conventional TWA 2) Modified TWA 3) LCR-matched PA 4) 2 2 matrix modified TWA

63 2 2 matrix Modified TWA Design Goal: Bandwidth: 6:1 (1-6 GHz) Gain > 10 db PAE > 15 % P out 8 Watt (2W/mm) Approach & Improvement: Modified TWA Bandwidth & equal drive Lower frequency: 1 6 GHz Higher gain Real air-bridges Better bonding Thicker CPW lines ( > 3 µm) Reduce conductive loss

64 Schematic of 2 2 Modified TWPA 1mm GaN HEMTs 15 Ω L 3 L 4 L 5 C 3 C 4 C 5 Z in L 1 L 2 L 3 L 4 L 5 C 1 C 2 Z d =R opt opt C 3 C 4 C 5 Z 1 Z 2 In L 3 L 4 L 5 Out Z in L 1 L 2 C 3 C 4 C 5 C 1 C 2 L 3 L 4 L 5 C 3 C 4 C 5 Z g,τ g /2 C in Z g,τ g C in 15 Ω Corporate Power Combiner

65 Better Equal Drive RF IN RF IN 15 Ω 50 Ω 2 22 gate feeding 1 44 gate feeding α 1 = ω R C Z 2 2 g 2 c in gs matrix TWA has better equal drive than 1 44 TWA

66 Curtice-3 Large-signal Model I = ( A + AV + AV + AV )tanhγv d V1 = Vgs 1 + β ( VOUTO Vds ) ds Assumption: V 1 = V gs A 2 = A 3 =0 Gm: constant ds : infinity R ds Conclusion: First order simulation Compatible with small-signal signal model

67 Simulation Results Gain: ~ 11 db BW: 1-7 GHz out : 6 8 W PAE: ~ 20 % P out Sparameters (GHz) S11(dB) S12(dB) S21(dB) S22(dB) P out (dbm) Pout(dB) PAE(%) PAE(%) Freq (GHz) Freq (GHz)

68 RF IN 10 mm Photos of the Circuit Circuit components: GaN HEMTs (4 X 1mm) MIM Capacitors, NiCr Resistors Air-Bridges 8 mm RF OUT Circuit with flipped GaN HEMTs Delay Lines Corporate Combiner

69 Small-signal and Large-signal Performance Gain: 9-12 db, BW: GHz V ds =10 V, I ds = 400 ma Pout: Watt, PAE: % V ds = 18V, I ds = 400 ma S 11 B ) (d s r m ete a S par S 21 S 12 S 22 B ) (d t P ou P out (db) PAE(%) Freq (GHz) Freq (GHz)

70 Circuits Performance Comparison P out (W) 3dB BW (GHz) Gain (db) PAE (%) Features GaAs modified BW,flat gain TWPA good match GaN modified BW,flat gain TWPA good match GaN LCRmatched PA power compact GaN 2 2 matrix modified TWPA BW,power PAE

71 Achievements High Power small GaN HEMTs (un-passivated passivated): P out = 4.6 W/mm, PAE = 40% High Power large-periphery GaN HEMTS : P out = 4.4 W, PAE = GaN Modified GaN TWPA: First GaN amplifier! GaN LCR - matched PA: P out up to 8.5 W (>2W/mm) GaN 2 2 matrix modified TWPA: Best overall performance

72 Conclusions Achievements: Demonstration of power-bandwidth advantage of GaN (0.7µm HEMTs-on on-sapphire technology) Future work: Optimization of GaN material and device technology Incorporate GaN amplifiers into spatially combined modules