Digital Downconverter (DDC) Reference Design. Introduction

Transcription

1 Digital Downconverter (DDC) Reference Design April 2003, ver. 2.0 Application Note 279 Introduction Much of the signal processing performed in modern wireless communications systems takes place in the digital domain, which greatly increases processing demands of modern digital modulator/demodulator applications. The high data rate, parallel processing capabilities of Altera programmable logic devices makes them an attractive solution for baseband/intermediate frequency (IF) digital signal processing (DSP) applications. By combining drop-in DSP cores from Altera s extensive intellectual property (IP) portfolio with Altera Stratix devices, complex high performance DSP designs can be implemented in a relatively short period of time. Altera provides a direct digital downconverter (DDC) reference design with the DSP Development Kit, Stratix Edition or DSP Development Kit, Stratix Professional Edition for use as either a design starting point or an experimental platform. A DDC demodulates a signal and then decimates it down to baseband. Designers typically use DDCs in digital receivers, in front-end demodulators and 3G wireless UMTS systems. The signal coming to the receiver often contains extra noise, which is removed by filtering and pulse shaping. The Altera DDC reference design consists of numerically controlled oscillators (NCOs), filters, and open-source Verilog HDL glue logic that supports 8 independent channels. The target device on the Stratix EP1S25 DSP development board is the EP1S25F780C5. The target device on the Stratix EP1S80 DSP development board is the EPS1S80B956C6. f Refer to the Stratix EP1S25 DSP Development Board Data Sheet for more information on the board. Refer to the Stratix EP1S80 DSP Development Board Data Sheet for more information on the board. When you install the software from the DSP Development Kit, Stratix Edition CD-ROM, the DDC design files are installed in the directory structure shown in Figure 1. Altera Corporation 1 AN

2 Figure 1. DDC Reference Design Directory Structure Stratix_DSP_kit-v<version> or Stratix_DSP_pro_kit-v<version> The Stratix_DSP_kit-v<version> directory contains the files for the EP1S25 DSP development board and the Stratix_DSP_pro_kit-v<version> directory contains the files for the EP1S80 board. Reference_Designs ddc doc Contains the reference design documentation. Projects Contains the ModelSim, Quartus II, and RTL source files. ModelSim Contains the ModelSim files. tcl Contains the ModelSim Tcl scripts. testbench Contains the simulation testbench. work ModelSim working directory. Quartus Contains the Quartus II design files. work Quartus II working directory. work_brd Quartus II project for evaluating the design on the DSP development board. RTL_Source Contains the RTL source files. mix Contains the digital mixer design files. st1_plus_fir Contains the stage 1 filter design files. st2_plus_fir Contains the stage 2 filter design files. st3_plus_fir Contains the stage 3 filter design files. top Contains the top level design files. Utilities Contains the design utilities, e.g., the signal generator and spectral plotters. ddc_sig_gen_cmd_line_src Contains the C/C++ source code for DDC signal generator command-line program. 2 Altera Corporation

3 Features The DDC modem reference design provides the following features: Input sample rate of millions of samples per second (MSPS) 8 UMTS channels Decimation factor of bit input samples 16-bit output samples 0.02-Hz tuning resolution > 80 db far band rejection > 110 db spurious free dynamic range (SFDR) using an 18-bit NCO Nyquist filtering for QPSK or QAM symbol data Signal generator utility to create a modulated input signal Spectral display utility to display the filter frequency response Functional Description Figure 2 shows the functional block diagram of a single DDC channel. The DDC consists of a front end digital mixer, which performs a frequency translation to baseband, and a three-stage digital filtering and decimation section. Figure 2. Single-Channel Digital Downconverter Functional Block Diagram I/Q Splitter & Mixer I (cos) 10 Decimate 2 10 Decimate 4 10 Decimate 3 16 I out Input 14 NCO Q (sin) 10 Decimate 2 10 Decimate 4 10 Decimate 3 16 Q out Digital Mixer The digital mixer comprises an NCO sinusoidal generation unit and two multipliers. The input signal is real data that is split into I and Q components by multiplication with a sine and cosine waveform (basic amplitude modulation), which results in a signal with a reduced amplitude and two frequency components generated for both the I and Q data streams. These streams contain the baseband signal and a secondary signal located at 2f C (when viewed in the frequency domain), where f C is the carrier frequency. This secondary signal, located in both the I and Q data streams, is removed during filtering and decimation. Altera Corporation 3

4 The DDC employs a precision NCO to demodulate the signal to baseband. For 3G UMTS applications, the input signal bandwidth is 3.84 MHz. This input signal is oversampled 24 times for a sample rate of MHz. The sine and cosine waveforms are phase offset by 90 degrees. The following equations describe the result of the I/Q splitting and mixing operation in the frequency domain (upon input signal x(t)). cos( ω c t) xt () 0.5 X( ω ω c ) X( ω + ω c ) sin( ω c t) xt () 0.5 X( ω ω c )j X( ω + ω c )j 3-Stage Filter The filter removes the 2f C component and noise, and shapes pulses in several stages: Stage 1 decimates by a factor of 2 Stage 2 decimates by a factor of 4 Stage 3 decimates by a factor of 3 The combined total decimation factor is 24. Figure 3. 3-Stage Filter Input Low-Pass Filter MHz MSPS Decimate by 2 Low-Pass Filter MHz MSPS Decimate by 4 Low-Pass Filter 5.76 MHz MSPS Decimate by 3 Output The first-stage filter operates on data that arrives at million samples per second (MSPS). Frequencies up to the Nyquist rate of MHz are discernible. The second-stage filter operates on data at MSPS and resolves up to MHz. The third-stage filter operates on data at MSPS and discerns up to 5.76 MHz. To study the effects of a multi-rate decimating filter, first examine the convolution function. The standard convolution function has the form: yn ( ) = gn ( ) xr ( n) r 4 Altera Corporation

5 Decimating the convolution function yields ym ( ) = g m ( n) xmm ( n) for decimation factor M using the random variables m and n. The samples from the original sample rate are captured under n and those from the decimated sample rate are under m. The following equation is a standard z transform definition: n Yz ( ) = ym ( )z m m Because the sample rate will be reduced, create terms such that y ( n) = yn ( ) ( n = 0, ± M, ± 2M, ± 3M, ) 0 otherwise It follows that Yz ( ) = y ( m)z m m Yz ( ) = H e M l j2π M M z j X e j2π M z M Evaluating this result on the unit circle leads to Ye ( jω ) which expands out to j ω 2πl M 1 j = ---- H e X e M l ω 2πl M Altera Corporation 5

6 Employing an ideal low-pass filter such that He jw ( ) = 2πF T 1 ω = πm 2 0 otherwise the high-order terms drop out, which leaves 1 j ω M j ω M ( ) ---- H e X e M Ye jω Most UMTS systems require at least 80 db rejection. This DDC reference design provides better than 80 db rejection from the entire filter chain. The stage 1 filter covers 0 Hz to MHz The stage 2 filter covers 0 Hz to MHz The stage 3 filter covers 0 Hz to 5.76 MHz The first filter is the only one that operates on frequencies greater than MHz. It rejects all frequencies between MHz and Nyquist by 80 db. The first and second filters operate on frequencies in the range of 5.76 to MHz and together they reject 80-dB. All three filters operate on frequencies from DC up to 5.76 MHz and reject better than 80 db outside this range. See Figures 4, 5, and 6. Figure 4. Filter Frequency Operation Third Stage Filter Second Stage Filter First Stage Filter (Nyquist) 6 Altera Corporation

7 To analyze the system, perform the following steps: 1. Perform a multi-rate convolution. 2. Combine the transfer functions for the first two stages for frequencies in the range of 5.76 MHz and MHz. Because convolution in the time domain is the same as multiplication in the frequency domain, you can multiply the transfer functions in these appropriate frequency ranges. 3. Combine all three filters, to examine the response from DC up to 5.76 MHz, which is performed also via multiplication in the frequency domain. Figure 5 shows the individual filter transfer functions. Figure 5. Individual Filter Responses The blue line indicates the first-stage filter; the red line indicates the second-stage filter; the green line indicates the third-stage filter. The resulting combined three-stage filter has a multi-rate convolutional transfer function (see Figure 6). Altera Corporation 7

8 Figure 6. 3-Stage Filter Transfer Function Implementation The DDC reference design is targeted and optimized for Altera Stratix devices. The design uses two Altera MegaCore functions. You can evaluate MegaCore functions using the OpenCore feature, which lets you quickly and easily verify the functionality of an IP function, and evaluate its size and speed before making a purchase decision. Additionally, these functions have the OpenCore Plus hardware evaluation feature, which allows you to generate time-limited programming files for prototyping and board-level verification. NCO The NCO was created using the Altera NCO Compiler MegaCore function. The NCO is completely programmable and has a phase dithering option. The NCO Compiler supports clock rates over 200 MHz. With the single-cycle, dual output option, the NCO can provide data rates up to 400 MSPS. The NCO Compiler allows you to trade off parameters to obtain a spurious free dynamic range (SFDR) greater than 110 db. The built-in spectral plotter quickly shows which parameters result in better spectral performance. The resource estimator allows you to estimate which elements of an FPGA will be consumed when generating the NCO. 8 Altera Corporation

9 The NCO design uses the NCO Compiler s optional phase modulation input, which generates both the sine and cosine waveforms. The NCO has a multiplier-based generation algorithm, and uses phase dithering. Table 1 shows the settings used in this design. Figure 7 shows an example wizard page. Table 1. NCO Compiler Settings Parameter Setting Generation Algorithm Multiplier Based Accumulator Precision 32 Angular Precision 16 Magnitude Precision 18 Implement Phase Dithering On Dither Level Set to the middle of the slider bar Phase Modulation Input On Frequency Modulation Input Off Outputs Single Output Target Device Family Stratix Multiplier-Based Architecture Use Dedicated Multipliers Clock Cycles per Output 1 Figure 7. NCO Compiler Parameters Page Altera Corporation 9

10 As reported by the Quartus II software, the NCO uses 8 9-bit DSP elements and 6 M4K memory blocks. The wizard estimates the Stratix device resource usage as shown in Figure 8. Figure 8. NCO Compiler Architecture Page f For more information, refer to the NCO Compiler MegaCore Function User Guide. Filter The DDC reference design employs a three-stage decimation filter (see Figure 3). Each of the three stages uses a filter created with the Altera Compiler MegaCore function. The Compiler wizard lets you generate floating-point filter coefficients, perform floating-point to fixed-point conversion, and generate a filter in hardware. Tables 2 through 4 show the parameters used in this design. 10 Altera Corporation

11 Table 2. First-Stage Filter Parameters Parameter Setting Sample Rate MHz single rate Filter Type Raised cosine, excess bandwodth = 22% Cut-Off Frequency 1.92 MHz (3.84 MSPS MHz) Window Type Blackman Number of Taps 27 taps Coefficient Scaling Type Auto Coefficient Bit Width 14 bits Input Bit Width 10 bits Output Resolution Full Precision MSB Bits Removed 0 MSB Operation Saturation LSB Bits Removed 0 LSB Operation Rounding Architecture Fixed Coefficient Fully Parallel Number of Channels 2 Pipeline Level 1 Data Storage Auto Coefficient Storage Logic Cells Simulation Models Generated Verilog HDL, VHDL, MATLAB Table 3. Second Stage Filter Parameters (Part 1 of 2) Parameter Setting Sample Rate MHz single rate Filter Type Low pass Cut-Off Frequency MHz Window Type Blackman Number of Taps 45 taps Coefficient Scaling Type Auto Coefficient Bit Width 16 bits Input Bit Width 10 bits Output Resolution Full Precision MSB Bits Removed 0 MSB Operation Saturation LSB Bits Removed 0 Altera Corporation 11

12 Table 3. Second Stage Filter Parameters (Part 2 of 2) Parameter Setting LSB Operation Rounding Architecture Fixed Coefficient Fully Parallel Number of Channels 4 Pipeline Level 1 Data Storage Auto Coefficient Storage Logic Cells Simulation Models Generated Verilog HDL, VHDL, MATLAB Table 4. Third Stage Filter Parameters Parameter Setting Sample Rate MHz Filter Type Low pass Cut-Off Frequency MHz Window Type Blackman Number of Taps 45 taps Coefficient Scaling Type Auto Coefficient Bit Width 16 bits Input Bit Width 10 bits Output Resolution Full Precision MSB Bits Removed 0 MSB Operation Saturation LSB Bits Removed 0 LSB Operation Rounding Architecture Fixed Coefficient Fully Parallel Number of Channels 16 Pipeline Level 1 Data Storage Auto Coefficient Storage Logic Cells Simulation Models Generated Verilog HDL, VHDL, MATLAB Figure 9 shows the wizard s coefficient analysis tool. 12 Altera Corporation

13 Figure 9. Compiler Coefficient Analysis Page You can pick from the available architectures to trade off area (i.e., device resources) and throughput. Additionally, the Compiler includes a resource estimator that allows you to see instantly how many resources are used for a particular filter architecture (see Figure 10). Altera Corporation 13

14 Figure 10. Compiler Architecture Page f For more information, refer to the Compiler MegaCore Function User Guide. Design Partitioning This reference design supports 8 DDC channels and is partitioned into digital mixers and filters. See Figure 11. The input sample rate is MHz. 14 Altera Corporation

15 Figure Channel DDC Design Partitioning Channel Channel Channel Channel Channel Channel Channel Channel Multiplier NCO Multiplier NCO Multiplier NCO Multiplier NCO Multiplier NCO Multiplier NCO Multiplier NCO Multiplier NCO Stage 1 Stage 1 Stage 1 Stage 1 Stage 1 Stage 1 Stage 1 Stage 1 Stage 2 Stage 2 Stage 2 Stage 2 Stage 3 Each digital mixer comprises an NCO and a multiplier. The NCO was created using a single compilation of the NCO Compiler MegaCore function with associated parameters and settings. The NCO must generate two distinct values (sine and cosine) for each channel, which requires the NCO to operate at MHz. Each DDC channel has a single NCO. The I/Q splitter and mixer subdesign requires 2 multiplications at MHz. Because Stratix multipliers are capable of speeds over 230 MHz, this design uses a single multiplier and time-shares it between the I and Q streams per DDC channel. See Figure 12. Figure 12. Time-Division Multiplexing Input Data MHz I Q NCO sin MHz cos MHz This implementation requires the NCO output to be in a time-shared format as well. The NCO Compiler includes a phase modulation input. Using this input and toggling it between 0 and 90 degrees generates the required sine and cosine functions without using a multiplexer. This implementation also causes the design to run faster. Altera Corporation 15

16 The Compiler MegaCore function can generate filters with speeds over 200 MHz. In this DDC design, each I and Q channel accepts data at integer factors of MHz. The first stage filters can operate near 200 MHz in a Stratix EP1S25-5 speed grade device or EP1S80-6 speed grade device. Because each I and Q channel requires MHz of throughput, the stage 1 filters are limited to 1 DDC channel. This single DDC channel contains a twochannel (I and Q) filter. Because the stage 1 filter decimates by a factor of 2, each stage 1 outputs half as much data as it receives. Therefore, a multi-channel stage 2 filter can accommodate outputs from two stage 1 filters. Similarly, because a stage 2 filter decimates by a factor of 4, a stage 3 filter can accommodate 4 stage 2 filters (or 8 stage 1 filters). Figure 11 on page 15 shows this design partitioning. The stage 1 filter accepts the data split in a time shared format as shown in Figure 13. Figure 13. Data Split in Time-Shared Format DDC Channel 0 ch1 I ch2 Q DDC Channel 1 ch1 I ch2 Q DDC Channel 9 ch1 I ch2 Q Finally, the design has the glue logic that cements the everything together. In this case, the design uses a flexible Stratix M4K memory to act as a combined FIFO buffer and multiplexer. The design writes into the memory in a wide port, and reads from it using a narrow port. By using address locations, the design does not have to keep track of time sharing across channels. Instead, it reorders the counters that drive the read and write address locations. 16 Altera Corporation

17 Each NCO uses two multipliers to generate a high-quality sinusoid, which leaves one additional multiplier for an overall gain element. Six Stratix DSP blocks implement the I/Q splitter and mixer functions. A single multiplier mixes the data signal (I/Q streams with the NCO). 1 The Quartus II software reports that the design uses 48 9-bit DSP elements. In hardware, this corresponds to multipliers. Design Resources The DDC design uses the resources shown in Table 5. Table 5. Resources Used Resource Usage LEs 22,000 M512 blocks 208 M4K blocks 12 M-RAM 2 DSP blocks 8 Input Signal Generation The input signal typically comes from an analog receiver connected to an analog-to-digital converter (ADC). The reference design comes with 2 stimulus generators (one for hardware and one for simulation), each consisting of a RAM and a counter. The supplied testbench connects the stimulus generator to all 8 channels. You can synthesize and instantiate the signal source in hardware for board verification. Additionally, you can take the contents of the RAM, take the Fourier transform of the data, and verify that it consists of modulated data. The utility directory contains a command-line C/C++ program, ddc_sig_gen_cmd_line.exe, to generate input data for one DDC channel in your choice of the following formats: QPSK 8 PSK 16 QAM 256 QAM Altera Corporation 17

18 To use the utility, type the following at a Command Prompt: ddc_sig_gen_cmd_line <bit rate> <number of bits> <modulation type> <oversampling factor> <pulse-shaping filter file> <carrier frequency> r where: <modulation type> is one of the following numbers: 0 for QPSK 1 for 16 QAM 2 for 64 QAM <number of bits> and <oversampling factor> are natural numbers. <bit rate> and <carrier frequency> are real, positive numbers. <pulse-shaping filter file> is a text file of coefficients in the format shown in Figure 14. You can generate the coefficients using MATLAB or any other filter design tool. 1 All numbers can be in scientific notation or floating-point format. Figure 14. Pulse-Shaping Filter File Format e For example: ddc_sig_gen_cmd_line coef_97_tap_64x2.txt e+007 r The program generates the following output files (see Figure 15): mod_file.txt Raw data used to generate the MIF. The file contains modulated, pseudo-random, pulse-shaped data. In Generate a Modulated Signal on page 22, you will view the modulated signal in a frequency display. It is an ASCII text file, of the same format as the pulse-shaping filter file (Figure 14). 18 Altera Corporation

19 sig_gen_mem.v Verilog HDL simulation vector file. In Simulate the Design in the ModelSim Software on page 24, you will use this file to simulate in the ModelSim software. sig_gen.mif Quartus II Memory Initialization File (.mif) for compilation. Figure 15. ddc_sig_gen_cmd_line.exe Output ddc_sig_gen_cmd_line.exe Modulated Data mod_file.txt sig_gen_mem.v ASCII-formatted numerical data with one number per line Verilog HDL-formatted numerical data Data Formatters sig_gen.mif Altera-formatted (MIF) numerical data The program displays parameters entered from the command line (see Figure 18 on page 22). The stimulus generator, sig_gen.v, is written Verilog HDL and infers a counter coupled to an instantiation of a preloaded RAM. You can synthesize this stimulus generator and download it into hardware. The RAM instance is loaded with the contents of the MIF, sig_gen.mif. Because you cannot use MIFs in the ModelSim software for simulation, the reference design includes a second Verilog HDL stimulus generator, sig_gen_mti.v, which creates a two dimensional array of registers that are preloaded with a Verilog HDL memory file. Figure 16 shows how the stimulus is generated for each channel for both hardware and software. Figure 16. Stimulus Generator Stimulus Generator Reset Clock Counter addr Preloaded RAM (Hardware) 2-Dimensional Array (Software) data Data Out (Input to DDC Design) C/C++ Program Generates the Memory Contents: sig_gen.mif for Hardware and sig_gen_mem.v for Software Altera Corporation 19

20 Simulation Verification The design includes a testbench that you can use to exercise the design. See Figure 17. You can instantiate up to 8 stimulus generators in the wrapper file. Figure 17. DDC Simulation Testbench Testbench Stimulus Generator Stimulus Generator Channel 0 Channel 1 DDC ASCII Text File Stimulus Generator Channel 7 The testbench uses the Verilog HDL file filewriter_iq.v to output the DDC output data to an ASCII text file. When you install the reference design, filewriter_iq.v prints the following data to a file for channel 0: All of the input data at every clock cycle For the output data, it prints 1 line every 2 clock cycles for the I/Q pair You can modify the filewriter_iq.v source code if you want to capture different data. You can instantiate filewriter_iq.v for as many channels as you want to observe. You can perform a Fourier transform on the output data files to analyze the baseband signal. Altera includes an FFT viewer application and a time domain plotting application in the utilities directory, one for frequency response and one for time response, that perform the Fourier analysis and display the signal graphically. 1 The FFT viewer application displays a maximum of 1,024 points. If the data file has more that 1,024, only the first 1,024 are displayed. 20 Altera Corporation

21 Design File List The DDC reference design includes Verilog HDL design files, files generated by the NCO Compiler and Compiler wizards, and a test bench. Table 6 lists the files you can modify (you should use the wizards to modify the wizard-generated files). Table 6. DDC Reference Design File List Module File Description Top-level top.v Top-level synthesizable module. Testbench filewriter_iq.v Verilog HDL file that outputs data to a text file. nco_setup.v Initializes NCO configuration. pll_clk_mti.v ModelSim simulation model of PLL block. sig_gen.v Stimulus generator. sig_gen_mem.v Input data for simulation. sig_gen_mti.v Stimulus generator for simulation. tb_top.v Top-level testbench file. top_wrap.v Top-level testbench wrapper file. NCO mix.v Mixer top-level file. ddc_mix_mul.v Mixer/multiplier generated by the lpm_mult wizard. ddc_nco.v NCO generated by the NCO Compiler wizard. Stage 1 Filter st1_plus_fir\st1_plus_fir.v Integrates the stage 1 filter, FIFO, and multiplexing circuitry. st1_fir.v Stage 1 filter generated by the Compiler wizard. Stage 2 Filter st2_plus_fir\st2_plus_fir.v Integrates the stage 2 filter, FIFO, and multiplexing circuitry. st2_fir.v Stage 2 filter generated by the Compiler wizard. st2_mem_mux.v Memory instance generated by the altsyncam wizard. Stage 3 Filter st3_plus_fir\st3_plus_fir.v Integrates the stage 3 filter, FIFO, and multiplexing circuitry. st3_fir.v Stage 3 filter generated by the Compiler wizard. st3_mem_mux.v Memory instance generated by the altsyncam wizard. Before You Begin These instructions assume that you have already installed the software provided with the DSP Development Kit, Stratix Edition onto your PC. Refer to the DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide for installation instructions. Additionally, you must have the following software installed on your PC: Quartus II software version 2.2 ModelSim PE or ModelSim SE software version 5.6 or higher Altera Corporation 21

22 1 This application note assumes that you have installed the software into the default locations. Design Walkthrough The following sections walk you through the following steps: 1. Generate a Modulated Signal 2. Simulate the Design in the ModelSim Software 3. Verify the ModelSim Output 4. Download the DDC Reference Design to the Stratix EP1S25 or EP1S80 DSP Development Board 5. Customize the DDC Design Generate a Modulated Signal The DDC brings a modulated signal to baseband. Altera supplies a C/C++ program that you can use to create a modulated signal. At a Command Prompt, run the batch file for the stimulus generator, ddc_sig_gen.bat (located in the DDC\Projects\Utilities directory), to create a modulated signal. See Figure 18. The stimulus generator outputs the files sig_gen.mif, mod_file.txt, and sig_gen_mem.v. 1 Refer to Input Signal Generation on page 17 for more information on this utility. Figure 18. Stimulus Generator Parameters 22 Altera Corporation

23 Verify the frequency characteristics of the stimulus by performing the following steps: 1. Launch the Altera Frequency Display window by executing Altera_Freq_disp.exe, which is located in the utilities folder, at a Command Prompt. 2. Click Load Data File. 3. Browse to DDC\Projects\Utilities directory, which contains the modulated signal in mod_file.txt. 4. Select mod_file.txt and click Open. 5. Type 92.16e6, which is the UMTS sample rate, in the Sample Rate box. 6. Select Hanning from the Window Type (for Data) list box to reduce the effects of side lobes within the FFT and observe the spectrum. See Figure The FFT is limited to 1,023 points. For this oversampling factor, you will not see a clean spectrum for 1,023 points: the signal viewer would need 65,536 or more points to provide a clean, spectral view. Nevertheless, the 1,023-point FFT provides a good estimate of the spectrum. Altera Corporation 23

24 Figure 19. Modulated Signal in the Frequency Display Note: (1) Your waveform may appear slightly different due to the high oversampling factor and the random bit stream. Simulate the Design in the ModelSim Software After you generated the modulated signal, you can view signals in the reference design and testbench in the ModelSim software by performing the following steps: 1. Open the top-level testbench file, top_wrap.v, which is located in the ddc\projects\rtl_source\testbench directory, in the ModelSim software. This file instantiates the device under test (DUT), the stimulus generator, and the response capture. The wrapper file contains the input signal generator and instantiates the Verilog HDL module filewriter_iq.v, which captures the data from interesting points in the reference design and outputs it as text files. Figure 20 shows the testbench hierarchy. 24 Altera Corporation

25 Figure 20. Testbench Hierarchy top_tb.v reset clock top_wrap.v Signal generators (sig_gen.v) NCO Setup (nco_setup.v) File Sinks (filewriter_iq.v) DDC Design (top.v) By default, top_wrap.v writes the outputs of the NCO and three filter stages to the files outfile_nco.txt, outfile_st1.txt, outfile_st2.txt, and outfile_st3.txt, respectively. 2. The testbench, top_wrap.v, contains a stimulus generator. If you did not install the reference design in the default location, change the parameter pointing to the Verilog HDL memory file, sig_gen_mem.v, to point to the correct location. For the EP1S25 DSP development board, use: defparam stim_data_file = "<installation directory> megacore/stratix_dsp_kit-v1.00/ Reference_Designs/ddc/Projects/RTL_Source/ test_bench/sig_gen_mem.v"; For the EP1S80 DSP development board, use: defparam stim_data_file = "<installation directory> megacore/stratix_dsp_pro_kit-v1.00/ Reference_Designs/ddc/Projects/RTL_Source/ test_bench/sig_gen_mem.v"; See Figure 21. Refer to Input Signal Generation on page 17 for information on sig_gen_mem.v. Altera Corporation 25

26 Figure 21. Instantiating filewriter_iq.v // Input Signal filewriter_iq InstFW (.clk(clk),.data(tb_out[11:0]),.mode(3 d0),.cntr(2 d0)); defparam InstFW.WIDTH=12; defparam InstFW.FILENAME="stimulus.txt"; // Time Division Multiplexed NCO signal filewriter_iq InstFW_NCO (.clk(dut.clk_200),.data(dut.u_mix_ch1.nco_mag),.mode(3 d0),.cntr(2 d1)); defparam InstFW_NCO.WIDTH=18; defparam InstFW_NCO.FILENAME="outfile_nco.txt"; // stage 1 filter output filewriter_iq InstFW_ST1_ (.clk(dut.clk_200),.data(dut.st1_fir_01_out),.mode(2 d2),.cntr(3 d1)); defparam InstFW_ST1_.WIDTH=12; defparam InstFW_ST1_.FILENAME="outfile_st1.txt"; defparam InstFW_ST1_.TDM_SEL = 1; // stage 2 filter output filewriter_iq InstFW_ST2_ (.clk(dut.clk_200),.data(dut.st2_fir_01_out),.mode(2 d2),.cntr(dut.ust2_01_fir.fast_addr)); defparam InstFW_ST2_.WIDTH=12; defparam InstFW_ST2_.TDM_SEL = 1; defparam InstFW_ST2_.FILENAME="outfile_st2.txt"; // stage 3 filter output filewriter_iq InstFW_ST3_ (.clk(dut.clk_200),.data(tdm_out_a),.mode(2 d2),.cntr(dut.ust3_01_fir.fast_cnt)); defparam InstFW_ST3_.WIDTH=12; defparam InstFW_ST3_.TDM_SEL = 5; defparam InstFW_ST3_.FILENAME="outfile_st3.txt"; 3. The output from the stimulus generator is connected to channel 0. Connect the output from the stimulus generator signal name to the desired DDC channel using the TDM_SEL parameter in the filewriter_iq.v file. The stimulus generator generates 16-bit numbers and its output is tb_out. 14 bits from the stimulus generator are already connected to the channel 1 input of the DDC. 4. Change your working directory to <installation directory>\megacore\<stratix_dsp_kit-v[version] or Stratix_DSP_pro_kit-v[version]>\Reference_Designs\ddc\Projects\ ModelSim\tcl. 5. Execute the run.tcl script by typing do run.tcl r at the Command Prompt. This Tcl script loads the design files, sets up a display window, and runs a simulation for a 32 µs. See Figure Altera Corporation

27 Figure 22. Simulation in ModelSim Software 6. Quit the ModelSim simulation with the command quit sim r to close the relevant output files. Verify the ModelSim Output In this section, you will use two Altera-provided FFT viewer applications to verify the ModelSim output. The viewers use the output files, outfile_nco.txt and outfile_st2.txt, which were specified in top_wrap.v. To verify the output, perform the following steps: 1. Browse to DDC\Projects\ModelSim\tcl directory and open the output files in a text editor to view the output. 2. Remove any Xs or Zs and save the files. 3. Launch the Altera_Plotter window by double-clicking the file Altera_Plotter.exe, which is located in the utilities folder, in the Windows Explorer. 4. Choose Open (File menu). Altera Corporation 27

28 5. Browse to the ModelSim working directory, <installation directory>\<stratix_dsp_kit-v[version] or Stratix_DSP_pro_kitv[version]>\Reference_Designs\ddc\ Projects\ModelSim\tcl. 6. Select the NCO output file, outfile_nco.txt, and click Open. The NCO output is loaded (see Figure 23). Figure 23. NCO Time Plot View 7. Choose Dual Time Plot (View menu) to display 2 signals, sine and cosine, and to open the Time Plot Specifications dialog box. 8. Make the settings shown in Figure 24 and click OK. 28 Altera Corporation

29 Figure 24. Time Plot Specifications With these settings, you can see that the NCO produces sine and cosine waveforms in a TDM format. See Figure 25. Figure 25. NCO in TDM Format 9. Launch the Altera Frequency Display window by double-clicking Altera_Freq_Disp.exe, which is located in the utilities folder, in the Windows Explorer. 10. Click Load Data File. Altera Corporation 29

30 11. Browse to your ModelSim working directory, <installation directory>\<stratix_dsp_kit-v1.0.0 or Stratix_DSP_pro_kitv1.0.0>\Reference_Designs\ddc\ Projects\ModelSim\tcl. 12. Select the stage 2 filter output file, outfile_st2.txt, and click Open. 13. Type in the Sample Rate box. 14. Apply a Hanning window for better rejection. Only 1,023 sample points are available for analysis, and more samples are needed to provide an accurate spectral picture (typically, 65,535-point FFTs are used in spectral plots). Nevertheless, 1,023 points provides a good approximation of the spectrum. See Figure 26. Figure 26. Stage 2 Filter Plot 30 Altera Corporation

31 Download the DDC Reference Design to the Stratix EP1S25 or EP1S80 DSP Development Board You can download the DDC reference design to the Stratix EP1S25 or EP1S80 DSP development board for hardware verification. To view selected nodes from within the DDC on the Stratix EP1S25 or EP1S80 DSP development board, you use the Signal Tap II logic analyzer. The reference design includes a separate Quartus II project that works with the development board. The design includes the following: A PLL converts the 80-MHz clock to MHz using a 144/125 clock multiplication/division factor. A short stimulus generator that produces 256 input data points. NCO setup circuitry to set the phase increment value. SignalTap II circuitry. To exercise the DDC on the Stratix EP1S25 or EP1S80 DSP development board, you need to: Configure the Stratix EP1S25 or EP1S80 device on the development board with the Altera-provided SRAM Object File top_qns_wrap.sof from within the SignalTap II logic analyzer in the Quartus II software. Run the Signal Tap II logic analyzer to view selected nodes from within the DDC in the Stratix device. f Refer to the DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide for instructions on connecting cables. To configure the Stratix EP1S25 or EP1S80 device on the development board with the Altera-provided file top_qns_wrap.sof perform the following steps: 1. Connect the power supply provided with the kit to the board. 2. Attach the ByteBlaster II cable to the LPT1 parallel port of your PC and connect it to the board. 3. Run the Quartus II software. 4. Choose Open Project (File menu). 5. Browse to the c:\megacore\<stratix_dsp_kit-v1.0.0 or Stratix_DSP_pro_kit-v1.0.0>\ reference_designs\ddc\projects\quartus\work_brd directory. 6. Select the top_qns_wrap.quartus file and click Open. Altera Corporation 31

32 7. Open the Signal Tap II user interface in the Quartus II software by choosing Signal Tap II Logic Analyzer (Tools menu). The SignalTap II logic analyzer opens the stp_dsk_brd.stp file. 1 Ensure that the hardware setup is appropriately set to use the ByteBlaster II cable on the correct communications port. 8. Click Program/Configure icon. To run the SignalTap II logic analyzer, perform the following steps: 1. Click the Autorun icon. 2. Press the pushbutton switch SW1 on the Stratix EP1S25 or EP1S80 DSP development board to reset the design and trigger SignalTap read-back. The SignalTap II logic analyzer displays an internal node within the NCO. These steps demonstrate how to use the SignalTap II logic analyzer, you can add additional SgnalTap II probes at different points within the design. Customize the DDC Design Altera provides the source code for the DDC design, which you can use as a starting point for your own design. You can modify the RTL source code and use the Compiler and NCO Compiler wizards to make changes to the design. Additionally, you can modify the testbench, top_wrap.v, to view different points in the RTL design. 1 The design does not use the OpenCore Plus hardware evaluation version of the cores, therefore, you need to license them before you generate programming files. To customize this design in the Quartus II software, perform the following steps: 1. Run the Quartus II software. 2. Create a working directory. 3. Use the batch file, qts_cpy_dsk_brd.bat, which is provided with the reference design in the Quartus directory, to copy the revelant design files into your working directory. 32 Altera Corporation

33 4. Open the Quartus project (<filename>.quartus) in your working directory. 5. Make design modifications as desired. 6. Choose Start Compilation (Processing menu) to compile the new design. 7. When compilation completes, you can view the compilation results to verify the timing requirements are met and to verify the size and speed of the design. The top-level testbench, top_wrap.v, uses the Verilog HDL module filewriter_iq.v to capture the data from interesting points in the reference design and output it as text files. Refer back to Figure 20 on page 25 for details. To view different points, instantiate the Verilog HDL file filewriter_iq.v and make the following settings: 1. Connect the clock and data signals. Verilog HDL allows you to obtain buried signals in the hierarchy using the convention module_instance_name.sub_instance_name.wire_or_reg_name. 2. Select the desired mode for writing files. Figure 27 shows the source code for the modes. 0 Prints all the data at every clock cycle. 1 Prints all the data for a particular channel, one line per clock. 2 Prints 1 line every 2 clocks for an I/Q pair for a particular channel (tab separated). Altera Corporation 33

34 Figure 27. filewriter_iq.v Modes clk) begin // print all output if (mode == 0) $fwrite(fid, "%d\n", data_int); end // print all I and Q for relevant channel if (mode == 1) begin if (cntr == 1) $fwrite(fid, "%d\n", data_int); end // print all I,Q pairs for relevant channel if (mode == 2) begin if (cntr == 1) begin cnt = cnt + 1 b1; if (cnt == 2) cnt = 0; if (cnt == 0) $fwrite(fid, "%d\t", data_int); if (cnt == 1) $fwrite(fid, "%d\n", data_int); end end 3. Create a counter signal to isolate a TDM channel. 4. Connect the counter signal to the cntr input port of the filewriter_iq.v instantiation. 5. Change the output file name for every instantiation using a defparam statement. All filenames must be unique. 1 By default, the output files are connected to the stimulus, the time-division multiplexed NCO, and all three filter stages. See Figure 21 on page Change the data bit width using a defparam statement. 7. If you are isolating a particular TDM channel, override the TDM_SEL parameter with a defparam statement. 34 Altera Corporation

35 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera products are protected under numerous U.S. and foreign patents, maskwork rights, copyrights and other intellectual property laws. 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com This reference design file, and your use thereof, is subject to and governed by the terms and conditions of the applicable Altera Reference Design License Agreement (found at By using this reference design file, you indicate your acceptance of such terms and conditions between you and Altera Corporation. In the event that you do not agree with such terms and conditions, you may not use the reference design file and please promptly destroy any copies you have made. This reference design file being provided on an "as-is" basis and as an accommodation and therefore all warranties, representations or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, noninfringement, or fitness for a particular purpose, are specifically disclaimed. By making this reference design file available, Altera expressly does not recommend, suggest or require that this reference design file be used in combination with any other product not provided by Altera. 35 Altera Corporation