Single phase hybrid asymmetrical multilevel inverter

Transcription

1 New Asymmetrical Hybrid Multilevel Voltage Inverter Domingo Ruiz-Caballero *, Luis Martinez*, Reynaldo Ramos A. *, Samir A. Mussa ** * PONTIFICIA UNIVRSIDAD CATÓLICA D VALPARAÍSO School of lectrical ngineering I Power lectronic Laboratory LP Av. Brasil 147, P.O. BOX 4059, Valparaíso, CHIL. Tel: domingo.ruiz@ucv.cl ** FDRAL UNIVRSITY OF SANTA CATARINA Department of lectrical ngineering/power lectronics Institute INP P. O. BOX Florianópolis SC BRAZIL Tel: mail: samir@inep.ufsc.br Keywords <<Multilevel converters>>, <<Voltage Source Inverters (VSI)>>, Hybrid inverters, Asymmetrical multilevel converters. Abstract This article presents the study and implementation of a new asymmetric hybrid voltage inverter, for high voltage applications. The proposed inverter employs two types of modulation in low and high frequency (sinusoidal PWM). Simulations and experiment results are provided showing the validity of the analyses. These were obtained using a low-voltage single-phase prototype that demonstrated its operation. Introduction The multilevel inverters have become popular in high power and high voltage applications. The work shown in [1] was the first to submit a topology known as asymmetric hybrid multilevel inverters. The inverter belongs to the family of hybrids [5] which means it is composed of switches of different technologies (MOSFT and GTOS, for instance) and strategies for several modulation (PWM Pulse single, sinusoidal). The inverter is also known as asymmetric, since it has power supplies of different values. In this study is a circuit configuration with binary sources of voltages, is described similar to the inverter studied in [1, 3, 4, 7], but proposed as an alternative. Single phase hybrid asymmetrical multilevel inverter In [5, 8] is proposing a new topology that derives from a DC-DC three level buck converter. The proposal differs from this cell by the peculiarity of having a binary distribution on the voltages sources. In Fig. 1 shows that distribution topological while the Fig. 1 shows the possible voltage levels that can be obtained at the voltage output of the cell. In general the voltage produced by the inverter is governed by equation (1) where `n` is the amount of sources in each of the TC (three-level cell), with value increasing exponentially (,, 4,...). m n1 1 (1) In Fig., a change in the circuit allows the reversal of the voltage produced in TC. To obtain a voltage alternating connects an inverter type H-bridge between points A and B. Using a strategy of differentiation approach, you get a signal in the output of alternating between points a and b.

2 3 v ab (t), Fig 1. Five-level cell (TC), waveform of the voltage between a and b. 0 t The switches,,, and produce a waveform unipolar as shown in Fig. 1, while the switches SH1, SH, SH3 and SH4 generate an alternate output voltage for each cycle of operation of switches to. Fig. shows the output signal to the inverter, resulting in effectively seven voltage levels. Fig. (c) shows the three-phase extent of the proposed circuit. The advantage is that the switches,,, and can operate at higher frequencies can be MOSFTs or IGBTs will withstand, for,, and for, voltage level, while SH1, SH, SH3 and SH4 often operate on the main frequency, so the switches are slow as the GTO or IGCTs must withstand whole DC-link Voltage. v A B (t) 3, SH SH3 t 0 - SH1 SH Fig.. Single-phase asymmetrical hybrid multilevel inverter, Output voltage waveform., Three-phase hybrid asymmetrical multilevel inverter If three single phase outputs are connected, so that they feed a three-phase load in star connection, then the outcome would be a three-phase symmetrical hybrid multilevel inverter, as shown in Fig. 3. The modulator is composed of three sinusoidal reference signals shifted by 10º from each other, compared to three carrier signals in phase disposition (PD). The common point of the inverters is called o, whereas the common point of the load star connection will be named N. The connection points between each single-phase inverter and the load will be called U, V and W. Modulation strategy In general the inverters are modulated by pulse width (PWM), or the pulses are generated comparison of a signal modulator with the carrier. Often for converters with m voltage levels and m-1 carriers, the carriers are defined with the same frequency (fc) and amplitude (Ac). The amplitude of the modulator is defined as (Am) and with a frequency (fm). The index of modulation, given by equation (), relates to initially the magnitude of the modulator with respect to a carrier (m i ) and finally respect to three carriers in Phase Disposition (m a ). A m mi A m Am a m 1 Ac C ()

3 There are situations where the voltages levels in the load are not kept. The equation (3) sets a minimum rate of modulation which can be obtained in an inverter of seven levels. O a Da b Db c Dc S7a D S7a a Da S5a DS5a S 7b D S7b S b Db S5b DS5b S7c DS7c c Dc S5c D S5c S8a DS8a a Da S6a DS6a S8b DS8b S 3b Db S6b DS6b S8c DS8c c Dc S6c DS6c a Da b Db c Dc Inverter leg U V W N (c) Fig. 3. Three-phase asymmetrical hybrid multilevel inverter. Load- phase voltage and (c) line-toline voltage waveforms in steady state. m 3 ma (3) min m 1 In this inverter a limit of modulation is given at 66.6%, below you lose a voltage level. Another point is at 33.3% which is lost the second voltage level, see Fig. 4. There is another concept that is the index of frequency often given by the equation (4) and which is defined as the ratio of the frequency of the carrier with respect to the modulator. This index is always greater than one. m f c f (4) fm The modulations strategy for driving the switches is based on the sinusoidal PWM modulation with phase disposition (PD) [] [6]. This technique requires (m-1) carriers to get (m) voltages levels in the output of the cell. ach of these carriers is in phase, but displaced vertically with a value equal to its maximum. The circuit used in the generation of pulses of commands of switches is shown in Fig. 4. In Fig. 5, shows the different waveforms of the output voltage of three different rates of modulation. VP1 3 VP VP3 1 VM Fig. 4. Command circuit for the switches for modulation PWMS.

4 (c) Fig. 5. Signal of control and output voltage of the inverter for an index of modulation of 0.85, 0.5 and (c) 0.3. By the way as modulated is, without phase-shifting of the carriers, the order of the harmonics generated by the converter in the output voltage will depend, such as occur with the two levels sinusoidal PWM, of the rate of frequency (m f ), i.e., if m f is even number, it will generate even and odd harmonics, and if m f is odd, will generate only odd harmonics. Spectral analysis of the load voltages In order to analytically define the load voltages spectra and their THD, this section shows the derivation of the expressions for, both, single-phase and three-phase converters. For the analysis was assumed that the carriers are delayed 10 degrees with each other. However can be observed that the mathematical outcomes obtained are a good approximation of reality, simulation and experimental results are provided showing the validity of the analyses. A. Single-Phase Load Voltage Analysis The load voltage for the single-phase multilevel converter is given by, v ab sin 1 ti ns ti ( t) mi sin( 1 t) Jn, n mi (5) n n sin 1 ti ns i Where Jv represents the Bessel function of v order. Being this equation a good approximation for the output voltage. Table I: Amplitude of the load voltage harmonic components Harmonic Amplitude Frequency Fundamental A 1 A1 m i 1 Components A n,v n =,4,6... Jn, n m i n v n 1 s t

5 When watching the equation (5) it is possible to see that the harmonic components exist in sidebands ( 1 ) around multiple of the switching frequency ( s ). Fig. 6 is a plot of the previous equation normalized with respect to. The peak amplitude of the harmonic components of the inverter output voltage and their harmonic frequencies are exposed in table 1 and are graphically shown as a function of the modulation index m i in Fig.6. The harmonics components are obtained from h=n. m f ±. 0.0 Modulation Index.5 An,v/ Harmonics Amplitude A A 1,1 A 1, A1,3 A, ti mi Fig. 6. Single-Phase Output voltage of the inverter for mf=3. Graph obtained from eq. (4), taking account until n=30 and v=31, i.e. h=991. Harmonic components amplitude of the voltage V ab : A 1 = fundamental component, A n,v = frequency harmonic v1 ns ; n =, 4, 6...; v = 1, 3, 5,...It can be seen that A 1,1 represents the harmonics h=31 and 33, being these the lower order. B. Three-Phase Load Voltage Analysis With: And, Moreover; 1 P sen v1tnst P vun t mi sen1t Jvn mi 3 n1 v, impar 3n N sen v1t nstn 0.3 P cos vn cos vn s en vn s en vn (7) N cos vn cos vn sen vn s en vn (8) tg P 1 v n v n sen vn sen vn cos cos (9) (6) And, N tg 1 v n v n sen v n sen v n cos cos (10)

6 The maximum amplitude of the harmonic components of the load-phase voltage and their frequencies are given in table and plotted in Fig. 7. Fig. 7 is a plot of the previous equation normalized with respect to. Table II: Amplitude of the load-phase voltage harmonic components Harmonic Amplitude Frequency Fundamental A 1 1 A1 m i 3 Componentes, A n,v, B 3n n,v n = 1,,3..., 3n v = 1,3, A J n m M n v v i P B J n m M n v v i N v n 1 s v n 1 s An,v/ Bn,v/ Harmonics Amplitude A A 1,1 B 1,3 B 1,1 A,3 Fig. 7. Load-Phase Output voltage of the inverter for mf=3. Graph obtained from eq. (6), taking account until n=100 and v=41, i.e. h=341. Amplitude of the harmonic components of the load-phase voltage of inverter: A 1 = fundamental component, A n,v = v1 ns, B n,v = v1 ns. It can be seen that A 11 represents the harmonic 33 and B 13 the harmonic mi On the other hand, the expression that defines line-to-line voltage is given by (11). With: With NP sen v1tnstp vuv t 3mi sen1t Jvn mi 6 n1 v, impar n NN sen v1tnstn N 1cos vn P N 1cos vn P N tg 1 v n cot N tg 1 5 (11) (1) (13) v n cot (14)

7 3 In Fig. 8 is a plot of the previous equation normalized with respect to. The peak amplitude of the harmonic components of the line-to-line voltage and their frequencies are tabulated in Table III and are displayed in function of the modulation index m i in Fig. 8. Table III: Amplitude of the line-to-line voltage harmonic components Harmonic Amplitude Frequency Fundamental A 1 A1 3 mi Componentes A n,v, B n,v A, J n = 1,,3... n n m N v = 1,3,5... B, J n n m N 1 n v v i P n v v i N v n 1 s v n 1 s (15) An,v/ Bn,v/ A 1 B 1,3 A 1,1 A 1,3 B 1,1 A,1 Fig.8. Line-to-line voltage of the inverter for mf=3. Graph obtained from eq. (11), taking account until n=100 and v=41, i.e. h=341. Amplitude of the harmonic components line-to-line voltage inverter: A 1 = fundamental component, A n,v = harmonics at the frequency v1 ns, B n,v = v1 ns n =, 4, 6...; v = 1, 3, 5,... A 11 represents the harmonic 33 and B 11 the harmonic 31. ; Also were obtained the expressions of the harmonic distortion of voltages. The equation 16 shows the THDv of line-to-line voltage and the equation 17 shown the THDv of phase-load voltage, both are shown by Figure 9 and. Jnv, n,, mi N Pv, n N Nv, n n (16) THDvUV 100 n v 3 mi

8 Jnv, n,, mi M Pv, n M Nv, n 3n (17) THDvUN 100 n v 1 mi 3 THDv UN THDv UV mi mi Fig.9. THDv to load-phase voltage and at THDv to Line-to-line voltage of the inverter. Simulation results for single-phase asymmetrical hybrid inverter In this section the results obtained by digital simulations for the single phase and three-phase circuit with PD-PWM modulation. Consider all the components ideals, with the following designs specifications: 1 0 red kv P 54 kw f 50 Hz cos 0.9 m 0.85 V 1.75 kv R 1 L mh f 4 khz L L port To check the operation of asymmetric hybrid multilevel inverter is performed simulations with the proposed modulation. In Fig. 10 it is possible to observe that the single-phase voltage has seven levels, -1.5 kv, -1 kv, -0.5 kv, 0, 0.5 kv, 1 kv and 1.5 kv. The magnitude of fundamental component is 1.7 kv with a distortion of a 19.46%. Regarding the harmonic spectrum can be observed in Fig. 10 higher order of the components appear at 4 khz and only in side-bands on multiple frequencies of the carrier frequency. Also it presents simulation results from the three-phase 7-level converter. The simulation specifications are the same as given before except that the total output power is multiplied by three and the carrier frequency was 1.6 khz. In Fig. 11 shows the load voltages obtained in the simulation. The phase voltage v UN at the load presents fifteen levels as seen in Fig. 11, while the line voltage v UV presents eleven levels. From the simulation were obtained that line-to-line voltage has a THDv of 0.% and load-phase voltage has a THDv of 0.8% taking a maximum of 100 harmonics. i Fig. 10. Output voltage of the single-phase inverter, harmonic spectrum of the output voltage.

9 Fig. 11. Phase-load voltage, and Line-to-Line voltage of the three-phase inverter. It is possible to appreciate that the voltage stress are different among the switches. We can see that the fast switches; and must withstand of reverse voltage, and must withstand, while on the other hand, the H-bridge switches (SH 1, SH, SH 3 and SH 4 ) must block a higher voltage level of 3. However, these switches operate only in one cycle of the output voltage. Thus, they operate at low frequency commutating at zero voltage. From the viewpoint of the current sharing; is that the RMS current levels in the switches are function of angle of load. For resistive loads the sharing of current becomes asymmetrical and the switches, and, carry a large percentage of the total current, this distribution tends to be uniform for inductive loads. For the H-bridge, besides, the distribution will be function of the angle of load, but is not as asymmetrical as in the case of fast switches. From the viewpoint of the conduction loss it is clear that will be who will have a higher level of losses, since it must withstand /3 of the DC-link voltage and moreover this leads a large amount of current. xperimental results To validate the operation of the inverter, an experimental prototype of the single-phase multilevel inverter was built with the following specifications: =100V and = 50V, 300 W of output power, operating at 1500 Hz frequency switching and the fundamental frequency of 50 Hz. The switches used to cell CT were IRF840A MOSFT and the bridge IRGP30B60KD-. The modulation strategy is based on the Phase Disposition (PD) PWM and was implemented using the TM0F81 DSP. In Fig. 1 shows the waveforms of the voltage and current output (top) obtained a resistive load. Also at the bottom shows the waveforms of the command pulse for the fast switches. In Fig. 1 is shown output voltage and output current, to single-phase inverter with inductive load.

10 Fig. 1. a) Top; output voltage and output current to resistive load and bottom; command pulses for fast switches. b) Output voltage and output current, to single-phase inverter with inductive load. Conclusions This paper presented the asymmetrical hybrid multilevel inverter circuit based on the three-level cell (TC) and the associated modulation technique. The circuits are characterized by fast switches in the inverter cell and slow switches in H-bridge. The switches that make up the cell (CT) support different voltages, depending with which the sources of voltages are connected and can be or. The voltage blocked by the H-bridge switches equals the entire DC-link voltage (3). The voltages produced in the output of the inverter are seven levels with a low harmonic distortion. In the case of PWM modulation that generates high-frequency components in bands around the side of the index of multiple frequency, which is convenient if the goal is to eliminate through a filter output. One should take into account that with the strategy of modulation used, you should choose a frequency of carriers that do not manage even components in the output signal of the inverter to avoid asymmetry in the signal. Also was realized the theoretical analysis to waveforms of, line-to-line and phase-load, three-phase output voltages and obtained its THD. This topology has the advantage over the symmetric of a greater amount of output levels for the same amount of switches used. But has the disadvantage of having greater efforts of voltage in a pair of high frequencies switches. References [1] M. D. Manjrekar, P. Steimer, T. A. Lipo, Hybrid Multilevel Power Conversion System: A Competitive Solution for High Power Applications, Publisher Item Identifier S x/98, I [] G Carrara, S. Gardella, M. Marchenosi, R. Salutari, G. Sciutto, A new multilevel PWM method: A Theoretical Analysis Power lectronics, I Transactions on, Vol 7, July 199, pp [3] R. Lund, M.D. Manjrekar, P. Steimer, T. A. Lipo, Control Strategies for a Hybrid Seven-Level Inverter, P [4] M. D. Manjrekar, T. A. Lipo A Hybrid Multilevel Inverter Topology for Drive Applications. Publisher Item Identifier S /98, I-APC [5] R. Ramos A., Márcio Ortmann, Samir A. Mussa and D. Ruiz-Caballero, New Symmetrical Hybrid Multilevel DC-AC Converter Presented in PSC 008 Rhodes - Greece. [6] M. Calais, L. J. Borle, V. G. Agelidis, Analysis of Multicarrier PWM Methods for a Single-Phase Five Level Inverter, PSC Vol 3, pp , 001. [7] J. Rodríguez, J.L. Lai F. Z. Peng, Multilevel Inverters: A Survey of Topologies, Controls and Applications, I transactions on Industrial lectronics, Vol 49, N 4,pp August 00. [8] D. Ruiz-Caballero and R. R. Astudillo, Celda inversora multinivel y familia de inversores multiniveles híbridos para aplicaciones de alta tensión y alta potencia, Patent Chilean; patent request nr , 006.