CHAPTER 5 Z-SOURCE MULTILEVEL INVERTER FOR UPS APPLICATIONS

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1 90 CHAPTER 5 Z-SOURCE MULTILEVEL INVERTER FOR UPS APPLICATIONS 5.1 INTRODUCTION Multilevel Inverter (MLI) has a unique structure that allows reaching high voltage and power levels without the use of transformers. They are specially suited for applications which need low THD. Multilevel inverter is a power electronic device built to synthesize a desired AC voltage from several levels of DC voltages. In this research it is found that multilevel inverter exhibits good performance when it is used in uninterruptible power supplies. The attractive features of multilevel inverter can be summarized as follows (Nima et al 2012, Mariusz et al 2010). It not only can generate the output voltage with very low distortion, but also can reduce the dv/dt stresses and therefore reduces Electromagnetic Compatibility (EMC) problems. It draws input current with low distortion. It can operate at both fundamental switching frequency and high switching frequency Pulse Width Modulation (PWM). It should be noted that lower switching frequency usually means lower switching loss and higher efficiency.

2 91 These properties make multilevel inverter very attractive to the industry. Nowadays researchers all over the world are making great efforts to improve the performance of multilevel converters and the different optimization algorithms are developed in order to reduce THD balance the DC capacitor voltage and reduce the ripples in load current. This research work is focused on the development of the Z- Source multilevel inverter and the control strategies are also discussed. The new MLI topology based UPS is proposed and its functions are analyzed. 5.2 MULTILEVEL INVERTERS Diode Clamped Multilevel Inverter Diode Clamped Multilevel Inverter (DCMLI) typically consists of (n-1) capacitors on the DC bus and produces m levels on the phase voltage. Figure 5.1 shows one leg of a five level DCMI. The numbering order of the switches iss a1, S a2, S a3, S a4, S' a1, S' a2, S' a3and S' a4. The DC bus consists of four capacitors C 1, C 2, C3 and C 4. For a DC bus voltage V dc, the voltage across each capacitor is V 4 dc and each device stress is limited to one capacitor voltage level V 4 dc through clamping diodes (Jing Zhao et al 2011). An n-level inverter leg requires (n-1) capacitors, 2(n-1) switching devices and (n-1) (n-2) clamping diodes. Adam et al (2008) introduced a new operational mode for diode clamped multilevel inverters which avoid the imbalance problem of the DC link capacitors for multilevel inverters and reduces the DC link capacitance.

3 92 Figure 5.1 Basic Structure of Diode Clamped Multilevel Inverter Flying Capacitor Multilevel Inverter Flying Capacitor Multilevel Inverter (FCMLI) requires a large number of capacitors to clamp the device (switch) voltage to one capacitor voltage level which is shown in Figure 5.2. An n-level inverter requires a total of (n-1)(n-2)/2 clamping capacitors per phase leg in addition to (n-1) main DC bus capacitors. The size of the voltage increment between two consecutive legs of the clamping capacitors defines the size of voltage steps in the output waveform (Rodriguez et al 2002). Perhaps the main and most important difference with the DCMLI topology is that the FCMLI has a modular structure and can be more easily extended to achieve more voltage levels and higher power ratings. Shukla et al (2008) focused on the development of multilevel hysteresis current regulation strategies which have been applied to a five level FCMLI. A time based approach for controlling the capacitor voltages is presented and it achieves appreciable voltage spectrum under wide range of

4 93 load power factor conditions. The voltage levels and the arrangements of the flying capacitors in the FCMLI structures assures that the voltage stress across each main device is same and is equal to V dc /(n-1) for n-level inverter. The flying capacitor MLI has the following limitations. S a1 S b1 V 5 + S a2 S b2 Sb3 C b3 C 1 AC Ls S a3 S a4 C a1 C a2 C a3 C a3 S b4 C b1 C b2 C b3 V 4 C 2 V 3 C 3 S a1 S a2 S a3 Ca2 S B1 C S b2 a3 S b3 C b2 C b3 V 2 C 4 S a4 S b4 V 1 - Figure 5.2 Basic Structure of Flying Capacitor Multilevel Inverter Control is complicated in FCMLI to track the voltage levels for all the capacitors. Also, pre-charging all the capacitors to the same voltage level and startup are complex. Switching utilization and efficiency in FCMLI are poor for real power transmission. The large number of capacitors in FCMLI is more expensive and bulkier than clamping diodes in DCMLI. Packaging is also more difficult in inverters with high number of levels.

5 Cascaded Multilevel Inverter Cascaded Multilevel Inverters (CMLI) are formed by the series connection of two or more single-phase H-bridge inverters. Liao et al (2008) have designed multilevel converters which gained popularity in high power applications due to their low switch leg voltage stress and modularity. CMLI introduces the idea of using separate DC sources to produce an AC voltage waveform. Each H-bridge inverter is connected to its own DC source V dc. By cascading the AC outputs of each H-bridge inverter, an AC voltage waveform is produced (Brendan et al 2003 and Mariusz et al 2010). Figure 5.3 provides an illustration of a single phase CMLI using three DC sources. Figure 5.3 Basic Structure of Cascaded H-Bridge Multilevel Inverter To achieve a 3-level waveform, a single full bridge inverter is employed. Three distinct DC sources (S=3, where S is the number of DC sources) can produce a maximum of (L=7) distinct levels in the output phase voltage of the multilevel inverter. Generally, a cascaded H-bridge multilevel inverter can produce a maximum of (2s+1) distinct level (Minai and Tariq 2011). Fang et al (2007) had put forth a novel method to eliminate the specified lower frequency harmonics in CMLI (Hossein et al 2011). By closing the appropriate switches, each H-bridge inverter can produce three

6 95 different voltages: +V dc, 0 and -V dc. As mentioned earlier, each H-bridge inverter produces an AC voltage V i, where i stands for one particular H- bridge inverter. Figure 5.3 contains three such H-bridges, one for each DC source. Therefore, to obtain the total AC voltage produced by MLI, these three distinct AC voltages are added together (Javad et al 2011). The smallest number of voltage levels for a MLI using CMLI with system DC sources is three. Table 5.1 Comparison of Component Requirements of Three Types of MLI Converter Type Diode clamped Flying capacitors Cascaded inverter Main switching devices 2(n-1) 2(n-1) 2(n-1) Main diodes 2(n-1) 2(n-1) 2(n-1) Clamping diodes (n-1)(n-2) 0 0 DC bus capacitors (n-1) (n-1) (n-1)/2 Balancing capacitors 0 (n-1)(n-2)/ LIMITATIONS OF MULTILEVEL INVERTER MLI requires more number of power semiconductor switches. Although lower voltage rated switches can be utilized in a MLI, each switch requires a related gate drive circuit. This may cause the overall system to be more expensive and complex. The output side voltage level is equal to supply voltage and hence boosting of input voltage is not possible.

7 Z-SOURCE MULTILEVEL INVERTER To overcome the limitations of traditional multilevel inverter, in this section z-source multilevel inverter is proposed for UPS applications. It consists of ZS network and traditional MLI topology. ZS-MLI consists of active state and shoot through state. By properly adjusting the shoot through time period of pulses in ZSMLI, the voltage can buck or boost the input DC voltage (Banaei et al 2012). Also the proper selection of firing pulses in the ZSMLI can limit the THD in the output voltage. Figure5.10 shows the basic structure of proposed ZSMLI based UPS system. Figure 5.4 Per Phase Circuit Diagram of Z-Source Cascaded Multilevel Inverter

8 Z-SOURCE MULTILEVEL INVERTER BASED UPS SYSTEM The proposed UPS system consists of single phase rectifier, battery, multicarrier PWM generation, Z-Source cascaded multilevel inverter and a filter unit. The input stage is an AC-to-DC converter, which rectifies the input AC voltage and creates the DC bus voltage while maintaining sinusoidal input current at a high input power factor. A DC to DC buck-boost converter stage implements the battery charger. The battery charger stage steps down the high DC bus voltage to allow a smaller battery to be charged. A DC to DC boost converter raises the battery voltage up to the bus voltage when the system is operating in battery backup mode. Since seven level output is required, three H-bridges are used. LC filter is added to eliminate higher order harmonics and to provide sinusoidal waveform to the load. Z-Source inverter, unlike traditional inverters can utilize shoot through states to boost the input dc voltage of inverter switches when both switches in the same phase leg. Z-Source inverters as compared to the traditional inverters are less costly, more reliable, less complex and more efficient. In addition to cascaded inverter advantages, proposed topology employs Z-Source inverter advantages such as shoot through capability and ability of voltage boosting. The output voltage of the proposed inverter can be controlled using modulation index and shoot through state. Figure 5.8 shows the complex circuit diagram of ZSMLI based UPS system.

9 98 Figure 5.5 Z-Source Multilevel Inverter based UPS System Development of MLI Peng (2003) employed a unique impedance network to couple the converter main circuit to the power source, thus providing unique features that cannot be obtained in the traditional voltage-source and current-source converters where a capacitor and an inductor are used respectively. Das et al (2009) achieved the AC output voltage control of the Z-Source inverter using space vector modulation. The AC voltage from ZSI can be controlled theoretically to any value. Space vector modulation (SVM) is widely used for variable frequency drive applications (Loh et al 2005) because of its advantages like good DC utilization and less harmonic distortion in the output waveform. In order to use SVM for ZSI, conventional space vector control strategy has to

10 99 be changed to distribute the shoot through states into the zero vectors without compromising the active space vector. Muntean et al (2008) proposed a closed loop modified carrier based PWM modulation technique for a z-source inverter, in order to maintain a desired average DC voltage value after the boost section. Gao et al (2009) have designed a five level z-source diode clamped inverter with two intermediate z-source networks connected between the DC input sources and rear-end inverter circuitry. By partially shorting the Z-source networks, new operating states are introduced with voltage buck boost energy conversion ability and five level phase voltage switching. After analyzing various options, the authors commented that the five level Z-Source inverter implemented using the minimum of two impedance networks is the highest extended variant with satisfactory waveform quality that can be constructed using the diode clamped topology. For the Z-Source two port network, it is implemented using a split inductor and two shunt capacitors connected in an X-shaped structure, which when added to the inverter, allows switches from any phase leg to turn ON simultaneously with diode naturally reverse biased. This shooting through of the inverter does not result in huge current flow because of the limiting action introduced by the Z-Source split inductor and therefore will not cause any damage to the semiconductor switches. In addition to its protective feature, full shooting through of the inverter has already been proven in (Peng 2003) to allow the inverter to gain its voltage boosting feature in addition to its usual voltage buck ability.

11 100 ZSI utilizes impedance network between the DC source and inverter circuitry to achieve boost operation. ZSI, unlike traditional inverters can utilize shoot through states to boost the input DC voltage of inverter switches when both switches in the same phase leg are on (shen et al 2007). ZSI with respect to traditional inverters are lower costs, reliable, lower complexity and higher efficiency (Das et al 2008). In addition to CMI advantages, proposed topology employs ZSI advantages such as shoot through capability and ability of voltage boosting. The output voltage of proposed inverter can be controlled using modulation index and shoot through state. Figure 5.4 shows the proposed z-source multilevel inverter. The proposed topology consists of a series of single phase H-bridge inverter units, impedance networks and DC voltage sources. It is supplied from several DC sources, which may be obtained from batteries, fuel cells, solar cells or ultra-capacitors. Each H-bridge inverter can generate three different voltage outputs +V in, 0, -V in. The number of output voltage levels in the suggested topology is 2n+1 where n is the number of impedances or DC voltage sources. As compared to CMI, the proposed topology has an extra switching state; the shoot through state. During the shoot through state, the output voltages of Z networks are zero. Each H-bridge is turned in to shoot through state when the output voltage level is traditional zero therefore some or all of the zero states are changed to shoot through state. Table 5.2 indicates the values of V 0 for states of switches.

12 101 Table 5.2 Switching Scheme for ZSMLI Voltage Levels Output Levels ON switches Level 2 (non shoot-through) 2V in S13,S14,S21, S23 Level 1 (non shoot-through) V in S11,S13,S21, S23 Level 1 (shoot-through) V in S11,S12,S13,S14,S21, S23 Level 1 (non shoot-through) V in S13,S14,S21, S23 Level 1 (shoot-through) V in S13,S 14,S21,S 22,S23, S24 Level 0 (Zero state) 0 S11,S13,S21, S23 Level 0 (shoot-through) 0 S11,S12,S13,S14,S21, S23 Level 0 (shoot-through) 0 S11,S13,S21,S22,S23, S24 Level -1(non shoot-through) -V in S11,S13,S23, S24 Level -1(shoot-through) -V in S11,S 12,S13,S14,S23, S24 Level -1(non shoot-through) -V in S11,S12,S21, S23 Level -1(shoot-through) -V in S11,S12,S21,S22,S23, S24 Level -2(non shoot-through) -2V in S11,S12,S23, S PWM CONTROL SCHEMES FOR MULTILEVEL INVERTER There are many control techniques used in MLI and the most popular being carrier based and Space Vector Modulation (SVM). Several multi carrier techniques have been developed to reduce the distortion in MLI, based on classical Sinusoidal Pulse Width Modulation (SPWM) with

13 102 triangular carriers. The multilevel PWM techniques developed thus have been extension of two level PWM methods, the multiple levels in a cascaded inverter offer extra degrees of freedom and greater possibilities in terms of device utilization, state redundancies and effective switching frequency which has been reported by Govindaraju and Baskaran (2011). In multi carrier PWM, the amplitude modulation index M and the frequency ratio M f are defined as a M = a A m (5.1) M-1 A c M = f f c (5.2) f m In this technique, as carriers are in phase across all the bands, significant harmonic energy is concentrated at the carrier frequency. Multi carrier PWM methods can be categorized into two groups: Carrier Disposition methods (CD), where the reference waveform is sampled through a number of carrier waveforms displaced by continuous increments of the reference waveform amplitude and phase shifted (PS) PWM methods, where multiple carriers are phase shifted accordingly. The carrier disposition method comprises Phase Opposition Disposition (POD), Phase Disposition (PD) and Alternative Phase Opposition Disposition (APOD) (Seyezhai et al 2008) Phase Disposition Modulation McGrath and Holmes (2002) proposed the multi carrier phase disposition modulation technique. It has to be noted that PD strategy is now

14 103 well accepted as achieving the lowest line-to-line harmonic voltage distortion (MCgrath 2002). For MLI, it is generally accepted that PD gives rise to the lowest harmonic distortion (Mingyao et al 2007). In this method carriers are same in frequency, amplitude and phase. The reference waveform has peak to-peak amplitude A M, a frequency f m and its zero is centered in the middle of the carrier set. The reference is continuously compared with each of the carrier signals. If the reference is greater than a carrier signal, then the active device corresponding to that carrier is switched on; and if the reference is less than a carrier signal, then the active device corresponding to that carrier is switched off (Seyezhai et al 2008). Figure 5.6 Phase Disposition Modulation Figure 5.6 shows the carrier and reference arrangement in phase disposition technique. In this strategy, the most significant harmonic appears around the carrier frequency. However, this component does not appear in the line-to-line Voltages. This technique guarantees only odd harmonics for odd values of the frequency modulation depth (Diorge et al 2010) Phase Opposition Disposition Modulation Figure 5.7 shows the Phase Opposition Disposition (POD) where the carriers above the reference zero point are out of phase with those below the zero point by In this scheme, every pair of switches has a carrier

15 104 signal which has a phase change to the other. In general, a multilevel inverter with m voltage levels requires (m-1) triangular carriers (Tolbert et al 2000).The modulating signal is usually a sinusoidal wave with adjustable amplitude and frequency (Govindaraju and Baskaran 2011). The gate signals are generated by comparing the modulating signal with the carrier signals. Figure 5.7 Phase Opposition Disposition Modulation Alternate Phase Opposition Disposition Modulation Alternate Phase Opposition Disposition (APOD) where each carrier is phase shifted by 1800 from its adjacent carriers is shown in Figure 5.8. Figure 5.8 Alternate Phase Opposition Disposition Modulation

16 Phase Shifted Carrier Modulation The principle of PSC-PWM is to retain sinusoidal reference waveforms for the two phase legs of each FBI that are phase shifted by 180 and then phase shift the carriers of each bridge to achieve additional harmonic sideband cancellation around the even carrier multiple groups. The required carriers, all with the same amplitude and frequency, depend on the number of levels: in a converter with n-level, (n-1)/2 carriers are necessary. As the name suggests, the carriers have to be displaced, shifting their phases Space Vector Modulation Space Vector Modulation (SVM) is a digital modulating technique. SVM scheme gives a more fundamental voltage and better harmonic performance compared to the SPWM schemes. The maximum peak of the fundamental component in the output voltage obtained with SVM is 15% greater than with the sine-triangle modulation. But the conventional SVM scheme requires sector identification and look-up tables to determine the timings for various switching vectors of the inverter, in all the sectors. This makes the implementation of the SVM scheme quite complicated the over modulation range, extending up to six-step operation (Dae-Wook Kang et al 2003). Wenxi Yao suggested that these techniques are harmonically equivalent, with the best spectral performance being achieved when the nearest three space vector states are selected with the middle two vectors centered in each half carrier switching interval. This strategy is known as Carrier Based Space Vector Modulation (CBSVM) which is derived from the addition of a common offset voltage to the three-phase references. This will center the active space-vectors in the switching period and hence match the

17 106 carrier modulation to get optimized space vector modulation (Saad and Mohamad 2011). The offset voltage V ' for multilevel operation can be calculated as: off V off max (V, V, V ) a b c 2 min (V, V, V ) a b c (5.3) V k ' (V k V off V dc ) mod 2 V ( dc N 1 ), k a, b, c (5.4) V off ' V dc N 1 max (V ', V ', V ' ) a b c 2 min (V ', V ', V ' ) a b c (5.5) where V is 1 p.u. dc The modified phase references are obtained by adding V ' to the reference waveform V, V or off a b V. c V and off 5.7 CLOSED LOOP CONTROL SYSTEM The technique of output feedback control is incorporated to determine the switching actions of the inverters. The measured voltages are the inputs to the error correction unit which gives signals to the control unit as shown in Figure 5.9. Modulation unit generates PWM pulses to get the desired output voltage and its performance is similar to switching algorithm. The inverter modulates a DC bus voltage into a cycle-by-cycle average output voltage. Current mode control is used for this inverter. Current mode control is a two loop control system that simplifies the design of the outer voltage control loop and improves UPS performance in many ways,

18 107 including better dynamics and a feed forward characteristic that could be used to compensate DC bus ripple. As shown in Figure 5.9, the instantaneous inverter output voltage and the load current are sensed and conditioned by the respective voltage and current sense amplifiers. The sensed voltage signals are then compared to an reference voltage. The difference between these two voltages is fed into the PI regulator (PI 1 ) which is based on GPI 1 =K P +K I /S (K P =2, K I =1884.9). The output of this compensator is the reference current command for the inner current loop. This reference is compared with the current feedback and then the difference is passed to the second PI regulator, PI 2, based on GPI 1 =K P +K I /S (K P =1, K I =314.15). The output of this current regulator is the command voltage which is used to determine the duty cycle of the PWM gating signals. Figure 5.9 Control Structure for ZSMLI based UPS Operation

19 STEADY STATE STABILITY ANALYSIS A single phase Z-Source multilevel inverter is shown in Figure Vout is the inverter bridge output voltage; Vc is the voltage of Z-Source, i L Z-source inductor current and i 0 is the load current and R is the equivalent damping resistance. Figure 5.10 Circuit Diagram for Cascaded Z-Source Multilevel Inverter

20 109 The differential equation model can be derived as follows: dvc 1 1 = i L - i dt C C 0 (5.6) di L 1 1 R = V out - V c - i dt L L L L (5.7) The inverter transfer function with no load can be derived from equation (5.6) and (5.7) as follows: V s 2 G s = out = n 0 V s s 2 +2 s+ 2 in n n 1 = LCs 2 +RCs+1 (5.8) where n is the undamped natural frequency, = 1 LC n ; is the damping ratio, = R 2 C L. The closed loop transfer function with PI controller is given by K s+k p i G(s)= (5.9) LCs 3 +rcs 2 +(1+K p )s+k i Figure 5.11 shows the Bode plot for closed loop transfer function. It shows that closed loop system is stable and it has strong robustness. When compared with FWI and FWZSI, the ZSMLI has better stability in the closed loop for shoot through periods of 0.1 to 0.35.Figure 5.11 gives the stability of ZSMLI for a shoot through duty ratio of 0.35.

21 Frequency (rad/sec) Figure 5.11 Bode Plot for Closed Loop Transfer Function 5.9 RESULTS AND DISCUSSION The simulation model of Z-Source multilevel inverter incorporated in the proposed UPS system is developed using MATLAB/SIMULINK and results were developed for various values of input and output conditions. The output voltage and current waveforms with spectral analysis are analyzed for different loading conditions. The phase disposition modulation is used for the Z-Source multilevel inverter For a shoot through duty ratio of 0.35,the PWM switching pattern for nine levels is shown in Figure 5.12.The Figure includes the pulses for shoot through time as well as active time.

22 Figure 5.12 Gate Pulse Pattern for ZSMLI Figure 5.13 shows the per phase voltage of Z-Source multilevel inverter. The corresponding THD spectrum of output voltage as shown in Figure From the Figure 5.13 it is observed that the voltage contains only higher order harmonics in the order of 11, 13 and 17. Hence lower value of filter inductance is enough to filter that harmonics

23 112 (a) (b) Figure 5.13 Output Phase Voltage Waveform of ZSMLI (a) Phase Voltage and (b) THD Spectra Figure 5.14(a) shows the load current waveform of ZSMLI for a load of 1kW and the corresponding input current harmonics shown in Figure 5.14(b).As evident from the figures, the input source current harmonics is very minimum and the spectra shows only the fundamental. The total distortion is around 1.69% which will be constant for all loading conditions.

24 113 (a) (b) Figure 5.14 Simulated Waveform of ZSMLI (a) load Current (b) THD Spectra From this analysis, it can be noticed that the voltage waveforms for the multilevel modulation are not symmetrical regardless of whether frequency ratio (m f ) is odd or even. While there is an increase in m f, m a remains constant, more switching will appear in the waveforms. Since the fundamental frequency, f m is always constant, when m f increases, f c also increases. As a result, there will be more intersections or comparisons between the modulating and the carrier signals. The z-source capacitor voltage and inductor current waveforms are shown in Figure 5.15 (a) and (b).

25 114 (a) (b) Figure 5.15 (a) Z-Source Capacitor Voltage Waveform and (b) Z-Source Inductor Current Waveform The performance of Z-Source cascaded multilevel inverter for varying load condition is given in the Table 5.3. The ZSMLI is loaded from0.25kw to 1.5kW of non linear loads and the corresponding load current, terminal voltage THD and input current THD are measured. The % THD of ZSMLI is around 20% less than the FWZSI and 37% less than the conventional PWM inverter. The % current THD is very minimum and is around 1.15 % for all loading conditions. Figures 5.16(a) and (b) show the variation of voltage THD and current THD against various load conditions. Figure 5.16 shows the comparative chart of the harmonics against various load conditions. Figure 5.17 shows the experimental waveforms of ZSMLI. Figure 5.17(a) and (b) consists of phase voltages, capacitor voltage and dc link voltages for D0=0.1 and 0.2. The values of ripples in dc link voltage and phase voltages increases with increase in shoot through time period. Figure 5.17(c) shows the zoomed waveform of ZSMLI phase voltage.

26 115 Experimental waveforms of nine level multilevel inverter very well coincide with simulation results. From the Figures5.17 (a),(b) and(c) it is observed that the terminal voltage of ZSMLI is boosted with increase in shoot through pulses of PWM signals. From the waveforms the simulation result well coincide with experimental results. Table 5.3 Analysis of ZSMLI with Harmonic Filter for Different Load Conditions Input Voltage(V) Load (kw) Output Votage(V) Output Current(A) Voltage THD% Current THD% Load (KW) (a) Load(KW) (b) Figure 5.16 Simulated Results of ZSMLI with Load (a) Voltage THD and (b) Current THD

27 116 (a) (b) (c) Figure 5.17 Experimental Results of Nine Level MLI for a Shoot Through Period of (a) 0.1, (b) 0.2 and (c) 0.3

28 117 Figure 5.18 shows the output voltage and input current Total Harmonic Distortion of ZSMLI for a RL load of 0.5 kw. The output voltage harmonics is 5 % and 17 % less than FWZSI and conventional PWM inverter. The input current harmonics is 27 % and 32 % less than FWZSI and conventional PWM inverter. (a) (b) Figure 5.18 Experimental THD Spectra of ZSMLI (a) Output Voltage and (b) Input Current

29 SUMMARY The basic principle and operating modes of ZSMLI for UPS applications have been discussed. The control of ZSMLI is done using Modified Space Vector PWM (MSVPWM) scheme. The mathematical relation between output voltage, modulation index and boost factor has been derived. The transfer function model of the ZSMLI has been derived in order to check the stability of the system. The ZSMLI can buck or boost the input voltage by proper control of shoot through pulses. Because of lower THD in ZSMLI the neutral current is 20% lesser in magnitude than the MLI when the rectifier load is connected across it. The input current Total Harmonic Distortion (THD) is 30 % less than the PWM inverter for RL load applications. Similarly the output voltage THD is 19 % less than the PWM inverter. Moreover the output voltage and current waveforms remain undistorted.

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