DIGITAL TO ANALOG CONVERTER (DAC)

Transcription

1 PH315 DIGITAL TO ANALOG CONVETE (DAC) Portland State University 1. PUPOSE: Construction of digitaltoanalogue converters using different techniques, namely the scaled resistors into summing junction, and the 2 ladder. Figure. 1 Digital vs analog signal processing. 2. CONVETING DIGITAL TO ANALOG SIGNALS: It is often necessary to convert analog signal to an accurate digital number, and vice versa. For example, in applications where a microprocessor is controlling an experiment, the analogue signal from a sensor needs to be converted into digital form so it can be communicated to the microprocessor. After the processing takes place in the digital form, the from the microcontroller needs to be converted back to the analogue form to communicate with the analogue world. In this lab session we will consider the case of digital to analogue conversion (DAC). The DAC techniques presented here are not aimed at developing skills in converter designs. Instead, they aim at presenting the advantages and disadvantages of each method. In most cases, when embarked in an electronic project, one rather buys commercially available chips instead of building a converter from scratch. An understanding of DAC methods, however, will guide you in selecting the more suitable one for the project at hand. 2.1 Scaled resistors into summing junction Implement the circuit shown in Fig. 2. a) Notice that the circuit has an input count from 0 (when all the inputs are OFF) to 15 (when all the inputs are HIGH.) b) Verify that the circuit generates an voltage from zero to (almost) 5 Volts. The exact value is estimated below. EXACT CALCULATION b1) Verify that the total maximum current through the gain resistor is given by,

2 I f V (1 10k ) 3 2 b2) Verify that the circuit generates an voltage from zero to, 4 5 k 1 (1/ 2) Vmax 10 k 1 (1/ 2) V max V = 5 Volt k, 1% k, 2% 40k, 4% i 3 i 2 i 1 5k, 1% + V CC LM358AP V CC k, 8% i 0 Digital input Fig. 2 Fourbit DAC. Example of a binary input: We need an experimental implementation that lect the corresponding weight of the binary digits, Calibration voltage: Contribution to the total voltage from bit, V j,out = 5V j 5k, j= 0, 1, 2, 3

3 2 3 5 V 10k, 1% V 5 V 20k, 2% 40k, 4% i 3 i 2 i 1 5k, 1% + VCC LM358AP VCC V 80k, 8% i 0 Theory Experimental implementation Experimental implementation of the binary input: c) GENEALIZATION (for nbits DAC) In Fig. 2, consider adding input bits on the left side (i.e. adding resistors whose values increase by a factor of 2) until n inputs are completed. Show that the maximum input count is 2 n 1 (when all the n bits set to 1.) Show analytically that the circuit generates voltages from zero to n 2 1 V max [ ] n 2 d) EQUIED PECISION of the ESITOS d1) Show that for a given input of resistance in the DAC circuit, the contribution (only V from that input) to the voltage is Vout 5k. Hence, a smaller resistance produces larger currents (V/) and has a larger contribution to the voltage. This explains why in Fig. 2: the input with smaller resistance (10 k in this case) is assigned to represent the mostsignificantbit (); and the input with higher resistance (80 k is assigned to represent the leastsignificantbit ().

4 d2) If the value of the resistor were to have an uncertainty show that the corresponding uncertainty in the out voltage V out is given by, Vout Vout Thus, for a given required precision in the voltage, a higher value of can afford a larger uncertainty (lower precision). Hence, the resistance at the input (lower resistance ) requires smaller uncertainty (i. e. higher precision) in the resistance value. e) Make a table of the digital inputs in one column and the corresponding voltage in another column, and verify if the obtained experimental values correspond with the predicted ones ladder The scaled resistor technique becomes awkward for higher bits DAC. (A 12bit converter would need a 2000:1 range of resistor values) with corresponding precision in the input. This becomes impractical. The 2 ladder, shown in Fig. 3 offers an elegant alternative. Only two resistor values are needed. Although the resistors must be precisely matched, the actual value of the resistors is not critical. V EF = 5 Volts 2i i i / 2 i / 4 i / = 50k v in 50 k Fig. 2 Fourbit DAC. V CC + LM358AP V CC a) Check if suggested distribution of currents along the network of resistance is correct. b) Calculate and verify experimentally that the contribution to the voltage from the is 2.5 V.

5 Verify that the contribution to the voltage from the other inputs decrease by a factor of 2, from bit to the next. c) Make a table of the digital inputs in one column and the corresponding voltage in another column, and verify if the obtained experimental values correspond with the predicted ones. d) Calculate (show all your steps) and verify experimentally that the maximum magnitude of the voltage is V 15/16.