SPC564A70B4, SPC564A70L7

Transcription

1 S564A70B4, S564A70L7 32-bit ower Architecture based MU for automotive powertrain applications Datasheet preliminary data Features 150 MHz e200z4 ower Architecture core Variable length instruction encoding (VLE) Superscalar architecture with 2 execution units Up to 2 integer or floating point instructions per cycle Up to 4 multiply and accumulate operations per cycle Memory organization 2 MB on-chip flash memory with E and read-while-write (RWW) 128 KB on-chip SRAM with standby functionality (32 KB) and E 8 KB instruction cache (with line locking), configurable as 2- or 4-way KB etu code and data RAM 4 4 crossbar switch (XBAR) 24-entry MMU Fail Safe rotection 16-entry Memory rotection Unit (MU) R unit with 3 submodules Junction temperature sensor Interrupt onfigurable interrupt controller (INT) with non-maskable interrupt (NMI) 64-channel edma Serial channels 3 esi modules 3 DSI modules (2 of which support downstream Micro Second hannel [MS]) 3 FlexAN modules with 64 message buffers each BA324 (23 mm x 23 mm) LQF176 (24 mm x 24 mm) 1 FlexRay module (V2.1) up to Mbit/s w/dual or single channel, 128 message objects, E 1 emis (24 unified channels) 1 etu2 (second generation etu) 32 standard channels 1 reaction module (6 channels with 3 outputs per channel) 2 enhanced queued analog-to-digital converters (eqads) Forty 12-bit input channels 688 ns minimum conversion time n-chip AN/SI Bootstrap loader with Boot Assist Module (BAM) Nexus: lass 3+ for core; lass 1 for etu JTA (5-pin) Development Trigger Semaphore (DTS) lock generation n-chip 4 40 MHz main oscillator n-chip FMLL (frequency-modulated phase-locked loop) Up to 112 general purpose lines ower reduction modes: slow, stop, and standby Flexible supply scheme 5 V single supply with external ballast Multiple external supply: 5 V, 3.3 V, and 1.2 V Designed for LQF176, LBA208, BA324 Table 1. Device summary art number Memory Flash size ackage LQF176 ackage LBA208 ackage BA324 2MB S564A70L7 - S564A70B4 September 23 Doc ID Rev 4 1/133 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1

2 ontents S564A70B4, S564A70L7 ontents 1 Introduction Document overview Description Device feature summary Block diagram Feature details e200z4 core rossbar switch (XBAR) Enhanced direct memory access (edma) Interrupt controller (INT) Memory protection unit (MU) Frequency-modulated phase-locked loop (FMLL) System integration unit (SIU) Flash memory Static random access memory (SRAM) Boot assist module (BAM) Enhanced modular input/output system (emis) Second generation enhanced time processing unit (etu2) Reaction module (REAM) Enhanced queued analog-to-digital converter (eqad) Deserial serial peripheral interface (DSI) Enhanced serial communications interface (esi) ontroller area network (FlexAN) FlexRay System timers Software watchdog timer (SWT) yclic redundancy check (R) module Error correction status module (ESM) eripheral bridge (BRIDE) alibration bus interface ower management controller (M) Nexus port controller (N) JTA controller (JTA) Development trigger semaphore (DTS) /133 Doc ID Rev 4

3 S564A70B4, S564A70L7 ontents 2 inout and signal description LQF176 pinout LBA208 ballmap BA324 ballmap Signal summary Signal details Electrical characteristics arameter classification Maximum ratings Thermal characteristics eneral notes for specifications at maximum junction temperature EMI (electromagnetic interference) characteristics Electrostatic discharge (ESD) characteristics ower management control (M) and power on reset (R) electrical specifications Regulator example Recommended power transistors ower up/down sequencing D electrical specifications pad current specifications pad V R33 current specifications LVDS pad specifications scillator and LLMRFM electrical characteristics Temperature sensor electrical characteristics eqad electrical characteristics onfiguring SRAM wait states latform flash controller electrical characteristics Flash memory electrical characteristics A specifications ad A specifications A timing Reset and configuration pin timing IEEE interface timing Nexus timing Doc ID Rev 4 3/133

4 ontents S564A70B4, S564A70L alibration bus interface timing External interrupt timing (IRQ pin) etu timing emis timing DSI timing eqad SSI timing FlexAN system clock source ackages EAK ackage mechanical data LQF BA BA rdering information Revision history /133 Doc ID Rev 4

5 S564A70B4, S564A70L7 List of tables List of tables Table 1. Device summary Table 2. S564A70 device feature summary Table 3. S564A70 series block summary Table 4. S564A70 signal properties Table 5. ad types Table 6. Signal details Table 7. ower/ground segmentation Table 8. arameter classifications Table 9. Absolute maximum ratings Table. Thermal characteristics for 176-pin LQF Table 11. Thermal characteristics for 208-pin LBA Table 12. Thermal characteristics for 324-pin BA Table 13. EMI testing specifications Table 14. ESD ratings Table 15. M operating conditions and external regulators supply voltage Table 16. M electrical characteristics Table 17. S564A70 External network specification Table 18. Transistor recommended operating characteristics Table 19. ower sequence pin states Fast type pads Table 20. ower sequence pin states Medium, slow and multi-voltage type pads Table 21. D electrical specifications Table 22. pad average I DDE specifications Table 23. pad V R33 average I DDE specifications Table 24. V R33 pad average D current Table 25. DSI LVDS pad specification Table 26. LLMRFM electrical specifications Table 27. Temperature sensor electrical characteristics Table 28. eqad conversion specifications (operating) Table 29. eqad single ended conversion specifications (operating) Table 30. eqad differential ended conversion specifications (operating) Table 31. utoff frequency for additional SRAM wait state Table 32. A, RWS, WWS settings vs. frequency of operation Table 33. Flash program and erase specifications Table 34. Flash EERM module life Table 35. ad A specifications (V DDE = 4.75 V) Table 36. ad A specifications (V DDE = 3.0 V) Table 37. Reset and configuration pin timing Table 38. JTA pin A electrical characteristics Table 39. Nexus debug port timing Table 40. Nexus debug port operating frequency Table 41. alibration bus interface maximum operating frequency Table 42. alibration bus operation timing Table 43. External interrupt timing Table 44. etu timing Table 45. emis timing Table 46. DSI channel frequency support Table 47. DSI timing Table 48. eqad SSI timing characteristics (pads at 3.3 V or at 5.0 V) Doc ID Rev 4 5/133

6 List of tables S564A70B4, S564A70L7 Table 49. FlexAN engine system clock divider threshold Table 50. FlexAN engine system clock divider Table 51. LQF176 mechanical data Table 52. LBA208 mechanical data Table 53. BA324 package mechanical data Table 54. Document revision history /133 Doc ID Rev 4

7 S564A70B4, S564A70L7 List of figures List of figures Figure 1. S564A70 series block diagram Figure pin LQF pinout (top view) Figure pin LBA package ballmap (viewed from above) Figure pin BA package ballmap (northwest, viewed from above) Figure pin BA package ballmap (southwest, viewed from above) Figure pin BA package ballmap (northeast, viewed from above) Figure pin BA package ballmap (southeast, viewed from above) Figure 8. ore voltage regulator controller external components preferred configuration Figure 9. ad output delay Fast pads Figure. ad output delay Slew rate controlled fast, medium, and slow pads Figure 11. Reset and configuration pin timing Figure 12. JTA test clock input timing Figure 13. JTA test access port timing Figure 14. JTA JM timing Figure 15. JTA boundary scan timing Figure 16. Nexus output timing Figure 17. Nexus event trigger and test clock timings Figure 18. Nexus TDI, TMS, TD timing Figure 19. LKUT timing Figure 20. Synchronous output timing Figure 21. Synchronous input timing Figure 22. ALE signal timing Figure 23. External interrupt timing Figure 24. DSI classic SI timing (master, HA = 0) Figure 25. DSI classic SI timing (master, HA = 1) Figure 26. DSI classic SI timing (slave, HA = 0) Figure 27. DSI classic SI timing (slave, HA = 1) Figure 28. DSI modified transfer format timing (master, HA = 0) Figure 29. DSI modified transfer format timing (master, HA = 1) Figure 30. DSI modified transfer format timing (slave, HA = 0) Figure 31. DSI modified transfer format timing (slave, HA = 1) Figure 32. DSI S strobe (SS) timing Figure 33. eqad SSI timing Figure 34. LQF176 package mechanical drawing Figure 35. LBA208 package mechanical drawing Figure 36. BA324 package mechanical drawing Figure 37. roduct code structure Doc ID Rev 4 7/133

8 Introduction S564A70B4, S564A70L7 1 Introduction 1.1 Document overview This document provides electrical specifications, pin assignments, and package diagrams for the S564A70 series of microcontroller units (MUs). It also describes the device features and highlights important electrical and physical characteristics. For functional characteristics, refer to the device reference manual. 1.2 Description This microcontroller is a 32-bit system-on-chip (So) device intended for use in mid-range engine control and automotive transmission control applications. It is compatible with devices in ST s S56xx family and offers performance and capability above that of the S563M devices. The microcontroller s e200z4 host processor core is built on the ower Architecture technology and designed specifically for embedded applications. In addition to the ower Architecture technology, this core supports instructions for digital signal processing (DS). The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory. For development, the device includes a calibration bus that is accessible only when using the STMicroelectronics calibration tool. 1.3 Device feature summary Table 2 summarizes the S564A70 features and compares them to those of the S564A80. Table 2. S564A70 device feature summary Feature S564A70 S564A80 rocess 90 nm ore e200z4 SIMD Yes VLE Yes ache 8 KB instruction Non-Maskable Interrupt (NMI) NMI and ritical Interrupt MMU 24-entry MU 16-entry rossbar switch ore performance MHz Windowing software watchdog Yes 8/133 Doc ID Rev 4

9 S564A70B4, S564A70L7 Introduction Table 2. S564A70 device feature summary (continued) Feature S564A70 S564A80 ore Nexus lass 3+ SRAM 128 KB 192 KB Flash 2 MB 4 MB Flash fetch accelerator bit bit External bus None 16-bit (incl. 32-bit muxed) alibration bus DMA DMA Nexus 16-bit (incl. 32-bit muxed) 64 channels Serial 3 esi_a esi_b esi_ None Yes (MS uplink) Yes (MS uplink) AN 3 AN_A AN_B AN_ Yes 64 message buffers 64 message buffers 64 message buffers SI 3 FlexRay Micro Second hannel (MS) bus downlink DSI_A DSI_B DSI_ DSI_D System timers emis etu ode memory Data memory Yes No Yes (with LVDS) Yes (with LVDS) Yes Yes 5 IT channels 4 STM channels 1 Software Watchdog 24 channels 32-channel etu2 14 KB 3 KB Reaction module 6 channels Interrupt controller 485 channels (1) AD 40 channels Doc ID Rev 4 9/133

10 Introduction S564A70B4, S564A70L7 Table 2. S564A70 device feature summary (continued) Feature S564A70 S564A80 R FMLL AD_0 AD_1 Temperature sensor Variable gain amplifier Decimation filter 2 Sensor diagnostics VR Yes Supplies 5 V, 3.3 V (2) Low-power modes ackages interrupt vectors are reserved V single supply only for LQF inout compatible with STMicroelectronics S563M64 devices 4. For ST calibration tool only LQF176 (3) BA pin S (4) Yes Yes Yes Yes Yes Yes Yes Stop mode Slow mode LQF176 (3) BA324 Known ood Die (KD) 496-pin S (4) 1.4 Block diagram Figure 1 shows a top-level block diagram of the S564A70 series. /133 Doc ID Rev 4

11 S564A70B4, S564A70L7 Introduction Interrupt ontroller 64-channel edma ower Architecture e200z4 SE VLE MMU 8 KB I-cache Debug JTA Nexus IEEE-IST FlexRay S0 2 MB Flash M4 M0 M1 M6 S2 128 KB SRAM rossbar Switch MU S7 Analog LL RS XS S1 Voltage Regulator Standby Regulator with Switch ESM alibration Bus Interface Bridge emis 24 hannel 3 KB Data RAM 14 KB ode RAM etu2 32 hannel REAM 6 ch DTS FMLL R BAM M STM IT SWT SIU FlexAN x 3 esi x 3 DSI x 3 ADi DE x2 Temp Sens AD AD VA AMux LEEND AD Analog to Digital onverter ADi AD interface AMux Analog Multiplexer BAM Boot Assist Module R yclic Redundancy heck unit DE Decimation Filter DTS Development Trigger Semaphore DSI Deserial/Serial eripheral Interface ESM Error orrection Status Module edma Enhanced Direct Memory Access emis Enhanced Modular Input utput System esi Enhanced Serial ommunications Interface etu2 Second gen. Enhanced Time rocessing Unit FlexAN ontroller Area Network FMLL Frequency-Modulated hase-locked Loop JTA IEEE Test ontroller MMU Memory Management Unit MU Memory rotection Unit M ower Management ontroller IT eriodic Interrupt Timer RS Low-speed R scillator REAM Reaction Module SIU System Integration Unit SE Signal rocessing Extension SRAM Static RAM STM System Timer Module SWT Software Watchdog Timer VA Variable ain Amplifier VLE Variable Length (instruction) Encoding XS XTAL scillator Figure 1. S564A70 series block diagram Doc ID Rev 4 11/133

12 Introduction S564A70B4, S564A70L7 Table 3 summarizes the functions of the blocks present on the S564A70 series microcontrollers. Table 3. S564A70 series block summary Block Function Boot assist module (BAM) alibration bus interface ontroller area network (FlexAN) rossbar switch (XBAR) yclic redundancy check (R) Deserial serial peripheral interface (DSI) e200z4 core Enhanced direct memory access (edma) Enhanced modular input-output system (emis) Enhanced queued analog-to-digital converter (eqad) Enhanced serial communication interface (esi) Enhanced time processor unit (etu2) Error orrection Status Module (ESM) Flash memory FlexRay Frequency-modulated phase-locked loop (FMLL) Interrupt controller (INT) JTA controller Memory protection unit (MU) Nexus port controller (N) eriodic interrupt timer (IT) Block of read-only memory containing executable code that searches for user-supplied boot code and, if none is found, executes the BAM boot code resident in device RM Transfers data across the crossbar switch to/from peripherals attached to the calibration tool connector Supports the standard AN communications protocol Internal busmaster R checksum generator rovides a synchronous serial interface for communication with external devices Executes programs and interrupt handlers erforms complex data movements with minimal intervention from the core. rovides the functionality to generate or measure events rovides accurate and fast conversions for a wide range of applications rovides asynchronous serial communication capability with peripheral devices and other microcontroller units Second-generation co-processor processes real-time input events, performs output waveform generation, and accesses shared data without host intervention The Error orrection Status Module supports a number of miscellaneous control functions for the platform, and includes registers for capturing information on platform memory errors if errorcorrecting codes (E) are implemented rovides storage for program code, constants, and variables rovides high-speed distributed control for advanced automotive applications enerates high-speed system clocks and supports programmable frequency modulation rovides priority-based preemptive scheduling of interrupt requests rovides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode rovides hardware access control for all memory references generated rovides real-time development support capabilities in compliance with the IEEE-IST standard roduces periodic interrupts and triggers 12/133 Doc ID Rev 4

13 S564A70B4, S564A70L7 Introduction Table 3. S564A70 series block summary (continued) Block Reaction Module (REAM) System Integration Unit (SIU) Static random-access memory (SRAM) System timers System watchdog timer (SWT) Temperature sensor Function Works in conjunction with the eqad and etu2 to increase system performance by removing the U from the current control loop. ontrols MU reset configuration, pad configuration, external interrupt, general purpose (I), internal peripheral multiplexing, and the system reset operation. rovides storage for program code, constants, and variables Includes periodic interrupt timer with real-time interrupt; output compare timer and system watchdog timer rovides protection from runaway code rovides the temperature of the device as an analog value 150 MHz e200z4 ower Architecture core Variable length instruction encoding (VLE) Superscalar architecture with 2 execution units Up to 2 integer or floating point instructions per cycle Up to 4 multiply and accumulate operations per cycle Memory organization 2 MB on-chip flash memory with E and read-while-write (RWW) 128 KB on-chip SRAM with standby functionality (32 KB) and E 8 KB instruction cache (with line locking), configurable as 2- or 4-way KB etu code and data RAM 4 4 crossbar switch (XBAR) 24-entry MMU Fail Safe rotection 16-entry Memory rotection Unit (MU) R unit with 3 submodules Junction temperature sensor Interrupt onfigurable interrupt controller (INT) with non-maskable interrupt (NMI) 64-channel edma Serial channels 3 esi modules 3 DSI modules (2 of which support downstream Micro Second hannel [MS]) 3 FlexAN modules with 64 message buffers each 1 FlexRay module (V2.1) up to Mbit/s w/dual or single channel, 128 message objects, E 1 emis 24 unified channels 1 etu2 (second generation etu) 32 standard channels Doc ID Rev 4 13/133

14 Introduction S564A70B4, S564A70L7 1 reaction module (6 channels with 3 outputs per channel) 2 enhanced queued analog-to-digital converters (eqads) Forty 12-bit input channels (multiplexed on 2 ADs); expandable to 56 channels with external multiplexers 6 command queues Trigger and DMA support 688 ns minimum conversion time n-chip AN/SI Bootstrap loader with Boot Assist Module (BAM) Nexus: lass 3+ for core; lass 1 for etu JTA (5-pin) Development Trigger Semaphore (DTS) EVT pin for communication with external tool lock generation n-chip 4 40 MHz main oscillator n-chip FMLL (frequency-modulated phase-locked loop) Up to 112 general purpose lines Individually programmable as input, output or special function rogrammable threshold (hysteresis) ower reduction modes: slow, stop, and standby Flexible supply scheme 5 V single supply with external ballast Multiple external supply: 5 V, 3.3 V, and 1.2 V 14/133 Doc ID Rev 4

15 S564A70B4, S564A70L7 Introduction 1.5 Feature details e200z4 core S564A70 devices have a high performance e200z4 core processor: 32-bit ower Architecture technology programmer s model Variable Length Encoding (VLE) enhancements Dual issue, 32-bit ower Architecture technology compliant U 8 KB, 2/4-way set associative instruction cache Thirty-two 64-bit general purpose registers (Rs) Memory Management Unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB) Harvard Architecture: Separate instruction bus and load/store bus Vectored interrupt support Non-maskable interrupt input ritical Interrupt input New Wait for Interrupt instruction, to be used with new low power modes Reservation instructions for implementing read-modify-write accesses Signal processing extension (SE) AU Single recision Floating point (scalar and vector) Nexus lass 3+ debug rocess ID manipulation for the MMU using an external tool In-order execution and retirement recise exception handling Branch processing unit Dedicated branch address calculation adder Branch target prefetching using 8-entry BTB Supports independent instruction and data accesses to different memory subsystems, such as SRAM and flash memory via independent Instruction and Data BIUs Load/store unit 2-cycle load latency Fully pipelined Big and Little endian support Misaligned access support Signal rocessing Extension (SE1.1) AU supporting SIMD fixed-point operations using the 64-bit eneral urpose Register file Embedded Floating-oint (EF2) AU supporting scalar and vector SIMD singleprecision floating-point operations, using the 64-bit eneral urpose Register file ower management Low power design extensive clock gating ower saving modes: wait Dynamic power management of execution units, cache and MMU Testability Doc ID Rev 4 15/133

16 Introduction S564A70B4, S564A70L7 Synthesizeable, MuxD scan design ABIST/MBIST for arrays Built-in arallel Signature Unit alibration support allowing an external tool to modify address mapping rossbar switch (XBAR) The XBAR multiport crossbar switch supports simultaneous connections between four master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features: 4 master ports U instruction bus U data bus edma FlexRay 4 slave ports Flash alibration bus interface SRAM eripheral bridge 32-bit internal address, 64-bit internal data paths Enhanced direct memory access (edma) The enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. The hardware micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TD) for the channels. This implementation minimizes overall block size. The edma module provides the following features: All data movement via dual-address transfers: read from source, write to destination rogrammable source and destination addresses, transfer size, plus support for enhanced addressing modes Transfer control descriptor organized to support two-deep, nested transfer operations An inner data transfer loop defined by a minor byte transfer count An outer data transfer loop defined by a major iteration count 16/133 Doc ID Rev 4

17 S564A70B4, S564A70L7 Introduction hannel activation via one of three methods: Explicit software initiation Initiation via a channel-to-channel linking mechanism for continuous transfers eripheral-paced hardware requests (one per channel) Support for fixed-priority and round-robin channel arbitration hannel completion reported via optional interrupt requests 1 interrupt per channel, optionally asserted at completion of major iteration count Error termination interrupts optionally enabled Support for scatter/gather DMA processing Ability to suspend channel transfers by a higher priority channel Interrupt controller (INT) The INT provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INT provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INT supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. The INT provides the following features: 9-bit vector addresses Unique vector for each interrupt request source Hardware connection to processor or read from register Each interrupt source can assigned a specific priority by software reemptive prioritized interrupt requests to processor ISR at a higher priority preempts executing ISRs or tasks at lower priorities Automatic pushing or popping of preempted priority to or from a LIF Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources Low latency 3 clocks from receipt of interrupt request from peripheral to interrupt request to processor This device also includes a non-maskable interrupt (NMI) pin that bypasses the INT and multiplexing logic Memory protection unit (MU) The Memory rotection Unit (MU) provides hardware access control for all memory references generated in a device. Using preprogrammed region descriptors, which define memory spaces and their associated access rights, the MU concurrently monitors all Doc ID Rev 4 17/133

18 Introduction S564A70B4, S564A70L7 system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. The MU has these major features: Support for 16 memory region descriptors, each 128 bits in size Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 B MU is invalid at reset, thus no access restrictions are enforced 2 types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus masters (edma, FlexRay) support {read, write} attributes Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only For overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software Support for two XBAR slave port connections (SRAM and BRIDE) For each connected XBAR slave port (SRAM and BRIDE), MU hardware monitors every port access using the preprogrammed memory region descriptors An access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference is terminated with an error response and the MU inhibits the bus cycle being sent to the targeted slave device 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail information Frequency-modulated phase-locked loop (FMLL) The FMLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal oscillator or external clock generator. Further, the FMLL supports programmable frequency modulation of the system clock. The LL multiplication factor, output clock divider ratio are all software configurable. The LL has the following major features: Input clock frequency from 4 MHz to 40 MHz Reduced frequency divider (RFD) for reduced frequency operation without forcing the LL to relock 3 modes of operation Bypass mode with LL off Bypass mode with LL running (default mode out of reset) LL normal mode Each of the 3 modes may be run with a crystal oscillator or an external clock reference 18/133 Doc ID Rev 4

19 S564A70B4, S564A70L7 Introduction rogrammable frequency modulation Modulation enabled/disabled through software Triangle wave modulation up to 0 khz modulation frequency rogrammable modulation depth (0% to 2% modulation depth) rogrammable modulation frequency dependent on reference frequency Lock detect circuitry reports when the LL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions lock Quality Module Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected Detects the quality of the LL output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request rogrammable interrupt request or system reset on loss of lock Self-clocked mode (SM) operation System integration unit (SIU) The S564A70 SIU controls MU reset configuration, pad configuration, external interrupt, general purpose (I), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of pins. The I block provides uniform and discrete input/output control of the pins of the MU. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTUT pin. ommunication between the SIU and the e200z4 U core is via the crossbar switch. The SIU provides the following features: System configuration MU reset configuration via external pins ad configuration control for each pad ad configuration control for virtual via DSI serialization System reset monitoring and generation ower-on reset support Reset status register provides last reset source to software litch detection on reset input Software controlled reset assertion External interrupt Rising or falling edge event detection rogrammable digital filter for glitch rejection ritical Interrupt request Non-Maskable Interrupt request I entralized control of and bus pins Virtual I via DSI serialization (requires external deserialization device) Dedicated input and output registers for setting each I and Virtual I pin Doc ID Rev 4 19/133

20 Introduction S564A70B4, S564A70L7 Internal multiplexing Allows serial and parallel chaining of DSIs Allows flexible selection of eqad trigger inputs Allows selection of interrupt requests between external pins and DSI From a set of etu output channels, allows selection of source signals for decimation filter integrators Flash memory The S564A70 provides 2 MB of programmable, non-volatile, flash memory. The nonvolatile memory (NVM) can be used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash array to match the U architecture. The flash module interfaces the system bus to a dedicated flash memory array controller. For U loads, DMA transfers and U instruction fetch, it supports a 64- bit data bus width at the system bus port, and 128-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. refetch buffer hits allow no-wait responses. The flash memory provides the following features: Supports a 64-bit data bus for instruction fetch, U loads and DMA access. Byte, halfword, word and doubleword reads are supported. nly aligned word and doubleword writes are supported. Fetch Accelerator Architected to optimize the performance of the flash onfigurable read buffering and line prefetch support 4-entry 128-bit wide line read buffer refetch controller Hardware and software configurable read and write access protections on a per-master basis Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for pipelined flash array designs onfigurable access timing usable in a wide range of system frequencies Multiple-mapping support and mapping-based block access timing (0 31 additional cycles) usable for emulation of other memory types Software programmable block program/erase restriction control Erase of selected block(s) Read page size of 128 bits (4 words) E with single-bit correction, double-bit detection rogram page size of 128 bits (4 words) to accelerate programming E single-bit error corrections are visible to software Minimum program size is 2 consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to E Embedded hardware program and erase algorithm Erase suspend, program suspend and erase-suspended program Shadow information stored in non-volatile shadow block Independent program/erase of the shadow block 20/133 Doc ID Rev 4

21 S564A70B4, S564A70L7 Introduction Static random access memory (SRAM) The SRAM provides 128 KB of general purpose system SRAM. The first 32 KB block of the SRAM is powered by its own power supply pin only during standby operation. The SRAM controller includes these features: 128 KB data RAM implemented as eight 16 KB ( bits) blocks Each 16 KB block has 2 rows repairable (RAMs with internal repair feature) Supports read/write accesses mapped to the SRAM memory from any master 32 KB block powered by separate supply for standby operation Byte, halfword, word and doubleword addressable E performs single bit correction, double bit detection 1.5. Boot assist module (BAM) The BAM is a block of read-only memory that is programmed once by ST and is identical for all S564A70 MUs. The BAM program is executed every time the MU is powered on or reset in normal mode. The BAM supports different modes of booting. They are: Booting from internal flash memory Serial boot loading (boot code is downloaded into RAM via esi or the FlexAN and then executed) The BAM also reads the reset configuration half word (RHW) from internal flash memory and configures the S564A70 hardware accordingly. The BAM provides the following features: Sets up MMU to cover all resources and mapping of all physical addresses to logical addresses with minimum address translation Sets up MMU to allow user boot code to execute as either ower Architecture technology code (default) or as VLE code Location and detection of user boot code Automatic switch to serial boot mode if internal flash is blank or invalid Supports user programmable 64-bit password protection for serial boot mode Supports serial bootloading via FlexAN bus and esi using standard protocol Supports serial bootloading via FlexAN bus and esi with auto baud rate sensing Supports serial bootloading of either ower Architecture technology code (default) or VLE code Supports booting from calibration bus interface Supports censorship protection for internal flash memory rovides an option to enable the core watchdog timer rovides an option to disable the system watchdog timer Enhanced modular input/output system (emis) The emis timer module provides the capability to generate or measure events in hardware. Doc ID Rev 4 21/133

22 Introduction S564A70B4, S564A70L7 The emis module features include: Twenty-four 24-bit wide channels 3 channels internal timebases sharable between channels 1 timebase from etu2 can be imported and used by the channels lobal enable feature for all emis and etu timebases Dedicated pin for each channel (not available on all package types) Each channel (0 23) supports the following functions: eneral urpose Input/utput (I) Single Action Input apture (SAI) Single Action utput ompare (SA) utput ulse Width Modulation Buffered (WMB) Input eriod Measurement (IM) Input ulse Width Measurement (IWM) Double Action utput ompare (DA) Modulus ounter Buffered (MB) utput ulse Width & Frequency Modulation Buffered (WFMB) Each channel has its own pin (not available on all package types) Second generation enhanced time processing unit (etu2) The etu2 is an enhanced co-processor designed for timing control. perating in parallel with the host U, the etu2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. onsequently, for each timer event, the host U setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the etu2 with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the etu2. S564A70 devices feature the second generation of the etu, called etu2. Enhancements of the etu2 over the standard etu include: The Timer ounter (TR1), channel logic and digital filters (both channel and the external timer clock input [TRLK]) now have an option to run at full system clock speed or system clock / 2. hannels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode. A new User rogrammable hannel Mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode. Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can also be requested simultaneously at the same instruction. hannel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point. hannel digital filters can be bypassed. 22/133 Doc ID Rev 4

23 S564A70B4, S564A70L7 Introduction The etu2 includes these distinctive features: 32 channels; each channel associated with one input and one output signal Enhanced input digital filters on the input pins for improved noise immunity Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. Input and output signal states visible from the host 2 independent 24-bit time bases for channel synchronization: First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time Both time bases can be exported to the emis timer module Both time bases visible from the host Event-triggered microengine: Fixed-length instruction execution in two-system-clock microcycle 14 KB of code memory (SM) 3 KB of parameter (data) RAM (SRAM) arallel execution of data memory, ALU, channel control and flow control subinstructions in selected combinations 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution Additional 24-bit Multiply/MA/Divide unit which supports all signed/unsigned Multiply/MA combinations, and unsigned 24-bit divide. The MA/Divide unit works in parallel with the regular microcode commands. Resource sharing features support channel use of common channel registers, memory and microengine time: Hardware scheduler works as a task management unit, dispatching event service routines by predefined, host-configured priority Automatic channel context switch when a task switch occurs, that is, one function thread ends and another begins to service a request from other channel: channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel SRAM shared between host U and etu2, supporting communication either between channels and host or inter-channel Hardware implementation of 4 semaphores support coherent parameter sharing between both etu engines Dual-parameter coherency hardware support allows atomic access to 2 parameters by host Doc ID Rev 4 23/133

24 Introduction S564A70B4, S564A70L7 Test and development support features: Nexus lass 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions Software breakpoints SM continuous signature-check built-in self test MIS (multiple input signature calculator), runs concurrently with etu2 normal operation Reaction module (REAM) The REAM provides the ability to modulate output signals to manage closed loop control without U assistance. It works in conjunction with the eqad and etu2 to increase system performance by removing the U from the current control loop. The REAM has the following features: 6 reaction channels with peak and hold control blocks Each channel output is a bus of 3 signals, providing ability to control 3 inputs. Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels Target applications include solenoid control for direct injection systems and valve control in automatic transmissions Enhanced queued analog-to-digital converter (eqad) The eqad block provides accurate and fast conversions for a wide range of applications. The eqad provides a parallel interface to two on-chip analog-to-digital converters (AD), and a single master to single slave serial interface to an off-chip external device. Both onchip ADs have access to all the analog channels. The eqad prioritizes and transfers commands from six command conversion command queues to the on-chip ADs or to the external device. The block can also receive data from the on-chip ADs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either AD and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADs were performing when the trigger occurred. The eqad supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip ADs or to the external device. It also monitors the fullness of command queues and result queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system memory, which is external to the eqad. The ADs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. The eqad also integrates a programmable decimation filter capable of taking in AD conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result FIFs. This allows the ADs to sample the sensor at a rate high enough to avoid aliasing of 24/133 Doc ID Rev 4