SPC560B40x, SPC560B50x SPC560C40x, SPC560C50x

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1 Features LQFP144 (20 x 20 x 1.4 mm) High-performance 64 MHz e200z0h PU 32-bit Power Architecture technology Up to 60 DMPs operation Variable length encoding (VLE) SP560B40x, SP560B50x SP56040x, SP56050x 32-bit MU family built on the Power Architecture for automotive body electronics applications LQFP100 (14 x 14 x 1.4 mm) Memory Up to 512 KB ode Flash with E 64 KB Data Flash with E Up to 48 KB SRAM with E 8-entry memory protection unit (MPU) nterrupts 16 priority levels Non-maskable interrupt (NM) Up to 34 external interrupts incl. 18 wakeup lines GPO: 45(LQFP64), 75(LQFP100), 123(LQFP144) Timer units 6-channel 32-bit periodic interrupt timers 4-channel 32-bit system timer module Software watchdog timer Real-time clock timer 16-bit counter time-triggered s Up to 56 channels with PWM/M//O AD diagnostic via TU ommunications interface LQFP64 (10 x 10 x 1.4 mm) Table 1. Device summary Datasheet - production data Up to 6 FlexAN interfaces (2.0B active) with 64-message objects each Up to 4 LNFlex/UART 3 DSP / 2 Single 5 V or 3.3 V supply 10-bit analog-to-digital converter (AD) with up to 36 channels Extendable to 64 channels via external multiplexing ndividual conversion registers ross triggering unit (TU) Dedicated diagnostic module for lighting Advanced PWM generation Time-triggered diagnostic PWM-synchronized AD measurements lock generation 4 to 16 MHz fast external crystal oscillator (FXOS) 32 khz slow external crystal oscillator (SXOS) 16 MHz fast internal R oscillator (FR) 128 khz slow internal R oscillator (SR) Software-controlled FMPLL lock monitor unit (MU) Exhaustive debugging capability Nexus1 on all devices Nexus2+ available on emulation package (LBGA208) Low power capabilities Ultra-low power standby with RT, SRAM and AN monitoring Fast wakeup schemes Operating temp. range up to -40 to 125 Part number Package 256 KB code Flash memory 512 KB code Flash memory LQFP144 SP560B40L5 SP560B50L5 LQFP100 SP560B40L3 SP56040L3 SP560B50L3 SP56050L3 LQFP64 (1) SP560B40L1 SP56040L1 SP560B50L1 SP56050L1 1. All LQFP64information is indicative and must be confirmed during silicon validation. February 2015 DocD14619 Rev 13 1/116 This is information on a product in full production.

2 ontents SP560B40x/50x, SP56040x/50x ontents 1 ntroduction Document overview Description Block diagram Package pinouts and signal descriptions Package pinouts Pad configuration during reset phases Voltage supply pins Pad types System pins Functional ports Nexus 2+ pins Electrical characteristics ntroduction Parameter classification NVUSRO register NVUSRO[PAD3V5V] field description NVUSRO[OSLLATOR_MARGN] field description NVUSRO[WATHDOG_EN] field description Absolute maximum ratings Recommended operating conditions Thermal characteristics Package thermal characteristics Power considerations pad electrical characteristics pad types input D characteristics output D characteristics Output pin transition times pad current specification /116 DocD14619 Rev 13

3 SP560B40x/50x, SP56040x/50x ontents 3.16 RESET electrical characteristics Power management electrical characteristics Voltage regulator electrical characteristics Low voltage detector electrical characteristics Power consumption Flash memory electrical characteristics Program/Erase characteristics Flash power supply D characteristics Start-up/Switch-off timings Electromagnetic compatibility (EM) characteristics Designing hardened software to avoid noise problems Electromagnetic interference (EM) Absolute maximum ratings (electrical sensitivity) Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Slow external crystal oscillator (32 khz) electrical characteristics FMPLL electrical characteristics Fast internal R oscillator (16 MHz) electrical characteristics Slow internal R oscillator (128 khz) electrical characteristics AD electrical characteristics ntroduction nput impedance and AD accuracy AD electrical characteristics On-chip peripherals urrent consumption DSP characteristics Nexus characteristics JTAG characteristics Package characteristics EOPAK Package mechanical data LQFP LQFP LQFP LBGA DocD14619 Rev 13 3/116 4

4 ontents SP560B40x/50x, SP56040x/50x 5 Ordering information Appendix A Abbreviations Revision history /116 DocD14619 Rev 13

5 SP560B40x/50x, SP56040x/50x List of tables List of tables Table 1. Device summary Table 2. SP560B40x/50x and SP56040x/50x device comparison Table 3. SP560B40x/50x and SP56040x/50x series block summary Table 4. Voltage supply pin descriptions Table 5. System pin descriptions Table 6. Functional port pin descriptions Table 7. Nexus 2+ pin descriptions Table 8. Parameter classifications Table 9. PAD3V5V field description Table 10. OSLLATOR_MARGN field description Table 11. WATHDOG_EN field description Table 12. Absolute maximum ratings Table 13. Recommended operating conditions (3.3 V) Table 14. Recommended operating conditions (5.0 V) Table 15. LQFP thermal characteristics Table 16. input D electrical characteristics Table 17. pull-up/pull-down D electrical characteristics Table 18. SLOW configuration output buffer electrical characteristics Table 19. MEDUM configuration output buffer electrical characteristics Table 20. FAST configuration output buffer electrical characteristics Table 21. Output pin transition times Table 22. supply segment Table 23. consumption Table 24. weight Table 25. Reset electrical characteristics Table 26. Voltage regulator electrical characteristics Table 27. Low voltage detector electrical characteristics Table 28. Power consumption on VDD_BV and VDD_HV Table 29. Program and erase specifications Table 30. Flash module life Table 31. Flash read access timing Table 32. Flash memory power supply D electrical characteristics Table 33. Start-up time/switch-off time Table 34. EM radiated emission measurement Table 35. ESD absolute maximum ratings Table 36. Latch-up results Table 37. rystal description Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Table 39. rystal motional characteristics Table 40. Slow external crystal oscillator (32 khz) electrical characteristics Table 41. FMPLL electrical characteristics Table 42. Fast internal R oscillator (16 MHz) electrical characteristics Table 43. Slow internal R oscillator (128 khz) electrical characteristics Table 44. AD input leakage current Table 45. AD conversion characteristics Table 46. On-chip peripherals current consumption Table 47. DSP characteristics Table 48. Nexus characteristics DocD14619 Rev 13 5/116 6

6 List of tables SP560B40x/50x, SP56040x/50x Table 49. JTAG characteristics Table 50. LQFP64 mechanical data Table 51. LQFP100 mechanical data Table 52. LQFP144 mechanical data Table 53. LBGA208 mechanical data Table 54. Abbreviations Table 55. Document revision history /116 DocD14619 Rev 13

7 SP560B40x/50x, SP56040x/50x List of figures List of figures Figure 1. SP560B40x/50x and SP56040x/50x block diagram Figure 2. LQFP 64-pin configuration Figure 3. LQFP 100-pin configuration Figure 4. LQFP 144-pin configuration Figure 5. LBGA208 configuration Figure 6. input D electrical characteristics definition Figure 7. Start-up reset requirements Figure 8. Noise filtering on reset signal Figure 9. Voltage regulator capacitance connection Figure 10. V DD_HV and V DD_BV maximum slope Figure 11. V DD_HV and V DD_BV supply constraints during STANDBY mode exit Figure 12. Low voltage detector vs reset Figure 13. rystal oscillator and resonator connection scheme Figure 14. Fast external crystal oscillator (4 to 16 MHz) timing diagram Figure 15. rystal oscillator and resonator connection scheme Figure 16. Equivalent circuit of a quartz crystal Figure 17. Slow external crystal oscillator (32 khz) timing diagram Figure 18. AD characteristic and error definitions Figure 19. nput equivalent circuit (precise channels) Figure 20. nput equivalent circuit (extended channels) Figure 21. Transient behavior during sampling phase Figure 22. Spectral representation of input signal Figure 23. DSP classic SP timing master, PHA = Figure 24. DSP classic SP timing master, PHA = Figure 25. DSP classic SP timing slave, PHA = Figure 26. DSP classic SP timing slave, PHA = Figure 27. DSP modified transfer format timing master, PHA = Figure 28. DSP modified transfer format timing master, PHA = Figure 29. DSP modified transfer format timing slave, PHA = Figure 30. DSP modified transfer format timing slave, PHA = Figure 31. DSP PS strobe (PSS) timing Figure 32. Nexus TD, TMS, TDO timing Figure 33. Timing diagram JTAG boundary scan Figure 34. LQFP64 package mechanical drawing Figure 35. LQFP100 package mechanical drawing Figure 36. LQFP144 package mechanical drawing Figure 37. LBGA208 package mechanical drawing Figure 38. ommercial product code structure DocD14619 Rev 13 7/116 7

8 ntroduction SP560B40x/50x, SP56040x/50x 1 ntroduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Description The SP560B40x/50x and SP56040x/50x is a family of next generation microcontrollers built on the Power Architecture embedded category. The SP560B40x/50x and SP56040x/50x family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. t belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. t operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. t capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 8/116 DocD14619 Rev 13

9 DocD14619 Rev 13 9/116 PU Feature SP560B 40L1 SP560B 40L3 Table 2. SP560B40x/50x and SP56040x/50x device comparison (1) SP560B 40L5 SP560 40L1 SP560 40L3 Device SP560B 50L1 e200z0h SP560B 50L3 SP560B 50L5 Execution speed (2) Static up to 64 MHz ode Flash 256 KB 512 KB Data Flash 64 KB (4 16 KB) SP560 50L1 SP560 50L3 RAM 24 KB 32 KB 32 KB 48 KB MPU 8-entry SP560B 50B2 AD (10-bit) 12 ch 28 ch 36 ch 8 ch 28 ch 12 ch 28 ch 36 ch 8 ch 28 ch 36 ch TU Total timer (3) emos 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit PWM + M + /O (4) 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch PWM + /O (4) 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch /O (4) 3 ch 6 ch 3 ch 3 ch 6 ch 3 ch 6 ch Yes 12 ch, 16-bit 28 ch, 16-bit S (LNFlex) 3 (5) 4 SP (DSP) AN (FlexAN) 2 (6) (7) khz oscillator Yes GPO (8) ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit SP560B40x/50x, SP56040x/50x ntroduction

10 10/116 DocD14619 Rev 13 Feature SP560B 40L1 Table 2. SP560B40x/50x and SP56040x/50x device comparison (1) (continued) SP560B 40L3 SP560B 40L5 SP560 40L1 SP560 40L3 Debug JTAG Nexus2+ Device SP560B 50L1 SP560B 50L3 Package LQFP64 (9) LQFP100 LQFP144 LQFP64 (9) LQFP100 LQFP64 (9) LQFP100 LQFP144 LQFP64 (9) LQFP Feature set dependent on selected peripheral multiplexingtable shows example implementation. 2. Based on 125 ambient operating temperature. 3. See the emos section of the device reference manual for information on the channel configuration and functions. 4. nput apture; O Output ompare; PWM Pulse Width Modulation; M Modulus counter. 5. S0, S1 and S2 are available. S3 is not available. 6. AN0, AN1 are available. AN2, AN3, AN4 and AN5 are not available. 7. AN0, AN1 and AN2 are available. AN3, AN4 and AN5 are not available. 8. count based on multiplexing with peripherals. 9. All LQFP64 information is indicative and must be confirmed during silicon validation. 10. LBGA208 available only as development package for Nexus2+. SP560B 50L5 SP560 50L1 SP560 50L3 SP560B 50B2 LBGA208 (10) ntroduction SP560B40x/50x, SP56040x/50x

11 SP560B40x/50x, SP56040x/50x Block diagram 2 Block diagram Figure 1 shows a top-level block diagram of the SP560B40x/50x and SP56040x/50x device series. DocD14619 Rev 13 11/

12 Block diagram SP560B40x/50x, SP56040x/50x Figure 1. SP560B40x/50x and SP56040x/50x block diagram JTAG port JTAG SRAM 48 KB ode Flash 512 KB Data Flash 64 KB Nexus port NM locks FMPLL Nexus Voltage regulator NM nterrupt requests from peripheral blocks MU e200z0h Nexus 2+ NT nstructions (Master) Data (Master) MPU registers 64-bit 2 x 3 rossbar Switch MPU SRAM controller (Slave) Flash controller (Slave) (Slave) RT STM SWT ESM PT M_RGM M_GM M_ME M_PU BAM SSM Peripheral bridge nterrupt request Reset control External interrupt request 36 h. AD TU 2 x emos 4 x LNFlex 3 x DSP 2 6 x FlexAN MUX GPO and pad control WKPU nterrupt request with wakeup functionality Legend: AD Analog-to-Digital onverter BAM Boot Assist Module FlexAN ontroller Area Network MU lock Monitor Unit TU ross Triggering Unit DSP Deserial Serial Peripheral nterface emos Enhanced Modular nput Output System FMPLL Frequency-Modulated Phase-Locked Loop 2 nter-integrated ircuit Bus MUX nternal Multiplexer NT nterrupt ontroller JTAG JTAG controller LNFlex Serial ommunication nterface (LN support) ESM Error orrection Status Module M_GM lock Generation Module M_ME Mode Entry Module M_PU Power ontrol Unit M_RGM Reset Generation Module MPU Memory Protection Unit Nexus Nexus Development nterface (ND) Level NM Non-Maskable nterrupt PT Periodic nterrupt Timer RT Real-Time lock System ntegration Unit Lite SRAM Static Random-Access Memory SSM System Status onfiguration Module STM System Timer Module SWT Software Watchdog Timer WKPU Wakeup Unit Table 3 summarizes the functions of all blocks present in the SP560B40x/50x and SP56040x/50x series of microcontrollers. Please note that the presence and number of blocks vary by device and package. 12/116 DocD14619 Rev 13

13 SP560B40x/50x, SP56040x/50x Block diagram Table 3. SP560B40x/50x and SP56040x/50x series block summary Block Function Analog-to-digital converter (AD) Boot assist module (BAM) lock monitor unit (MU) ross triggering unit (TU) Deserial serial peripheral interface (DSP) Error orrection Status Module (ESM) Enhanced Direct Memory Access (edma) Enhanced modular input output system (emos) Flash memory Multi-channel, 10-bit analog-to-digital converter A block of read-only memory containing VLE code which is executed according to the boot mode of the device Monitors clock source (internal and external) integrity Enables synchronization of AD conversions with a timer event from the emos or from the PT Provides a synchronous serial interface for communication with external devices Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Performs complex data transfers with minimal intervention from a host processor via n programmable channels. Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables FlexAN (controller area network) Supports the standard AN communications protocol Frequency-modulated phaselocked loop (FMPLL) nternal multiplexer (MUX) SU subblock nter-integrated circuit ( 2 ) bus nterrupt controller (NT) JTAG controller LNFlex controller lock generation module (M_GM) Mode entry module (M_ME) Power control unit (M_PU) Reset generation module (M_RGM) Generates high-speed system clocks and supports programmable frequency modulation Allows flexible mapping of peripheral interface on the different pins of the device A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Manages a high number of LN (Local nterconnect Network protocol) messages efficiently with a minimum of PU load Provides logic and control required for the generation of system and peripheral clocks Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called power domains which are controlled by the PU entralizes reset sources and manages the device reset sequence of the device DocD14619 Rev 13 13/

14 Block diagram SP560B40x/50x, SP56040x/50x Table 3. SP560B40x/50x and SP56040x/50x series block summary (continued) Block Memory protection unit (MPU) Nexus development interface (ND) Periodic interrupt timer (PT) Real-time counter (RT) System integration unit (SU) Static random-access memory (SRAM) System status configuration module (SSM) System timer module (STM) Software watchdog timer (SWT) Wakeup unit (WKPU) rossbar (XBAR) switch Provides hardware access control for all memory references generated in a device Provides real-time development support capabilities in compliance with the EEE-STO standard Produces periodic interrupts and triggers A free running counter used for time keeping applications, the RT can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Provides storage for program code, constants, and variables Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable Provides a set of output compare events to support AUTOSAR (Automotive Open System Architecture) and operating system tasks Provides protection from runaway code Function The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. 14/116 DocD14619 Rev 13

15 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions 3 Package pinouts and signal descriptions 3.1 Package pinouts The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual (RM0017). Figure 2. LQFP 64-pin configuration (a) PB[3] P[9] PA[2] PA[1] PA[0] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV P[10] PB[0] PB[1] P[6] PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_AD VSS_HV_AD P[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4] PB[2] P[8] P[4] P[5] PH[9] P[0] VSS_LV VDD_LV VDD_HV VSS_HV P[1] PH[10] PA[6] PA[5] P[2] P[3] LQFP64 Top view a. All LQFP64 information is indicative and must be confirmed during silicon validation. DocD14619 Rev 13 15/

16 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Figure 3. LQFP 100-pin configuration PB[3] P[9] P[14] P[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV P[11] P[10] PB[0] PB[1] P[6] PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_AD VSS_HV_AD P[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] PB[2] P[8] P[13] P[12] PE[7] PE[6] PE[5] PE[4] P[4] P[5] PE[3] PE[2] PH[9] P[0] VSS_LV VDD_LV VDD_HV VSS_HV P[1] PH[10] PA[6] PA[5] P[2] P[3] PE[12] LQFP100 Top view Note: Availability of port pin alternate functions depends on product selection. 16/116 DocD14619 Rev 13

17 DocD14619 Rev 13 17/116 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions 115 Figure 4. LQFP 144-pin configuration PB[3] P[9] P[14] P[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] P[11] P[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] P[6] PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_AD VSS_HV_AD P[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] PB[2] P[8] P[13] P[12] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] P[4] P[5] PE[3] PE[2] PH[9] P[0] VSS_LV VDD_LV VDD_HV VSS_HV P[1] PH[10] PA[6] PA[5] P[2] P[3] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] LQFP144 Note: Availability of port pin alternate functions depends on product selection. Top view

18 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Figure 5. LBGA208 configuration A P[8] P[13] N N PH[8] PH[4] P[5] P[0] N N P[2] N PE[15] N N N A B P[9] PB[2] N P[12] PE[6] PH[5] P[4] PH[9] PH[10] N P[3] PG[11] PG[15] PG[14] PA[11] PA[10] B P[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV P[1] N PA[5] N PE[14] PE[12] PA[9] PA[8] D N N P[15] N PH[6] PE[4] PE[2] VDD_LV VDD_HV N PA[6] N PG[10] PF[14] PE[13] PA[7] D E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV N N MSEO G H VSS_HV PE[11] VDD_HV N VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H J RESET VSS_LV N N VSS_HV VSS_HV VSS_HV VSS_HV N N N N J K EVT N VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV N PG[12] PA[3] PG[13] K L PG[9] PG[8] N EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] P[10] P[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] N N PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] N PB[11] PD[10] PD[9] PD[11] N P PF[8] N P[7] N N PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_HV _AD PB[6] PB[7] P R PF[12] P[6] PF[10] PF[11] VDD_HV PA[15] PA[13] N OS32K _XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_HV _AD PB[5] R T N N N MKO N PF[13] PA[12] N OS32K _EXTAL PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T Note: LBGA208 available only as development package for Nexus 2+. N = Not connected 3.2 Pad configuration during reset phases All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are forced to tristate with the following exceptions: PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash. PA[8] (ABS[0]) is pull-up. RESET pad is driven low. This is pull-up only after PHASE2 reset completion. JTAG pads (TK, TMS and TD) are pull-up whilst TDO remains tristate. Precise AD pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available). Main oscillator pads (EXTAL, XTAL) are tristate. Nexus output pads (MDO[n], MKO, EVTO, MSEO) are forced to output. 18/116 DocD14619 Rev 13

19 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions 3.3 Voltage supply pins Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization. Table 4. Voltage supply pin descriptions Port pin Function Pin number LQFP64 LQFP100 LQFP144 LBGA208 (1) VDD_HV Digital supply voltage 7, 28, 56 VSS_HV Digital ground 6, 8, 26, 55 VDD_LV VSS_LV 15, 37, 70, 84 14, 16, 35, 69, 83 19, 51, 100, , 20, 49, 99, 122 2, D9, E16, G13, H3, N9, R5 G7, G8, G9, G10, H1, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10 1.2V decoupling pins. Decoupling capacitor must be connected between 11, 23, 57 19, 32, 85 23, 46, 124 D8, K4, P7 these pins and the nearest V SS_LV pin. (2) 1.2V decoupling pins. Decoupling capacitor must be connected between 10, 24, 58 18, 33, 86 22, 47, 125 8, J2, N7 these pins and the nearest V DD_LV pin. (2) VDD_BV nternal regulator supply voltage K3 VSS_HV_AD VDD_HV_AD Reference ground and analog ground for the AD Reference voltage and analog supply for the AD R P14 1. LBGA208 available only as development package for Nexus2+ 2. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details). 3.4 Pad types n the device the following types of pads are available for system pins and functional port pins: S = Slow (b) (b) (c) M = Medium (b) (c) F = Fast = nput only with analog feature (b) J = nput/output ( S pad) with analog feature X = Oscillator b. See the pad electrical characteristics in the device datasheet for details. DocD14619 Rev 13 19/

20 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x 3.5 System pins The system pins are listed in Table 5. Table 5. System pin descriptions Pin number System pin Function direction Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (1) RESET EXTAL XTAL Bidirectional reset with Schmitt-Trigger characteristics and noise filter. M nput, weak pull-up only after PHASE J1 Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. Analog input for the clock generator when the oscillator X Tristate N8 is in bypass mode. (2) Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator is used in bypass mode. (2) X Tristate P8 1. LBGA208 available only as development package for Nexus2+ 2. See the relevant section of the datasheet 3.6 Functional ports The functional port pins are listed in Table 6. c. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PR.SR in section Pad onfiguration Registers (PR0 PR122) in the device reference manual). 20/116 DocD14619 Rev 13

21 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PA[0] PR[0] GPO[0] E0U[0] LKOUT WKPU[19] (4) emos_0 GL WKPU O M Tristate G4 PA[1] PR[1] GPO[1] E0U[1] NM (5) WKPU[2] (4) emos_0 WKPU WKPU S Tristate F3 PA[2] PR[2] GPO[2] E0U[2] WKPU[3] (4) emos_0 WKPU S Tristate F2 PA[3] PR[3] GPO[3] E0U[3] ERQ[0] emos_0 S Tristate K15 PA[4] PR[4] GPO[4] E0U[4] WKPU[9] (4) emos_0 WKPU S Tristate N6 PA[5] PR[5] GPO[5] E0U[5] emos_0 M Tristate PA[6] PR[6] GPO[6] E0U[6] ERQ[1] emos_0 S Tristate D11 DocD14619 Rev 13 21/

22 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PA[7] PR[7] GPO[7] E0U[7] LN3TX ERQ[2] emos_0 LNFlex_3 O S Tristate D16 PA[8] PR[8] N/A (6) GPO[8] E0U[8] ERQ[3] ABS[0] LN3RX emos_0 BAM LNFlex_3 S nput, weak pull-up PA[9] PR[9] N/A (6) GPO[9] E0U[9] FAB emos_0 BAM S Pull-down PA[10] PR[10] GPO[10] E0U[10] SDA emos_0 2_0 S Tristate B16 PA[11] PR[11] GPO[11] E0U[11] SL emos_0 2_0 S Tristate B15 PA[12] PR[12] GPO[12] SN_0 DSP0 S Tristate T7 PA[13] PR[13] GPO[13] SOUT_0 DSP_0 O M Tristate R7 22/116 DocD14619 Rev 13

23 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PA[14] PR[14] GPO[14] SK_0 S0_0 ERQ[4] DSP_0 DSP_0 M Tristate P6 PA[15] PR[15] GPO[15] S0_0 SK_0 WKPU[10] (4) DSP_0 DSP_0 WKPU M Tristate R6 PB[0] PR[16] GPO[16] AN0TX FlexAN_0 O M Tristate N3 PB[1] PR[17] GPO[17] WKPU[4] (4) AN0RX WKPU FlexAN_0 S Tristate N1 PB[2] PR[18] GPO[18] LN0TX SDA LNFlex_0 2_0 O M Tristate B2 PB[3] PR[19] GPO[19] SL WKPU[11] (4) LN0RX 2_0 WKPU LNFlex_0 S Tristate PB[4] PR[20] GPO[20] GP[0] AD Tristate T16 DocD14619 Rev 13 23/

24 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PB[5] PR[21] GPO[21] GP[1] AD Tristate R16 PB[6] PR[22] GPO[22] GP[2] AD Tristate P15 PB[7] PR[23] GPO[23] GP[3] AD Tristate P16 PB[8] PR[24] GPO[24] ANS[0] OS32K_XTAL (7) AD SXOS Tristate R9 PB[9] PR[25] GPO[25] ANS[1] OS32K_EXTAL ( 7) AD SXOS Tristate T9 PB[10] PR[26] GPO[26] ANS[2] WKPU[8] (4) AD WKPU J Tristate P9 24/116 DocD14619 Rev 13

25 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PB[11] (8) PR[27] GPO[27] E0U[3] S0_0 ANS[3] emos_0 DSP_0 AD J Tristate N13 PB[12] PR[28] GPO[28] E0U[4] S1_0 ANX[0] emos_0 DSP_0 AD O J Tristate M16 PB[13] PR[29] GPO[29] E0U[5] S2_0 ANX[1] emos_0 DSP_0 AD O J Tristate M13 PB[14] PR[30] GPO[30] E0U[6] S3_0 ANX[2] emos_0 DSP_0 AD O J Tristate L16 PB[15] PR[31] GPO[31] E0U[7] S4_0 ANX[3] emos_0 DSP_0 AD O J Tristate L13 P[0] (9) PR[32] GPO[32] TD JTAG M nput, weak pull-up A8 P[1] (9) PR[33] GPO[33] TDO (10) JTAG O M Tristate DocD14619 Rev 13 25/

26 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) P[2] PR[34] GPO[34] SK_1 AN4TX (11) ERQ[5] DSP_1 FlexAN_4 O M Tristate A11 P[3] PR[35] GPO[35] S0_1 MA[0] AN1RX AN4RX (11) ERQ[6] DSP_1 AD FlexAN_1 FlexAN_4 O S Tristate B11 P[4] PR[36] GPO[36] SN_1 AN3RX (11) DSP_1 FlexAN_3 M Tristate B7 P[5] PR[37] GPO[37] SOUT_1 AN3TX (11) ERQ[7] DSP1 FlexAN_3 O O M Tristate A7 P[6] PR[38] GPO[38] LN1TX LNFlex_1 O S Tristate R2 P[7] PR[39] GPO[39] LN1RX WKPU[12] (4) LNFlex_1 WKPU S Tristate P3 26/116 DocD14619 Rev 13

27 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) P[8] PR[40] GPO[40] LN2TX LNFlex_2 O S Tristate A1 P[9] PR[41] GPO[41] LN2RX WKPU[13] (4) LNFlex_2 WKPU S Tristate B1 P[10] PR[42] GPO[42] AN1TX AN4TX (11) MA[1] FlexAN_1 FlexAN_4 AD O O O M Tristate M3 P[11] PR[43] GPO[43] AN1RX AN4RX (11) WKPU[5] (4) FlexAN_1 FlexAN_4 WKPU S Tristate M4 P[12] PR[44] GPO[44] E0U[12] SN_2 emos_0 DSP_2 M Tristate B4 P[13] PR[45] GPO[45] E0U[13] SOUT_2 emos_0 DSP_2 O S Tristate A2 P[14] PR[46] GPO[46] E0U[14] SK_2 ERQ[8] emos_0 DSP_2 S Tristate DocD14619 Rev 13 27/

28 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) P[15] PR[47] GPO[47] E0U[15] S0_2 emos_0 DSP_2 M Tristate 4 4 D3 PD[0] PR[48] GPO[48] GP[4] AD Tristate P12 PD[1] PR[49] GPO[49] GP[5] AD Tristate T12 PD[2] PR[50] GPO[50] GP[6] AD Tristate R12 PD[3] PR[51] GPO[51] GP[7] AD Tristate P13 PD[4] PR[52] GPO[52] GP[8] AD Tristate R13 PD[5] PR[53] GPO[53] GP[9] AD Tristate T13 28/116 DocD14619 Rev 13

29 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PD[6] PR[54] GPO[54] GP[10] AD Tristate T14 PD[7] PR[55] GPO[55] GP[11] AD Tristate R14 PD[8] PR[56] GPO[56] GP[12] AD Tristate T15 PD[9] PR[57] GPO[57] GP[13] AD Tristate N15 PD[10] PR[58] GPO[58] GP[14] AD Tristate N14 PD[11] PR[59] GPO[59] GP[15] AD Tristate N16 PD[12] ( 8) PR[60] GPO[60] S5_0 E0U[24] ANS[4] DSP_0 emos_0 AD O J Tristate M15 DocD14619 Rev 13 29/

30 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PD[13] PR[61] GPO[61] S0_1 E0U[25] ANS[5] DSP_1 emos_0 AD J Tristate M14 PD[14] PR[62] GPO[62] S1_1 E0U[26] ANS[6] DSP_1 emos_0 AD O J Tristate L15 PD[15] PR[63] GPO[63] S2_1 E0U[27] ANS[7] DSP_1 emos_0 AD O J Tristate L14 PE[0] PR[64] GPO[64] E0U[16] AN5RX (11) WKPU[6] (4) emos_0 FlexAN_5 WKPU S Tristate 6 10 F1 PE[1] PR[65] GPO[65] E0U[17] AN5TX (11) emos_0 FlexAN_5 O M Tristate 8 12 F4 PE[2] PR[66] GPO[66] E0U[18] SN_1 emos_0 DSP_1 M Tristate D7 PE[3] PR[67] GPO[67] E0U[19] SOUT_1 emos_0 DSP_1 O M Tristate /116 DocD14619 Rev 13

31 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PE[4] PR[68] GPO[68] E0U[20] SK_1 ERQ[9] emos_0 DSP_1 M Tristate D6 PE[5] PR[69] GPO[69] E0U[21] S0_1 MA[2] emos_0 DSP_1 AD O M Tristate PE[6] PR[70] GPO[70] E0U[22] S3_0 MA[1] emos_0 DSP_0 AD O O M Tristate B5 PE[7] PR[71] GPO[71] E0U[23] S2_0 MA[0] emos_0 DSP_0 AD O O M Tristate PE[8] PR[72] GPO[72] AN2TX (12) E0U[22] AN3TX (11) FlexAN_2 emos_0 FlexAN_3 O O M Tristate 9 13 G2 PE[9] PR[73] GPO[73] E0U[23] WKPU[7] (4) AN2RX (12) AN3RX (11) emos_0 WKPU FlexAN_2 FlexAN_3 S Tristate G1 PE[10] PR[74] GPO[74] LN3TX S3_1 ERQ[10] LNFlex_3 DSP_1 O O S Tristate G3 DocD14619 Rev 13 31/

32 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PE[11] PR[75] GPO[75] S4_1 LN3RX WKPU[14] (4) DSP_1 LNFlex_3 WKPU O S Tristate H2 PE[12] PR[76] GPO[76] E1U[19] (13) SN_2 ERQ[11] emos_1 DSP_2 S Tristate PE[13] PR[77] GPO[77] SOUT2 E1U[20] DSP_2 emos_1 O S Tristate 103 D15 PE[14] PR[78] GPO[78] SK_2 E1U[21] ERQ[12] DSP_2 emos_1 S Tristate PE[15] PR[79] GPO[79] S0_2 E1U[22] DSP_2 emos_1 M Tristate 113 A13 PF[0] PR[80] GPO[80] E0U[10] S3_1 ANS[8] emos_0 DSP_1 AD O J Tristate 55 N10 PF[1] PR[81] GPO[81] E0U[11] S4_1 ANS[9] emos_0 DSP_1 O J Tristate 56 P10 32/116 DocD14619 Rev 13

33 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PF[2] PR[82] GPO[82] E0U[12] S0_2 ANS[10] emos_0 DSP_2 AD J Tristate 57 T10 PF[3] PR[83] GPO[83] E0U[13] S1_2 ANS[11] emos_0 DSP_2 AD O J Tristate 58 R10 PF[4] PR[84] GPO[84] E0U[14] S2_2 ANS[12] emos_0 DSP_2 AD O J Tristate 59 N11 PF[5] PR[85] GPO[85] E0U[22] S3_2 ANS[13] emos_0 DSP_2 AD O J Tristate 60 P11 PF[6] PR[86] GPO[86] E0U[23] ANS[14] emos_0 AD J Tristate 61 T11 PF[7] PR[87] GPO[87] ANS[15] AD J Tristate 62 R11 PF[8] PR[88] GPO[88] AN3TX (14) S4_0 AN2TX (15) FlexAN_3 DSP_0 FlexAN_2 O O O M Tristate 34 P1 DocD14619 Rev 13 33/

34 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PF[9] PR[89] GPO[89] S5_0 AN2RX (15) AN3RX (14) DSP_0 FlexAN_2 FlexAN_3 O S Tristate 33 N2 PF[10] PR[90] GPO[90] M Tristate 38 R3 PF[11] PR[91] GPO[91] WKPU[15] (4) WKPU S Tristate 39 R4 PF[12] PR[92] GPO[92] E1U[25] emos_1 M Tristate 35 R1 PF[13] PR[93] GPO[93] E1U[26] WKPU[16] (4) emos_1 WKPU S Tristate 41 T6 PF[14] PR[94] GPO[94] AN4TX (11) E1U[27] AN1TX FlexAN_4 emos_1 FlexAN_4 O O M Tristate 102 D14 PF[15] PR[95] GPO[95] AN1RX AN4RX (11) ERQ[13] FlexAN_1 FlexAN_4 S Tristate 101 E15 34/116 DocD14619 Rev 13

35 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PG[0] PR[96] GPO[96] AN5TX (11) E1U[23] FlexAN_5 emos_1 O M Tristate 98 E14 PG[1] PR[97] GPO[97] E1U[24] AN5RX (11) ERQ[14] emos_1 FlexAN_5 S Tristate 97 E13 PG[2] PR[98] GPO[98] E1U[11] emos_1 M Tristate 8 E4 PG[3] PR[99] GPO[99] E1U[12] WKPU[17] (4) emos_1 WKPU S Tristate 7 E3 PG[4] PR[100] GPO[100] E1U[13] emos_1 M Tristate 6 E1 PG[5] PR[101] GPO[101] E1U[14] WKPU[18] (4) emos_1 WKPU S Tristate 5 E2 PG[6] PR[102] GPO[102] E1U[15] emos_1 M Tristate 30 M2 DocD14619 Rev 13 35/

36 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PG[7] PR[103] GPO[103] E1U[16] emos_1 M Tristate 29 M1 PG[8] PR[104] GPO[104] E1U[17] S0_2 ERQ[15] emos_1 DSP_2 S Tristate 26 L2 PG[9] PR[105] GPO[105] E1U[18] SK_2 emos_1 DSP_2 S Tristate 25 L1 PG[10] PR[106] GPO[106] E0U[24] emos_0 S Tristate 114 D13 PG[11] PR[107] GPO[107] E0U[25] emos_0 M Tristate 115 B12 PG[12] PR[108] GPO[108] E0U[26] emos_0 M Tristate 92 K14 PG[13] PR[109] GPO[109] E0U[27] emos_0 M Tristate 91 K16 PG[14] PR[110] GPO[110] E1U[0] emos_1 S Tristate 110 B14 36/116 DocD14619 Rev 13

37 SP560B40x/50x, SP56040x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PG[15] PR[111] GPO[111] E1U[1] emos_1 M Tristate 111 B13 PH[0] PR[112] GPO[112] E1U[2] SN1 emos_1 DSP_1 M Tristate 93 F13 PH[1] PR[113] GPO[113] E1U[3] SOUT1 emos_1 DSP_1 O M Tristate 94 F14 PH[2] PR[114] GPO[114] E1U[4] SK_1 emos_1 DSP_1 M Tristate 95 F16 PH[3] PR[115] GPO[115] E1U[5] S0_1 emos_1 DSP_1 M Tristate 96 F15 PH[4] PR[116] GPO[116] E1U[6] emos_1 M Tristate 134 A6 PH[5] PR[117] GPO[117] E1U[7] emos_1 S Tristate 135 B6 PH[6] PR[118] GPO[118] E1U[8] MA[2] emos_1 AD O M Tristate 136 D5 DocD14619 Rev 13 37/

38 Package pinouts and signal descriptions SP560B40x/50x, SP56040x/50x Table 6. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET configuration LQFP64 LQFP100 LQFP144 LBGA208 (3) PH[7] PR[119] GPO[119] E1U[9] S3_2 MA[1] emos_1 DSP_2 AD O O M Tristate PH[8] PR[120] GPO[120] E1U[10] S2_2 MA[0] emos_1 DSP_2 AD O O M Tristate 138 A5 PH[9] (9) PR[121] GPO[121] TK JTAG S nput, weak pull-up B8 PH[10] ( 9) PR[122] GPO[122] TMS JTAG S nput, weak pull-up B9 1. Alternate functions are chosen by setting the values of the PR.PA bitfields inside the module. PR.PA = 00 ; PR.PA = 01 ; PR.PA = 10 ; PR.PA = 11. This is intended to select the output functions; to use one of the input functions, the PR.BE bit must be written to 1, regardless of the values selected in the PR.PA bitfields. For this reason, the value corresponding to an input only function is reported as. 2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMO.PADSELx bitfields inside the module. 3. LBGA208 available only as development package for Nexus2+ 4. All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details. 5. NM has higher priority than alternate function. When NM is selected, the PR.AF field is ignored. 6. Not applicable because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details. 7. Value of PR.BE bit must be 0 8. Be aware that this pad is used on the SP560B64L3 and SP560B64L5 to provide VDD_HV_AD and VSS_HV_AD1. Therefore, you should be careful in ensuring compatibility between SP560B40x/50x and SP56040x/50x and SP560B Out of reset all the functional pins except P[0:1] and PH[9:10] are available to the user as GPO. P[0:1] are available as JTAG pins (TD and TDO respectively). PH[9:10] are available as JTAG pins (TK and TMS respectively). f the user configures these JTAG pins in GPO mode the device is no longer compliant with EEE The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of k should be added between the TDO pin and VDD_HV. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin and GND instead. 38/116 DocD14619 Rev 13