IMP16C554 IMP 16C554. Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFO's. Data Communications. Description.

Transcription

1 Data Communicatio Quad Universal Asynchronous Receiver/Tramitter (UART) with FFO's Description MP6C554 The MP6C554 is a universal asynchronous receiver and tramitter with 6 byte tramit and receive FFO. A programmable baud rate generator is provided to select tramit and receive clock rates from 5Hz to.5mhz. The MP6C554 is an improved version of the MP6C55 UART with higher operating speed and lower access time. The MP6C554 on board status registers provides the error conditio, type and status of the trafer operation being performed. ncluded is complete MODEM control capability, and a processor interrupt system that may be software tailored to the user s requirements. The MP6C554 provides internal loop-back capability for on board diagnostic testing. The MP6C554 is fabricated in an advanced.2u CMOS process to achieve low drain power and high speed requirements. Key Features 6 byte receive FFO with error flags Modem control signal (CTS*, RTS*, DSR*, DTR*, R*,CD*) Programmable character lengths(5,6,7,8) Even, odd, or no parity bit generation and detection Status report register ndependent tramit and receive control TLL compatible inputs. outputs Software compatible with Ei825, Ei6C kHz tramit/receive operation with MHz crystal or external clock source Pin Configuration DSRA CTSA DTRA CC RTSA NTA CSA TXA OW TXB CSB NTB RTSB GND DTRB CTSD DSRB DSRD CTSD DTRD GND RTSD NTD CSD TXD OR TXC CSC NTC RTSC CC DTRC CTSC DSRC DSRA CTSA DTRA CC RTSA NTA CSA TXA OW TXB CSB NTB RTSB GND DTRB CTSD DSRD CTSD DTRD GND RTSD NTD CSD TXD OR TXC CSC NTC RTSC CC DTRC CTSC CDB RB RXB CC NC A2 A A XTAL XTAL2 ERSET RXRDY TXRD GND RXC RC CDC DSBS CDS RB RXB CC A2 A A XTAL XTAL2 RESET GND RXC RC CDC DSRC CDA RA RXA GND D7 D6 D5 D4 D3 D2 D D NTSEL CC RXD RD CDO CDA RA RXA GND D7 D6 D5 D4 D3 D2 D D CC RXD RD COD MP 6C MP 6C PN PLCC 64-PN QFP

2 MP6C554 SYMBOL DESCRPTON symbol pin Signal Type Pin Description D-D /O Bi-directional data bus. Eight bit, three state data bus to trafer information to or from the CPU. Do is the least significant bit of the data bus and the first serial data bit to be received or tramitted. RX A-B RX C-D Serial data input. The serial information (data) received from serial port to MP6C554 receive input circuit. A mark (high) is logic one and a space (low)is logic zero. During the local loopback mode the RX input is disabled from external connection and to the TX output internally. TX A-B TX C-D O Serial data output. The serial data is tramitted via this pin with additional start, stop and parity bits. The TX will be held in mark(high) state during reset, local loopback mode or when the tramitter is disabled. CS*A-B CS*C-D Chip select. (active low) A low at this pin enables the MP6C554/CPU data trafer operation. Each UART sectio of the MP6C554 can be accessed independently. XTAL 35 Crystal input or external clock input. A crystal can be connected to this pin and XTAL2 pin to utilize the internal oscillator circuit. An external clock can be used to clock internal circuit and baud rate generator for custom tramission rates. XTAL2 36 O Crystal input 2 or buffered clock output. See XTAL. LOW* 8 Write strobe.(active low)a low on this pin will trafer the contents of the CPU data bus to the addressed register. GND GND O Signal and power ground. OR* 52 Read strobe.(active low)a low level on this pin trafers the contents of the MP6C554 data bus to the CPU. 2

3 MP6C554 SYMBOL DESCRPTON symbol pin Signal Type Pin Description TXRDY* 39 O Tramit ready. (active low) This pin goes high when the tramit FFO of the MP6C554 is full. t can be used as a single or multi-trafer. A2 32 Address select line 2.To select internal registers. A 33 Address select line.to select internal registers. A 34 Address select line.to select internal registers. RXRDY* 38 O Receive ready.(active low ) This pin goes low when the receive FFO is full. t can be used as a single or multi-trafer. NTSEL 65 nterrupt type select. Enable /disable the interrupt three state function. Normal interrupt output can be selected by connecting this pin to CC(MCR bit-3 does not have any effect on the interrupt output ).The three state interrupt output is selected when this pin is left open or connected to GND and MCR bit-3 is to. NT A-B NT C-D O nterrupt output.( active high) this pin goes high (when enable by the interrupt enable register)whenever a receiver error. receiver data available. tramitter empty, or modem status condition flag is detected. RTS*A-B RTS*C-D O Request to send.(active low) To indicate that the tramitter has data ready to send.writing a in the modem control register(mcr bit-) will set this pin to a low state. After the reset this pin will be set to high. Note that this pin does not have any effect on the tramit or receive operation. DTR*A-B DTR*C-D O Data terminal ready. (active low) To indicate that MP6C554 is ready to receive data. This pin can be controlled via the modem control register (MCR bit-).writing a at the MCR bit- will set the DTR* output to low. 3

4 MP6C554 SYMBOL DESCRPTON symbol pin Signal Type Pin Description This pin will be set to high state after writing a to that register or after the reset. Note that this pin does not have any effect on the tramit or receive operation. RESET 37 Master reset.(active high)a high on this pin will reset all the outputs and internal registers. The tramitter output and the receiver input will be disabled during reset time. CTS*A-B CTS*C-D Clear to send. (active low) The CTS* signal is a MODEM control function input whose conditio can be tested by reading the MSR BT-4. CTS* has no effect on the tramit or receive operation. DSR*A-B DSR*C-D Data set ready. ( active low) A low on this pin indicates the MODEM is ready to exchange data with UART. This pin does not have any effect on the tramit or receive operation. CD*A-B CD*C-D Carrier detect.(active low) A low on this pin indicates the carrier has been detected by the modem. R*A-B R*C-D Ring detect indicator. ( active low) A low on this pin indicates the modem has received a ringing signal from telephone line. CC CC Power supply input. 4

5 MP6C554 MP6C554 ACCESSBLE REGSTERS A2AA Registe BT-7 BT-6 BT-5 BT-4 BT-3 BT-2 BT- BT- r RHR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit- bit- THR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit- bit- ER Modem Receiv Trami Receive status e line t holding interrup t status interru holding register register FCR RC R trigge r (MSB ) SR /FF Os enabl ed LCR Divis or latch enabl e RC R trigge r (LSB) /FF Os enabl ed Set break DMA Mode select int priority bit-2 Set parity Even parity MCR Loop back LSR o/ff tra break O empt interr error y upt tra holdi ng empt y Parity enable NT enable framing error pt XMTF FO reset nt priority bit- Stop bits Not used parity error RCRF FO reset nt priority bit- Word length bit- RTS* overrun error FFO enable nt status Word length bit- DTR* receive data ready MSR CD R DSR CTS delta CD* delta R* delta DSR* delta CTS* SPR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit- bit- DLL bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit- bit- DLM bit-5 bit-4 bit-3 bit-2 bit- bit- bit-9 bit-8 DLL and DLM are accessible only when LCR bit-7 is set to. 5

6 MP6C554 PROGAMMNG TABLE A2 A A READ MODE WRTE MODE Receive Holding Register nterrupt Status Register Line Status Register Modem Status Register Scratchpad Register Tramit Holding Register nterrupt Enable Register FFO Control Register Line Control Register Modem Control Register Scratchpad Register LSB of Divisor Latch MSB of Divisor Latch REGSTER FUNCTONAL DESCRPTONS TRANSMT AND RECEE HOLDNG REGSTER The serial tramitter section coists of a Tramit Hold Register (THR) and Tramit Shift Register (TSR).The status of the tramit hold register is provided in the Line status Register(LSR).Writing to this register (THR)will trafer the contents of data bus(d7-d) to the Tramitter shift register is empty. The tramit holding register empty flag will be set to when the tramitter is empty or data is traferred to the tramit shift register. Note that a write operation should be performed when the tramit holding register empty flag is set. On the falling edge of the start bit. the receiver internal counter will start to count 7 /2 clocks (6x clock) which is the center of the start bit. The start bit is valid if the RX is still low at the mid-bit sample of the start bit. erifying the start bit prevents the receiver from assembling a false data character due to a low going noise spike on the RX input. Receiver status codes will be posted in the Line Status Register. FFO NTERRUPT MODE OPERATON When the receive FFO (FCR BT-=) and receive interrupts (ER BT-=) are enabled. receiver interrupt will occur as follows. A)The receive data available interrupts will be issued to the CPU when the FFO has reached its programmed trigger level; it will be cleared as soon as the FFO drops below its programmed trigger level. B)The SR receive data available indication also occurs when the FFO trigger level is reached, and like the interrupt it is cleared when the FFO dorps below the trigger level. C)The data ready bit (LSR BT-) is set as soon as a character is traferred from the shift register to the receiver FFO. t is reset when the FFO is empty. FFO POLLED MODE OPERATON When FCR BT-=;resetting ER BT 3- to zero puts the MP6C554 in the FFO polled mode of operation. Since the receiver and 6

7 MP6C554 tramitter are controlled separately either one or both can in the polled mode operation by utilizing the Line status Register. A) LSR BT- will be set as long as there is one byte in the receive FFO. B) LSR BT4- will specify which error(s) has occurred. C) LSR BT-5 will indicate when the tramit FFO is empty. D) LSR BT-6 will indicate when both tramit FFO and tramit shift register are empty. E) LSR BT-6 will indicate when there are any errors in the receive FFO. The MS6C554 requires to have two step FFO enable operation in order to enable receive trigger levels. PROGRAMMABLE BAUD RATE GENERATOR The MP6C554 contai a programmable Baud Rate Generator that is capable of taking any clock input from DC-24 MHz and dividing it by any divisor from to 26-.The output frequency of the Baud out* is equal to 6X of tramission baud rate (Baudout*=6 x Baud Rate). Customize Baud Rates can be achieved by selecting proper divisor values for MSB and LSB of baud rate generator. NTERRUPT ENABLE REGSTER (ER) The interrupt Enable Register (ER) masks the incoming interrupts from receiver ready, tramitter empty, line status and modem status registers to the NT output pin. ER BR- =disable the receiver ready interrupt. =enable the receiver ready interrupt. ER BR- =disable the tramitter empty interrupt. =enable the tramitter empty interrupt. ER BR-2 =disable the receiver line status interrupt. =enable the receiver line status interrupt. ER BR-3 =disable the modem status register interrupt. =enable the modem status register interrupt. ER BR7-4 All these bits are set to logic zero. NTERRUPT STATUS REGSTER (SR) The MP6C554 provides four level prioritized interrupt conditio to minimize software overhead during data character trafers. The interrupt Status Register (SR) provides the source of the interrupt in prioritized matter. During the read cycle the MP6C554 provides the highest interrupt level to be serviced by CPU. No other interrupts are acknowledged until the particular interrupt is serviced. The following sre the prioritized interrupt levels: Priority level P D3 D2 C D Source of the interrupt LSR (Receiver Line Status Register) 2 RXRDY (Received Data Ready) 2* RXRDY (Received Data time out) 3 TXRDY (Tramitter Holding Register Empty) 4 MSR (Modem Status Register) *RECEE TME-OUT: This mode is enabled when the UART is operating in FFO mode. Receive time out will not occur if the receive FFO is empty. The time out counter will be reset at the center of each stop bit received or each time out value is T (Time out length in bits)=4 X P (Programmed word length)+2. To convert time out value to a character value, user has to divide this number to its complete word length + parity (if used)+number of stop bits and start bit. Example-A: if user programs the word length=7,and no parity and one stop bit. Time out will be:t=4x7(programmed word length)+2=4 bits Character time =4 / 9 (programmed word length=7)+(stop bit=)+(start bi=)=4.4 characters. Example-B: if user programs the word length=7,with parity and one stop bit, the time out will be: T=4x7 (programmed word length)+2=4 bits Character time =4 / (programmed word length=7) + (parity=) + 7

8 MP6C554 (stop bit=) + (start bi=) =4 characters. SR BT-: =an interrupt is pending and the SR contents may be used as a pointer to the appropriate interrupt service routine. =no interrupt pending. SR BT -3: Logical combination of these bits, provides the highest priority interrupt pending. SR BT 4-7: These bits are not used and are set to zero in MS6C45 mode. BT 6-7:are set to in MS6C554 mode. FFO CONTROL REGSTER (FCR) This register is used to enable the FFOs, clear the FFOs, set the receiver FFO trigger level, and select the type of DMA signaling. FCR BT-: =Diosable the tramit and receive FFO. =Enable the tramit and receive FFO. This is bit should be enabled before setting the FFO trigger levels. FCR BT-: =No change. =Clears the contents of receive FFO and resets its counter logic to ( the receive shift register is not cleared or altered). This bit will return to zero after clearing the FFOs. FCR BT-2: =No change. =Clears the contents of the tramit FFO and resets its counter logic to (the tramit shift register is not cleared or altered). This bit will return to zero after clearing the FFOs. FCR BT-3: =No change. = Changes RXRDY and TXRDY pi from mode to mode. Tramit operation in mode : When MP6C554 is in MS6C45 mode (FCR bit-=) or in the FFO mode (FCR bit-=,fcr bit-3=) when there are no characters in the tramit FFO or tramit holding register, the TXRDY* pin will go low. Once active the TXRDY* pin will go high (inactive) after the first character is loaded into the tramit holding register. Receive operation in mode : When MP6C554 is in MP6C45 mode (FCR bit-=) or in the FFO mode (FCR bit-=,fcr bit-3=) and there is at least character in the receive FFO, the RXRDY* pin will go low. Once active the RXRDY* pin will go high (inactive) when there are no more characters in the receiver. Tramit operation in mode : When MP6C554 is in MP6C55 mode (FCR bit-=,fcr bit-3=) the TXRDY* pin will become high (inactive) when the tramit FFO is completely full. t will be low if one or more FFO locatio are empty. Receive operation in mode : When MP6C554 is in MP6C55 mode (FCR bit-=,fcr bit-3=) and the trigger level or the timeout has been reached, the RXRDY* pin will go low. Once it is activated it will go high (inactive) when are no more characters in the FFO. FCR BT 4-5: Not used. FCR BT 6-7: These bits are used to set the trigger level for the receiver FFO interrupt. BT-7 BT-6 FFO trigger level LNE CONTROL REGSTER (LCR) The Line Control Register is used to specify the asynchronous data communication format. The number of the word length, stop bits, and parity can be selected by writing appropriate bits in this register. LCR BT-: These two bits specify the word length to be tramitted or received. BT- BT- Word length

9 MP6C554 8 LCR BT-2: The number of stop bits can specified by this bit. BT-2 Word length Stop bit(s) 5, 6, 7 5 6, 7, 8 -/2 2 LCR BT-3: Parity or no parity can be selected via this bit. = no parity =a parity bit is generated during the tramission. receiver also checks for received parity. LCR BT-4: f the parity bit is enabled, LCR BT-4 selects the even or odd parity format. = ODD parity bit is generated by forcing an odd number of `s in the tramitted data, receiver also checks for same format. =EEN parity bit is generated by forcing an even number of `s in the tramitted data, receiver also checks for same format. LCR BT-5: f the parity bit is enabled, LCR BT-5 selects the forced parity format. LCR BT-5= and LCR BT-4=, parity bit is forced to in the tramitted and received data. LCR BT-5= and LCR BT-4=, parity bit is forced to in the tramitted and received data. LCR BT-6: Break control bit. t causes a break condition to be tramitted (the TX is forced to low state). = normal operating condition. =forces the tramitter output (TX) to go low to alert the communication terminal. LCR BT-7: The internal baud rate counter latch enable (DLAB). =normal operation. =select divisor latch register. MODEM CONTROL REGSTER (MCR) This register controls the interface with the MODEM or a peripheral device (RS232). MCR BT-: =force DTR* output to high. =force DTR* output to low. MCR BT-: =force RTS* output to high. =force RTS* output to low. MCR BT-2: No used, except in internal loop-back mode. MCR BT-3: =set the NT A-D output pin to three state mode. =Enable the NT A-D output pin. MCR BT-4: =normal operation mode. =enable local loop-back mode (diagnostics). The tramitter output (TX) is set high (Mark condition), the receiver input (RX), CTS*, DSR*, CD*, and R* are disabled. nternally the tramitter output is connected to the receiver input and DTR*, RTS*, MCR* bit-2 and NT enable are connected to modem control inputs. n this mode, the receiver and tramitter interrupts are fully operational. The Modem Control interrupts are also operational. but the interrupts sources are now the lower four bits of the Modem Control Register itead of the four Modem Control inputs. The interrupts are still controlled by the ER. MCR BT 5-7: Not used. Are set to zero permanently. LNE STATUS REGSTER (LSR) This register provides the status of data trafer to CPU. LSR BT-: =no data in receive holding register or FFO. =data has been received and saved in the receive holding register or FFO. LSR BT-: =no overrun error (normal). = overrun error, next character arrived before receive holding register was emptied or if FFOs are enabled. an overrun error will occur only after the FFO is full and the next character has been completely received in the shift register. Note that character in the shift register is over written, but it is not traferred to the FFO. 9

10 MP6C554 LSR BT-2: =no parity error (normal). = parity error, received data does not have correct parity information. n the FFO mode this error is associated with the character at the top of the FFO. LSR BT-3: =no framing error (normal). =framing error received, received data did not have a valid stop bit. n the FFO mode this error is associated with the character at the top of the FFO. LSR BT-4: =no break condition (normal). =receiver received a break signal (RX was low for one character time frame). n FFO mode, only one zero character is loaded into the FFO. LSR BT-5: =tramit holding register is full. MP6C554 will not accept any data for tramission. = tramit holding register (or FFO) is empty. CPU can load the next character. LSR BT-6: =tramit holding register and shift register are full. =tramit holding register and shift register are empty. n FFO mode this bit is set to one whenever the tramitter FFO and tramit shift register are empty. LSR BT-7: = Normal. = At least one parity error, framing error or break indication in the FFO. This bit is cleared when LSR is read. MODEM STATUS REGSTER (MSR) This register provides the current state of the control lines from the modem or peripheral to the CPU. Four bits of this register are used to indicate the changed information. These bits are set to whenever a control input from the MODEM changes state. They are set to whenever the CPU reads this register. MSR BT-: ndicates that the CTS* input to the MP6C554 has changed state since the last time it was read. MSR BT-: ndicates that the DSR* input to the MP6C554 has changed state since the last time it was read. MSR BT-2: ndicates that the R* input to the MP6C554 has changed from a low to a high state. MSR BT-3: ndicates that the CD* input to the ST6C554 has changed state since the last time it was read. MSR BT-4 This bit is equivalent to RTS in the MCR during local loop-back mode. t is the compliment of the CTS* input. MSR BT-5: This bit is equivalent to DTR in the MCR during local loop-back mode. t is the compliment of the DSR* input. MSR BT-6: This bit is equivalent to MCR bit-2 during local loop-back mode. t is the compliment of the R* input. MSR BT-7: This bit is equivalent to NT enable in the MCR during local loop-back mode. t is the compliment of the CD* input. Note: whenever MSR BT3-: is set to logic, a MODEM Status nterrupt is generated. SCRATCHPAD REGSTER (SR) MP6C554 provides a temporary data register to store 8 bits of information for variable use. BAUD RATE GENERATOR PROGRAMMNG TABLE (.8432 MHz CLOCK): BAUD RATE x CLOCK DSOR % ERROR.26

11 MP6C K 38.4K 56K 5.2K MSR FCR 7= MSR BTS -3=, MSR BTS 4-7=input signals FCR BT -7= MP6C554 EXTERNAL RESET CONDTON REGSTER RESET STATE ER SR LCR MCR LSR ER BT -7= SR BT-=, SR BT -7= LCR BTS -7= MCR BTS -7= LSR BTS -4=, LSR BTS 5-6= LSR,BT SGNALS TX A-D RTS* A-D DTR* A-D RXRDY* TXRDY* NT A-D RESET STATE High High High High Low Three state mode AC ELECTRCAL CHARACTERSTCS TA= 7 C,cc= 5.±% unless otherwise specified Symbol Parameter Limits Min Typ Max T 2 T2 2 T3 T8 5 T9 T2 5 T3 5 T4 T5 5 T6 T7 55 Tw 5 T T2 T23 65 T24 T25 55 Tr 5 T26 35 T28 5 T29 7 T3 T3 T32 T33 T34 T35 T44 T45 T46 T47 Clock high pulse duration Clock low pulse duration Clock rise/fall time Chip select setup time Chip setup time Data setup time Data hold time OW* delay from chip select OW* strobe width Chip select hold time from OW* Write cycle delay Write cycle =T5+T7 Data hold time OR* delay from chip select OR* strobe width Chip select hold time from LOR* Read cycle delay Read cycle =T23+T25 Delay from OR* to data Delay from OW* to output Delay to set interrupt from MODEM input Delay to reset interrupt from OR* Delay from stop to set interrupt Delay from OR* to reset interrupt Delay from initial NT reset to tramit start Delay from stop to interrupt Delay from OW* to reset interrupt Delay from stop to set RxRdy Delay from OR* to reset RxRdy Delay from OW* to set TxRdy Delay from start to reset TxRdy 8 7 Rck RCL K 95 8 Units * us * Conditio pf load pf load pf load pf load pf load pf load N Baud rate devisor 26- Note : = Baudout cycle

12 MP6C554 ABSOLUTE MAXMUM RATNGS Supply range oltage at any pin Operating temperature Storage temperature Package dissipation 7 olts GND-.3 to CC+.3 C to +7 C -4 C to 5 C 5 Mw DC ELECTRCAL CHARACTERSTCS TA=*-7* C, cc= 5. ±% unless otherwise specified. symbol Parameter Limits Min Typ Max Units conditio LCK HCK L H OL OH CC L CL Clock input low level Clock input high level nput low level nput high level Output low level on all outputs Output high level Avg power supply current nput leakage Clock leakage vcc.8 vcc.4 4 ± ± ma ua ua LOL=6 ma LOH=-6 ma LCK HCK L H OL OH CC Clock input low level Clock input high level input low level input high level Output low level on all outputs output high level Avg power supply current vcc.8 vcc.4 2 ma CC=3. CC=3. CC =3. cc=3. CC=3., lol=8.5 ma CC=3., loh=-4 ma CC=3. 2

13 MP6C554 A-A2 CSx* T8 T9 T2 T23 T24 T25 OR* T26 T9 D-D7 FGURE - GENERAL READ TMNG 6245-RD- A-A2 CSx* T8 T9 T4 T5 T6 T7 OW* T2 T3 D-D WD- FGURE 2 - GENERAL WRTE TMNG 3

14 MP6C554 OW* T28 RTS* DTR* CD CTS DSR T29 T29 NTx T3 T29 OR* R 6245-MD- FGURE 3 - MODEM TMNG T2 T3 EXTERNAL CLOCK T CLOCK PEROD CLOCK PEROD T3 645-CK- FGURE 4 - CLOCK TMNG 4

15 MP6C554 START BT DATA BTS 5-8 STOP BT TX D D D2 D3 D4 D5 D6 D7 5 DATA BTS 6 DATA BTS 7 DATA BTS PARTY BT NEXT DATA START BT T34 NTx T33 T35 OW* 6 BAUD RATE CLOCK 6245-TX- FGURE 5 5

16 MP6C554 START BT DATA BTS 5-8 STOP BT RX (First byte) D D D2 D3 D4 D5 D6 D7 5 DATA BTS PARTY BT 6 DATA BTS 7 DATA BTS RXRDY* T44 T45 OR* 6552-RX-2 FGURE 6 - RXRDY TMNG FOR MODE "" 6

17 MP6C554 START BT DATA BTS 5-8 STOP BT RX D D D2 D3 D4 D5 D6 D7 5 DATA BTS 6 DATA BTS 7 DATA BTS PARTY BT First byte that reaches the trigger level RXRDY* T44 T45 OR* 6552-RX-3 FGURE 7 - RXRDY TMNG FOR MODE "" 7

18 MP6C554 START BT DATA BTS 5-8 STOP BT RX D D D2 D3 D4 D5 D6 D7 5 DATA BTS 6 DATA BTS 7 DATA BTS PARTY BT NEXT DATA START BT T3 NTx T32 OR* 6 BAUD RATE CLOCK 6245-RX- FGURE 8 - RECEE TMNG 8

19 MP6C554 START BT DATA BTS 5-8 STOP BT TX D D D2 D3 D4 D5 D6 D7 5 DATA BTS PARTY BT 6 DATA BTS 7 DATA BTS OW* D-D7 BYTE# T46 T47 TXRDY* 6552-TX-2 FGURE 9 - TXRDY TMNG FOR MODE "" 9

20 MP6C554 START BT DATA BTS 5-8 STOP BT TX D D D2 D3 D4 D5 D6 D7 5 DATA BTS PARTY BT 6 DATA BTS 7 DATA BTS OW* D-D7 BYTE#6 T46 T47 TXRDY* FFO FULL 6552-TX-3 FGURE - TXRDY TMNG FOR MODE "" Ordering nformation Part Number Package Operating Temperature MP6C554-CJ68 PLCC 68pi to +7 MP6C554-LJ68 PLCC 68pi -4 to +85 Life Support Policy: MP s products are not to be used in life support devices without prior written authorization. MP Retai the right to make changes to these specificatio at any time without notice. 2

21 MP6C554 Microelectronics Co.,Ltd 7 Keda Road, Hi-Tech Park, NingBo,Zhejiang, P.R.C. Post Code : 354 Tel:(86) Fax:(86) sales@ds-imp.com.cn The MP logo is a registered trademark of. All other company and product names are trademarks of their respective owners. 25 Revision : A ssue Date: 8 / 8 / 5 Type: Product