PERIPHERAL INTERFACING Rev. 1.0

Transcription

1 PERIPHERAL INTERFACING Rev.. This work is licensed under the Creative Commons Attribution-NonCommercial-Share Alike 2.5 India License. To view a copy of this license, visit or send a letter to Creative Commons, 7 Second Street, Suite 3, San Francisco, California, 945, USA. Part #

2 PERIPHERAL INTERFACING Rev.. COMMUNICATION BETWEEN TWO MICROPROCESSORS OBJECTIVE To establish communication between the two 885 Microprocessor by writing an assembly language program to transmitter and receiver APPARATUS REQUIRED Single board microcomputer (VI Microsystems 85). RS 232 Connector. Flat Ribbon Cable. DESCRIPTION When data are transmitted as voltage, the commonly used standard is known as RS 232C. It is defined in reference to data terminal equipment (DTE) and data communication equipment (DCE) terminal and modern. Its voltage levels are not compatible with TTL logic levels. The rate of data transmission in RS 232C, is restricted to a maximum of 2k baud and a distance of 5ft, for high speed data transmission, new standards RS - 422A and RS - 423A developed in recent years. The RS 232C is a 25 pin connector and its signals are divided in to four groups signals, control signals, timing signals and ground. The minimum interface between a computer and a peripheral requires three lines 2, 3, and 7. These lines are defined in relation to the DTE, the terminal transmits on pin2, and receiver other hand, the DCE transmits on pin3, receiver on pin2. The transmit and receive lines cross, hence it is known as NULL MODEM CONNECTION. ALGORITHM Transmitter Receiver Initialize the timer and USART of the transmitter. Set the starting address of data to be transmitted and the number of bytes to be transmitted. Program the USART for serial data transmission. Stop the execution. Intialize the timer and USART of receiving data. Set the starting address of data received. Program the USART for serial data reception. Receive the data from RS-232 pin and stop the execution. Part #2

3 PERIPHERAL INTERFACING Rev.. NULL MODEM CONNECTION NC T X D R X D NC T X D R X D CTS RTS RTS CTS NC GND NC GND RS 232 DETAILS - 25 PIN PIN SIGNALS Protective ground 2 Transmitted data (TXD) -> DCE 3 Received data (RXD) -> DTE 4 Request to send (RST)->DCE 5 Clear to send (CTS) -> DTE 6 Data set ready (DSR) -> DTE 7 Signal ground 8 Received line signal detector 9, Reserved for data set testing Unassigned 2 Secondary Clear to send 3 Secondary Recorded line signal detector 4 Secondary Transmitted data 5 Transmission signal element timing ( DCE source) 6 Secondary Received data 7 Receiver signal element timing ( DCE source) 8 Unassigned 9 Secondary request to send 2 DCE <- data terminal ready (DTR) 2 Signal quality detector 22 ring indicator Part #3

4 PERIPHERAL INTERFACING Rev.. 23 data signal rate selector (DTE/DCE source) 24 Transmit signal element timing 25 Unassigned COMMAND INSTRUCTION FORMAT OF 825A DATA BIT DESCRIPTION D TXEN TRANSMIT ENABLE ENABLE ; DISABLE D DTR DATA TERMINAL READY HIGH WILL FORCE DTR OUTPUT TO D 2 RXE RECEIVE ENABLE ENABLE ; DISABLE D 3 SBRK SEND BREAK CHARACTER = FORCE TXD LOW = NORMAL OPERATION D 4 ER ERROR RESET = RESET ERROR FLAGS OF, PE, OE, FE D 5 RTS REQUEST TO SEND HIGH WILL FORCE RTS OUPUT TO D 6 IR INTERNAL RESET HIGH RETURNS 825A TO MODE INSTRUCTION FORMAT D 7 EH ENTER HUNT MODE ENABLE A SEARCH FOR SYNCRONOUS CHARACTER ( HAS NO EFFECT IN ASYNCRONOUS MODE ) STATUS WORD FORMAT 825A DATA BIT DESCRIPTION D TXRDY TRANSMITTER READY TXRDY status bit has different meanings from the TXRDY output pin. The former is not conditioned by CTS & TXEN (i.e) TXRDY status bit = DB buffer empty TXRDY pin out = DB buffer empty. (CTS ) (TXEN ). D RXRDY RECEIVER READY This bit indicates that the 825A contains a character that is ready to be input to the CPU D 2 TXEMPTY TRANSMITTER EMPTY When the 825A has no character to transmit this bit will go high D 3 PE PARITY ERROR The PE flag is set when a parity error is detected. It is reset by the ER bit of the command instruction. PE does not inhibit operation of the 825A D 4 OE OVERFLOW ERROR The OE flag is set when the CPU does not read a character before the next one becomes available. OE is reset by the ER bit of the command instruction. OE does not inhibit the operation of 825A however the previously overrun character is lost. D 5 FE FRAMING ERROR(Asynchronous mode only) The FE flag is set when a valid stop bit is not detected at end of every character. It is reset by the ER BIT of the command instruction. FE does not inhibit the operation of 825A. D 6 SYNDET SYNC DETECT This pin is used in synchronous mode for syndet and is used in asynchronous mode for break detect. D 7 DSR DATA SET READY Indicates that the DSR is at zero level. Part #4

5 PERIPHERAL INTERFACING Rev.. ASYNCRONOUS MODE OF 825A DATA BIT D B D B2 D 2 L D 3 L2 D 4 PEN D 5 EP D 6 S D 7 S2 DESCRIPTION Baud rate Factor B2 B Syncronous mode X 6X 64X Character Length L2 L 5 bits 6 bits 7 bits 8 bits Parity Enable ENABLE DISABLE Even parity Generation Check ODD EVEN No of Stop bit S2 S Invalid bit.5 bits 2 bits CONTORL WORD FORMAT 8253 DATA BIT DESCRIPTION D BCD D M D 2 M D 3 M2 D 4 RL D 5 RL D 6 SC D 7 SC BINARY/BCD MODE M2 M M MODE READ/LOAD RL RL Latch LSB MSB LSB/MSB SELECT COUNTER SC SC CH# 2 X Part #5

6 PERIPHERAL INTERFACING Rev.. ASSEMBLY LANGUAGE PROGRAM Transmitter ADDRESS LABEL MNEMONICS OPCODE/OPERAND COMMENT 4 MVI A,36 H 3E 36 Initialization of OUT TMRCNT D3 B 44 MVI A,A H 3E A 46 OUT TMRCHO D XRA A AF 49 OUT TMRCHO D3 8 4B XRA A AF Resetting the 4C OUT UATCNT D A 4E MVI A,4 H 3E 4 4 OUT UATCNT D MVI A,4E H 3E 4E Initialization of 44 OUT UATCNT D A 46 MVI A,37 H 3E OUT UATCNT D3 5 4A LXI H,43 H 2 43 Load the input data in to transmitter memory 4D MVI C,5 H E 5 Initialize the number of input data count 4F LOOP IN UATCNT DB 5 Check 825A 42 ANI 4 H E6 4 TXEMPTY and 423 JZ LOOP CA F 4 then send the data 426 MOV A,M 7E Move the recent input data to accumulator 427 INX H 23 Increment the memory location to get the next data in to transmitter 428 OUT UATDAT D3 4 Transmit the data to receiver 42A DCR C D Decrement the input data count 42B JNZ LOOP C2 F 4 Until all data are transmitted continue looping 42E HLT 76 Stop the execution Receiver 42 MVI A,36 H 3E 36 Initialisation of OUT TMRCNT D3 B 424 MVI A,A H 3E A 426 OUT TMRCHO D XRA A AF 42A OUT TMRCHO D3 8 42B XRA A AF Resetting the 42C OUT UATCNT D A 42E MVI A,4 H 3E 4 42 OUT UATCNT D MVI A,4E H 3E 4E Initialization of 424 OUT UATCNT D A Part #6

7 PERIPHERAL INTERFACING Rev MVI A,37 H 3E OUT UATCNT D3 5 42A LXI H,44 H 2 44 Load the output data in to receiver memory 42D MVI C,5 H E 5 Initialize the number of input data count 42F LOOP IN UATCNT DB 5 Check 825A 422 ANI 2 H E6 2 RXEMPTY and 4223 JZ LOOP CA F 42 hence get the data and store the data 4226 IN UATDAT H DB 4 Receive the data from transmitter 4228 MOV M,A 77 Move the recent input data to accumulator 4229 DCR C D Decrement the receiver data count 422A INX H 23 Increment the memory location to store the transmitted data 422B JNZ LOOP C2 F 42 Until all data are received continue looping 422E HLT 76 Stop the execution EXECUTION Transmitter ADDRESS 43 H 43 H 432 H 433 H 434 H Receiver ADDRESS 44 H 44 H 442 H 443 H 444 H DATA AA H BB H CC H DD H EE H DATA AA H BB H CC H DD H EE H REFERENCE. Ramesh S.Gaonkar, Microprocessor Architecture, Programming, and Applications, Fourth Edition, Penram International Publishing (India), 2. Part #7

8 PERIPHERAL INTERFACING Rev.. 2. S.Subathra, Advanced Microprocessor Laboratory, Record work, Adhiparashakthi Engineering College, Melmaruvathur, October S.Subathra, Programming in 885 Microprocessor and its applications An Innovative Analysis, Technical Report, Adhiparashakthi Engineering College, Melmaruvathur, March Micro-85 EB, User Manual, Version 3., CAT #M85 EB-2, VI Microsystems Pvt. Ltd., Chennai. Part #8