ECG 3-lead, 5-lead, 12-lead and RESP Signal Processing ECG ASIC Part Number

Transcription

1 FEATURES ECG ASIC ECG 3-lead, 5-lead, 12-lead and RESP Signal Processing ECG ASIC Part Number lead or 5-lead ECG front end (one ASIC). 12-lead ECG front end (two ASICs). Four 8X gain differential amplifiers per ASIC. Built-in pacer pulse detector. Filtered lead-off detection for each electrode. Programmable input offset for each channel. Selectable reference electrode (5 choices). Patient range neonate through adult. Supports AAMI EC11:1991 and EC13:1992. On-chip RF filtering on all ECG inputs. Supports impedance pneumography (RESP). 6 mw typical active power, 1.4 mw sleep mode. Built-in self-test capability. Bidirectional 3.3 V/5 V serial control interface. Space-saving 0.36 sq. in. 52-pin PQFP pkg. ASIC and notes simplify and accelerate product development and qualification. 100% CMOS technology. ECG ASIC OVERVIEW The ECG ASIC is a complete front-end for 3-lead (3-electrode, up to 6-vector) or 5-lead (5-electrode, 7- vector) monitoring or diagnostic ECG systems. Two identical ECG ASIC devices can be used together to form a complete 12-lead (10-electrode, 12-vector) ECG system. The ASIC accepts low-level body surface ECG signals and amplifies and conditions those signals to directly feed an external 4-channel sigma-delta A/D converter. The A/D converter output feeds a suitable processor that performs the bandpass filtering, derivation of remaining ECG vectors, QRS-picking analysis, data transmission, display, and other functions. Copyright 2001 by Welch Allyn OEM Technologies. Welch Allyn and Protocol are registered trademarks, and Pryon is a trademark of Welch Allyn, Inc. Welch Allyn, Inc. is protected under various patents and patents pending. Welch Allyn OEM Technologies is a division of Welch Allyn, Inc. Information furnished by Welch Allyn OEM Technologies is believed to be accurate and reliable. However, no responsibility is assumed by Welch Allyn OEM Technologies for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Welch Allyn OEM Technologies. Disclaimers: This document may be wholly or partially subject to change without notice. All rights are reserved. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written permission from Welch Allyn OEM Technologies. Welch Allyn OEM Technologies 8500 SW Creekside Place, Beaverton, OR U.S.A. Phone: Fax: Rev. 2 05/ Rev. 2 Copyright 2001 Page 1

2 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies The use of a high-resolution A/D converter for each channel eliminates the need for hardware band-pass filtering, high-gain amplification, sample and holds, and trace restoration. These functions and others can be implemented in software, resulting in a simpler design of associated hardware and achieving improved performance through better matching of gain and phase, and zero time skew between channels. This virtually eliminates possible errors in any additional ECG vectors that are derived by software from the ECG vectors developed by the ASIC hardware. NOTE Welch Allyn OEM Technologies has designed the ECG ASIC in accordance with the applicable hardware requirements for this type of component for EC and EC as described on page 80 of this manual. However, it is the sole responsibility of the device manufacturer who incorporates the ECG ASIC into a host system device to demonstrate and confirm that the device complies with all regulatory, safety, and performance requirements for the device specific to intended use and the applicable market where the device is sold. TERMINOLOGY AAMI - Association for the Advancement of Medical Instrumentation. (See Related Documents, page 80.) ASIC - Application-Specific Integrated Circuit. CAUTION statement - Identification of a possible condition, event, or fault that could result in damage to the equipment or other property. ESIS - Electro-Surgical Interference Suppression. HOST SYSTEM - The medical device within which the ECG ASIC component is integrated. IMPEDANCE PNEUMOGRAPHY - A technique for detecting respiration by detecting the slight changes in electrical impedance of the chest and abdomen that occur during respiratory efforts. The technique involves injecting a psuedo constant current, high frequency (50-80 khz) carrier between body surface ECG electrodes, and monitoring the slight changes in voltage that occur between those electrodes due to impedance changes during breathing. LEADS and VECTORS - Lead is used preceeding a particular ECG vector, such as Lead II or Lead V. However, lead in common usage can mean an ECG vector, an ECG electrode, or an electrode lead wire or connection. Where using a more exact term in this manual might be confusing or would read awkwardly, the term lead is kept, but it is either used in quotes ( lead ), or its more precise meaning is shown. VN (such as V2 or V6) is used in this manual to indicate a particular unipolar chest ECG vector (according to Wilson), such as Lead V6. V N (such as V 2 or V 6 ) is used in this manual to indicate a chest electrode located at physical position N. This electrode is used to develop the Lead VN vector. R.T.I. Referred To Input. WARNING statement - Identification of a possible condition, event, or fault that could result in personal injury. Page 2 Copyright Rev. 2

3 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC SUMMARY OF CHANGES TO THIS MANUAL SINCE REVISION 1 The following information has changed or been added since Revision 1 of this manual. Description of Change Affected Pages Information is added about CMR issues while using a 3-wire ECG cable with grounded reference electrode to get 2 simultaneous ECG vectors. Explanations are added for various lead fail recovery and pacer detection anomalies observed while using certain types of patient simulators. Additional information is provided for successfully dealing with defibrillator discharges. For an overview, see page 21 of the Lead Fail Detection Function section, and all of the Possible Causes for Processor Resets, Etc., During Defibrillator Discharge section on pages 56 and 57. Additional component locations that should use physically larger packages are listed in the Component Voltage and Power Ratings section on page 59. Exclusion of neon bulb currents from the ground plane is discussed on page 73 of the Layout Considerations section. To help prevent circuit board arcovers, minimum board spacings are revised and assumptions are explained on pages 75 and 76 of the Layout Considerations section. Pages of the Reducing 60 Hz Interference section. See respectively page 21 of the Lead-Fail Detection Function section, and the Miscellaneous Causes for False Pacer Detection section on pages 28 and 29. Pages 21, 56, 57, 59, 73, 75 and 76 (see detailed references at left). A better way of optimizing the proper voltage for CLPIP in the chest-lead-present detector is added. Page 24 of the How the Chest Lead-Present Detector Works section. Polarity is fixed in the Offset Control table on page 36, and more information is added about why and Dealing With ECG Offset section on pages how to use the additional ECG offset capability. In the 5-lead ECG/respiration application schematic, a wrong Q2 connection is fixed, U2 reverts to a Page HC4053, component impedances are lowered in the synchronous demodulator, a low-noise VDDRSP supply is added and connections are defined for it, the capacitive loading on +2.5V is reduced, a clamp diode is added on CLPIN, and all neon bulbs share a single point connection to ground. In the 12-lead ECG application schematic, the capacitive loading on +2.5V is reduced, and all neon bulbs share a single point connection to ground. Circuit and power supply noise solutions are provided for noise issues in respiration, including circuit changes, and a low-noise VDDRSP supply implementation. Page 41. Respiration artifacts from non-patient sources. Pages 44 and 45. Added are ranges of respiration performance variations that have been observed with a range of different ECG cable designs. Detail is added for optimizing parts values in respiration s synchronous detector for a particular instrument and ECG cable design. Considerations are added for using a channel of the AD7716 ADC in a multiplexed application. Factors are described that affect how well an ECG cable design can tolerate defibrillator discharges. Observed limitations are added on the number of defibrillator discharges that are tolerated by neons and ECG cables. Differences in the stress levels caused by various standardized defibrillator-withstand tests are added. Board grounding issues (separate analog & digital ground planes vs a single ground plane) are discussed. All references have been removed to an ECG waveshape distortion hazard caused by actively driving signal electrode LL through an intentional RL-LL short in 3-lead cables. Analysis and experiments have confirmed that this configuration does not actually lead to signal distortion. See respectively, page 40 schematic, page 43 of the Respiration Circuit Issues section, and pages 53 and 54 of the ASIC Power Connections and Issues section. Pages of the ECG Cable Design Versus RESP Performance section. Fine Tuning RESP s Synchronous Detector section on pages 47 and 48. Page 50 of the Advantages and Disadvantages of the AD7716 section. Pages 59 and 60 of the Defibrillator Issues with ECG Cables section. Page 60 of the Defibrillator Issues with ECG Cables section. Pages of the Layout Considerations section. (Removed from Rev. 1 Manual, pages 14 and 60.) Rev. 2 Copyright 2001 Page 3

4 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies BASIC DESCRIPTION A processor is required to properly control the ASIC and perform QRS-picking, breath-picking, and other signal analysis as desired. The basic features of the ASIC are described below. ECG Portion The ASIC directly develops signals for either Lead I or Lead II (switchable), and a fixed Lead III for 3- electrode systems. The ASIC adds to these a fixed Lead V for 5-electrode systems. A pair of ASICs develops a switchable Lead I or Lead II, and fixed vectors for Lead III and Leads V1 through V6 for 10- electrode systems. Additionally, Lead II or Lead I and Leads av R, av L, and av F may be developed algebraically from each system, giving up to 6 total vectors for a 3-electrode system, 7 total vectors for a 5- electrode system, and 12 total vectors for a 10-electrode system. All ECG lead selection and differential amplification is internal, with all 4 amplifier outputs simultaneously available. When a higher than normal dc offset in the ECG electrodes is a concern, each of the 4 differential amplifiers can have its input offset range individually shifted to accommodate 500 to +100 mv, -300 to +300 mv, or 100 to +500 mv. (A higher-than-normal dc offset occurs following defibrillation, possible during body surface pacing, and while using electrodes of dissimilar materials, electrodes lacking silver/silver chloride, or stainless needle electrodes.) All differential amplifier outputs are continuous-time signals. A versatile lead (electrode) fail detection system provides connection status information for each of the 5 electrodes used with each ASIC. The detection scheme uses dc current sources, buffer amplifiers, low-pass filters, and comparators with hysteresis to detect a disconnected electrode. The low-pass filters virtually eliminate lead-fail detection problems caused by power line noise pickup. The status of each electrode is stored in a register that may be read by the serial interface. As an additional convenience, the ASIC provides a dedicated output pin that may be polled or used to generate a processor interrupt whenever there is any change in the status of any of the electrodes. The ASIC uses a unique method to distinguish between 3-lead and 5-lead ECG cables. This method works whether the cables are attached to a patient or not, and is not fooled by the RL-LL short built into many 3-lead ECG cables. To provide the maximum number of usable ECG vectors from a given number of electrodes (particularly after an electrode becomes accidentally disconnected), any one of the ASIC s 5 electrodes may be used as a reference electrode. The selected reference electrode may be either connected to the ECG power supply s common ("gnd"), or may be driven by a common mode signal obtained from any valid ECG vector. The ASIC includes a built-in pacer pulse detector which can select any one of the four amplifier outputs as its source. It detects 100 µsec-wide pacer pulses of ±3 mv to ±700 mv amplitude, and 200 µsec to 2 msecwide pacer pulses of ±2 mv to ±700 mv amplitude. A proprietary noise-adaptive detection mode may be enabled when desired. This mode dramatically improves the noise immunity of the detector by automatically raising the pacer pulse detection threshold to slightly greater than the amplitude of most repetitive, ambient electrical noise spikes. Built-in self-test circuits facilitate testing each ECG vector, the pacer detector, lead-fail detection, offset capability, and other functions under processor control. Respiration The ASIC provides all the digital circuitry required to do an optional impedance pneumography respiration monitoring system. It generates 3-level signals for driving two electrodes at a time (one fixed, the other selectable), such as RA and LA, or RA and LL. A digital phase reference signal is provided to control the switching of an external synchronous detector. Timing of all respiration signals is derived from the master clock signal provided to the ASIC. Page 4 Copyright Rev. 2

5 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC Communication Link A 4-line (CS/, DIN, DOUT, and SCLK) serial interface provides easy communication with a wide range of processors. Logic levels may be either 3.3 V or 5 V as desired. Power The ASIC operates from ±5 V analog supplies, and either a +3.3 V or +5 V digital supply. It also requires a +2.5 V reference. All ASIC bias currents are determined by the +2.5 V reference and an external resistor, which stabilizes performance over the ASIC s full operating temperature range. A power-saving sleep mode is provided which reduces ASIC power consumption to 1.4 mw typically. ECG lead-fail detection remains fully functional during this sleep mode. SPECIFICATIONS Specification values shown in bold type are 100% tested at 25 and 70 C. All other values are guaranteed by design and are not 100% tested. Specifications a Parameter ECG INPUTS (EIN1-EIN5) Input offset, normal range Input offset, shifted range Input bias current Input referred noise, Leads I, II, III Input referred noise, Lead V +Supply rejection -Supply rejection Common mode rejection, Leads I, II, III c Common mode rejection, Primary Lead V Common mode rejection, Secondary Lead V d ± Common mode input voltage range RF low-pass filter frequency Lead weighting error 0 ECG LEAD-FAIL DETECTION Lead-fail current Lead-fail current on RL (or V 2 ) Lead-fail threshold V+ e Lead-fail threshold V- Lead-fail threshold V+ Lead-fail threshold V- Low-pass filter LEAD CHANGE OUTPUT (LDCH/) Output High Voltage f Output Low Voltage Value b Units Condition/Comments Min Typ Max <±1 ±235 NA to % of V % of V ±5.0 ±250 ± ± mv mv µv p-p µv p-p db r.t.i. db r.t.i. db r.t.i. db r.t.i. db r.t.i. V khz % na na V V V V V V V V Hz V V EIN1-EIN5 all shorted to gnd and offset disabled EIN1-EIN5 all shorted to gnd and offset enabled Dominated by lead-fail detection current Hz BW, CLKIN=5.213 MHz, ESIS filter inputs grounded Hz BW, CLKIN=5.213 MHz, ESIS filter inputs grounded At 60 Hz on VDDA/VDDA1/VDDRSP At 60 Hz on VSS/VSSA At 60 Hz on EIN1-EIN3. See footnote c. At 60 Hz on EIN1-EIN5. See footnote c. At 60 Hz on Sec EIN1-EIN4, on Pri EIN1-EIN3, Pri AVG30 to Sec AVG3IN. See footnote c.; footnote d. -3 db point, each input Per AAMI EC11 section test dc, pullup on active inputs (EIN1-EIN5) dc, pullup disabled (EIN5 only) For ±300 mv offset range, bold=test limits. See footnote e. For ±300 mv offset range, bold=test limit. See footnote e. For -100/+500 mv, or -500/+100 mv range, any input, bold=test limits. See footnote e. For -100/+500 mv, or -500/+100 mv range, any input, bold=test limit. See footnote e. -3 db point, each input Iout source 0.5 ma. See footnote f. Iout sink 0.5 ma. See footnote f Rev. 2 Copyright 2001 Page 5

6 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Specifications a (Continued) ECG OUTPUTS (ECGO1-ECGO4) DC gain DC gain matching error Bandwidth (ASIC plus ESIS filter) Bandwidth (ASIC only) Output voltage swing Cross talk SLEEP CONTROL OUTPUT (ECGON) Output High Voltage Output Low Voltage ECG DRIVEN LEAD OUTPUT (LDRVO) Output voltage swing Resistance to gnd ECG COMMON MODE INPUT (AVG3IN) Input voltage range Input current ECG AVERAGE OF 3 OUTPUT (AVG30) Output voltage range Output offset Output impedance ± ±4.7 < ±1.5 < ±4.70 ± to to 4.0 <± ±1 % khz khz V mv p-p V V V kω V na Including internal average of RA, LA, and LL Worst case of all 4 outputs Small signal using filter in 5-lead schematic (page 40) Small signal 60 kω to gnd In any enabled x8 output (ECG01-ECG04) when any single input (EIN1-EIN5, AVG3IN), which should not affect that output, is a 600 mv p-p 1 khz sine wave, and all other inputs = 0 V. Iout source 0.5 ma Iout sink 0.5 ma ECG COMMON MODE OUTPUT (CMOUT) Output voltage range -2.0 to 4.0 V Not loaded ECG CHEST LEAD DETECTOR Input offset Input current Common mode input range CLPCLK output high voltage CLPCLK output low voltage Detection threshold CLPCLK frequency ECG PACER DETECTOR (+PDETO) Max detection threshold Min detection threshold 100 µsec pulses 200 µsec to 2 msec pulses 100 µsec pulses 200 µsec to 2 msec pulses Input current PDETO output high voltage PDETO output low voltage PDETO pulse duration PDETO delay from input pulse s leading edge ECG SELF-TEST VTST voltage PDTST voltage PDTST width Parameter ± ± Value b Units Condition/Comments Min Typ Max ±5 <± to ±2.8 ±1.8 ±0.5 ± ± ±20 ±20 ± ±3 ±2 ± V mv kω mv na V V V pf total khz mv mv mv mv mv na V V msec msec ±134 mv mv µsec (Reference Electrode Driver) 100 kω load to (virtual) gnd on LDRVO LDRVO to gnd when LDROFF = HI Not loaded EIN1-EIN3 shorted to gnd, all modes but 12 lead sec. Except high Z in 12-lead secondary mode CLPIN - CLPIP CLPIN and CLPIP CLPIN and CLPIP Iout source 0.5 ma Iout sink 0.5 ma With circuit in 5-lead schematic (page 40) CLKIN 160, 50% duty factor 100 µsec to 2 msec pulses, all modes Non-adaptive and adaptive with min threshold Non-adaptive and adaptive with min threshold Adaptive with noise-limited threshold Adaptive with noise-limited threshold PDFB, PDCAP (checked indirectly) Iout source 0.5 ma Iout sink 0.5 ma CLKIN periods For 2 mv, 200 µsec pulses. Others are faster. TSTON HI, sign determined by SIGN TSTON HI, PDTST HI Min required for effective ±testing, determined by speed of writing to serial interface (user-controlled). Page 6 Copyright Rev. 2

7 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC Specifications a (Continued) Parameter RESP OUTPUTS (RSPORA, RSPOLA, RSPOLL) Output high voltage Output mid voltage from RSPMID Output low voltage Output frequency RESP Φ REF OUTPUT (RSPREF) Output high voltage Output low voltage Phase shift Output frequency RESP PWR DN OUTPUT (RSPOFF) Output high voltage Output low voltage CLKIN INPUT (Schmitt Trigger) Input frequency CLK LO time CLK HI time Schmitt trigger VT+ Schmitt trigger VT- Input capacitance Input current GENERAL PURPOSE OUTPUTS (GPO1-GPO4) Output high voltage Output low voltage TEST INPUT (HWTST) Input high voltage g Input low voltage Input pulldown to gnd Pulse width VOLTAGE REFERENCE INPUT (VREF) Voltage range Input current Input current ± ± <3 Value b Units Condition/Comments Min Typ Max ± V V V khz V V degrees khz V V MHz nsec nsec V V pf na V V V V na µsec V µa µa Iout source 0.5 ma Iout 0.5 ma ( due entirely to Iout) Iout sink 0.5 ma CLKIN 80 Iout source 0.1 ma Iout sink 0.1 ma Delayed from RSPORA s 0 to 2.5 V transition CLKIN 80, 50% duty factor Iout source 0.5 ma Iout sink 0.5 ma See discussion of CLKIN frequency on page 31. Tested with 5.2 MHz square wave Tested with 5.2 MHz square wave (Powered by VDDRSP and RSPGND) Iout source 0.5 ma Iout sink 0.5 ma See footnote g. See footnote g. current sink See Voltage Reference Issues section (page 31). While any offset and/or self-test voltage is enabled. For all other conditions Rev. 2 Copyright 2001 Page 7

8 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Specifications a (Continued) Parameter POWER REQUIREMENTS CASE #1 +5 V supply current (+offsets) -5 V supply current (+offsets) +5 V supply current (-offsets) -5 V supply current (-offsets) +3.3 V supply current CASE #2 +5 V supply current -5 V supply current +3.3 V supply current CASE #3 +5 V supply current -5 V supply current +3.3 V supply current RSPMID current CASE #4 +5 V supply current -5 V supply current +3.3 V supply current CASE #5 +5 V supply current -5 V supply current +3.3 V supply current SERIAL INTERFACE Input high voltage Input low voltage Input pullup to 3.3 V DOUT high voltage DOUT low voltage Input and output capacitance SCLK TIMING SCLK T high (t6) SCLK T low (t4) SCLK frequency SCLK rise time WRITE CYCLE TIMING CS/ setup time (t1) DIN setup time (t2) DIN hold time (t3) CS/ hold time (t7) READ CYCLE TIMING CS/ setup time (t1) DIN setup time (t2) DIN hold time (t3) DOUT delay time (t5) DOUT relinquish time from CS/ (t8) CS/ hold time (t7) Value b Units Condition/Comments Min Typ Max < < <3 < < < µa µa µa µa µa µa µa µa µa µa µa µa µa µa µa µa µa µa V V na V V pf nsec nsec khz nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec See also Sleep Mode Issues section (page 52) CLKIN, ECGO1-ECGO4 (for 12-lead secondary mode), pacer detector, chest-lead-present detector, and Reference Electrode Driver all active; EIN1-EIN4 = 0 V; all 4 internal offsets enabled, RESP disabled; static serial interface (CS/, DIN, SCLK=3.3 V). (Typical 12-lead /no RESP; power same for 5-lead.) Same as Case #1, no internal offsets enabled. (Typical 5-lead with RESP.) Same as Case #2, except RESP is enabled using circuits in 5-lead schematic (page 40). Currents listed are for ASIC only. (Theoretically = 0 if RSPMID=VDDRSP/2) (Sleep mode.) ECG differential amps, pacer detector, chest-lead-present detector, Reference Electrode Driver, and RESP all off; CLKIN at 5V or 0V, serial interface static (CS/, DIN, SCLK = 3.3V), internal leadfail oscillator on. Increase in supply currents due to active serial interface, SCLK = 500 khz, alternating 1 s and 0 s on DIN, CS/ = 0 V for 15 SCLKs, 3.3V for 1 SCLK. (CS/, SCLK, DIN). See footnote g. (CS/, SCLK, DIN). See footnote g. (CS/, SCLK, DIN) current source Iout source 0.5 ma. See footnote f. Iout sink 0.5 ma. See footnote f. 20 pf load. a. VDDA = VDDA1 = VDDRSP = +5.0 V; VSS = VSSA = -5.0 V; VDDIO = +3.3 V; VREF = RSPMID = V; AGND1 = AGND2 = DGND = RSPGND = 0 V; CLKIN = MHz; RBIAS = 1 MΩ ±1% to V; outputs not loaded unless otherwise specified. b. Min and Max values apply over the full operating range of 0-70 C. Typical values apply at 25 C only. Bold specifications are 100% tested. Other specifications are guaranteed by design but are not 100% tested. c. The CMR tests of reference documents EC11 and EC13 give much better results than this because they take advantage of the ECG channel s required isolation. Page 8 Copyright Rev. 2

9 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC d. Proper CMR of the ASIC in 12-lead secondary mode requires the inherent delay in the primary chip s AVG30 path. e. Settling time issues during automated testing preclude more precise testing of these specifications. However, the test limits do guarantee satisfactory operation. f. Output range = GND - VDDIO. If VDDIO = +5.0 V, then logic HI = 5.0 V; output drive capability then matches output PDETO s. (Speed is not increased as limited by internal logic circuits.) g. Input range = GND-VDDIO. (If VDDIO = +5.0V, then logic HI = 5.0V. Input level characteristics then are VIL = to 1.50 V, VIH = 3.60 to 5.30 V. (Speed is not increased as limited by internal logic circuits.) Recommended Operating Conditions Parameter Minimum Maximum VDDA, VDDA1, VDDRSP 4.5 V 5.5 V VDDIO 3.0 V 5.5 V VSS, VSSA -4.5 V -5.5 V VREF V V CLKIN frequency 5.0 MHz 5.4 MHz Bias setting resistor (RBIAS to VREF) 0.99 MΩ 1.01 MΩ Operating Ambient Temperature 0 C 70 C Absolute Maximum Ratings a Parameter Minimum Maximum VDDA to GND -0.3V +6V VDDA1 to VDDA -0.1V +0.1V VDDRSP, RSPMID to GND -0.3V VDDA+0.3V VDDIO to GND -0.3V VDDA+0.3V VREF to GND -0.3V VDDA+0.3V VSSA to GND -6V +0.3V VSSA to VSS -0.3V +0.3V GND to any other GND -0.1V +0.1V Any input except CS/, DIN, SCLK, HWTST to GND VSSA-0.3V VDDA+0.3V Inputs CS/, DIN, SCLK, HWTST to GND -0.3 V VDDIO V Storage Temperature -25 C 125 C Soldering Temperature, 40 seconds maximum 220 C a. Operation outside these maximum ratings can affect the reliability of the ASIC Rev. 2 Copyright 2001 Page 9

10 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies The ASIC incorporates internal protection circuits that prevent latchup for currents up to 100 ma as tested under EIA/JEDEC Standard EIA/JESD78. Extra care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. After the ASIC is installed into a complete board, the ESD tolerance of the ECG system is determined almost entirely by devices external to the ASIC. A. WRITE OPERATION (See serial interface specifications for timing definitions.) SCLK t1 t4 t6 t7 CS/ t2 t3 REGISTER UPDATE OCCURS DIN I2 I1 I0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DOUT HIGH Z B. READ OPERATION (See serial interface specifications for timing definitions.) SCLK t1 t4 t6 t7 CS/ DIN t2 t3 I2 I1 I0 A4 A3 A2 A1 A0 t8 t5 DOUT HIGH Z D7 D6 D5 D4 D3 D2 D1 D0 Write and Read Operation Timing Diagrams Page 10 Copyright Rev. 2

11 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC TIME (PERIODS OF CLKIN) A. OUTPUT RSPORA VDDRSP RSPMID RSPGND 80 B. OUTPUTS RSPOLA/RSPOLL VDDRSP RSPMID RSPGND 80 C. OUTPUT RSPREF VDDRSP RSPGND RESP Circuit Timing Diagrams PIN CONFIGURATION PDFB PDCMPIN PDCAP CLPCLK VDDRSP RSPGND RSPMID RSPOLL RSPOLA RSPORA RSPREF DGND VSS PDETO 40 LDCH/ 41 CLPIN 42 CLPIP 43 VDDA1 44 VDDA 45 VSSA 46 AVG3O 47 VREF 48 ECGO4 49 ECGO3 50 ECGO2 51 ECGO1 52 PIN 1 INDICATOR AGND2 AGND1 EIN5 EIN4 EIN3 EIN2 EIN1 AVG3IN CMOUT LDRVI LDRVO RBIAS N/C 26 GPO4 25 GPO3 24 GPO2 23 GPO1 22 CLKIN 21 DIN 20 SCLK 19 DOUT 18 VDDIO 17 CS/ 16 HWTST 15 ECGON 14 RSPOFF Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment, and can discharge without detection. Although this device features ESD (Electrostatic Discharge) protection circuitry, permanent damage may still occur on this device if it is subjected to highenergy electrostatic discharges. Therefore, proper ESD precautions must be used to help avoid performance degradation or loss of functionality. ECG ASIC Pin Configuration Rev. 2 Copyright 2001 Page 11

12 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Pin Descriptions PIN NAME I/O TYPE FUNCTION 1 AGND2 Ground Analog ground used for all switched capacitor circuits (0 V nominal) 2 AGND1 Ground Analog ground used for all continuous-time circuits (0 V nominal) 3 EIN5 Analog I/O ECG electrode input 5 (also can be driven lead output) 4 EIN4 Analog I/O ECG electrode input 4 (also can be driven lead output) 5 EIN3 Analog I/O ECG electrode input 3 (also can be driven lead output) 6 EIN2 Analog I/O ECG electrode input 2 (also can be driven lead output) 7 EIN1 Analog I/O ECG electrode input 1 (also can be driven lead output) 8 AVG3IN Analog In Average of RA, LA, LL input (from Primary ASIC in a 12-lead system) 9 CMOUT Analog Out Buffered common-mode output (for lead-drive circuit) 10 LDRVI Analog In Inverting input to lead-drive op amp 11 LDRVO Analog Out Output of lead-drive op amp 12 RBIAS Analog In Virtual ground input for external bias resistor (1 Megohm to VREF) 13 N/C ---- Not used. Make no connection to this pin. 14 RSPOFF Digital Out External respiration disable control (0 V, VDDA logic levels) 15 ECGON Digital Out External ECG enable control (VSSA, 0 V logic levels) 16 HWTST Digital In Hardware test control input (0V, VDDIO logic levels, pull-down to 0 V) 17 CS/ Digital In ASIC select I/O input (0V,VDDIO logic levels, LOW True, pull-up to VDDIO) 18 VDDIO Power Positive digital power pin for serial I/O (+3.3 V nominal) 19 DOUT Digital Out Serial data output for I/O (Tristate 0V, VDDIO logic levels) 20 SCLK Digital In Serial clock input for I/O (0 V, VDDIO logic levels, pull-up to VDDIO) 21 DIN Digital In Serial data input for I/O (0 V, VDDIO logic levels, pull-up to VDDIO) 22 CLKIN Analog In External MHz clock input (Schmitt trigger input) 23 GPO1 Digital Out General purpose output bit (0V, VDDRSP logic levels) 24 GPO2 Digital Out General purpose output bit (0V, VDDRSP logic levels) 25 GPO3 Digital Out General purpose output bit (0V, VDDRSP logic levels) 26 GPO4 Digital Out General purpose output bit (0V, VDDRSP logic levels) 27 VSS Power Digital VSS (-5 V nominal) 28 DGND Ground Digital ground (0 V nominal) 29 RSPREF Digital Out Respiration carrier phase reference output (0 V, VDDRSP levels) 30 RSPORA Analog Out Respiration drive output for right arm (0 V, RSPMID, VDDRSP levels) 31 RSPOLA Analog Out Respiration drive output for left arm (0 V, RSPMID, VDDRSP levels) 32 RSPOLL Analog Out Respiration drive output for left leg (0 V, RSPMID, VDDRSP levels) 33 RSPMID Pseudo Power Respiration drive mid-level voltage reference input (+2.5 V nominal). See ASIC Power Connections for details (page 53). 34 RSPGND Ground Ground reference for respiration circuits (0 V nominal) 35 VDDRSP Power Positive power for respiration circuits (+5 V nominal). Must have very low noise. 36 CLPCLK Digital Out Chest-lead-present detector reference output signal (0 V,VDDRSP levels) 37 PDCAP Analog I/O Adaptive pacer detector external filter capacitor connection 38 PDCMPIN Analog In Adaptive pacer detector comparator input. 39 PDFB Analog In Adaptive pacer detector feedback input 40 PDETO Digital Out Adaptive pacer detector output (0 V, VDDA logic levels, HIGH True) 41 LDCH/ Digital Out Lead-Fail (electrode connection) status change output (0 V, VDDIO logic levels, LOW True) Page 12 Copyright Rev. 2

13 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC Pin Descriptions (Continued) PIN NAME I/O TYPE FUNCTION 42 CLPIN Analog In Chest-lead-present detector negative comparator input (sense signal) 43 CLPIP Analog In Chest-lead-present detector positive comparator input (dc reference) 44 VDDA1 Power Analog VDD used for all switched capacitor circuits (+5 V nominal) 45 VDDA Power Analog VDD used for all ECG continuous time circuits (+5 V nominal) 46 VSSA Power Analog VSS (-5 V nominal) 47 AVG3O Analog Out Buffered average of RA, LA, LL 3 kohm output (to Secondary ASIC in a 12-lead system) 48 VREF Analog In DC voltage reference input (+2.5 V nominal) 49 ECGO4 Analog Out ECG amplifier output 4 50 ECGO3 Analog Out ECG amplifier output 3 51 ECGO2 Analog Out ECG amplifier output 2 52 ECGO1 Analog Out ECG amplifier output 1 ECG ASIC BLOCK DIAGRAM ECG ASIC Block Diagram Rev. 2 Copyright 2001 Page 13

14 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies DETAILED DESCRIPTION This section describes the function of the ASIC sub-circuits, guidelines on how each sub-circuit should be used, and design considerations and tradeoffs involved in possible applications. Sample schematics on page 40 and page 41 provide detailed information regarding connections for 5-lead ECG, 12-lead ECG, and respiration system applications. These schematics show examples of the use or non-use of the circuits for sleep mode hardware shutdown, chest- lead -present detector, pacer detector, and two types of ECG input filters. Applications information about the schematics follow the schematics. ECG Amplifiers The ASIC has five ECG inputs (EIN1-EIN5) and four outputs (ECGO1-ECGO4). Each input is connected to a simple on-chip passive low-pass filter to reduce the effects of high-frequency noise and interference. Analog multiplexers are used to select the desired combination of inputs to be processed in various modes of operation. The outputs are generated by four instrumentation amplifiers, each having a fixed gain of 8. The entire signal path is dc-coupled from input to output. In a 5-lead application, the five inputs correspond to Right Arm (RA), Left Arm (LA), Left Leg (LL), Chest (V) and Right Leg (RL) electrodes. An averaging block derives the common-mode value (RA+LA+LL)/3 required to process the Lead V vector. The instrumentation amplifiers then generate the three appropriate output vectors for leads I (or II, switchable), III, and V. The fourth output (ECGO4) is not used in this mode and the corresponding amplifier is powered down. In 3-lead applications, the V connection to the patient is not used. The RL connection may or may not be used as described below. The circuits for ECGO3, ECGO4, and the averaging of RA, LA, and LL are disabled. For a 3 or 5-electrode system, all six vectors which are determined solely by electrodes RA, LA, and LL can be derived from any two of Leads I, II, and III (see the Derived ECG Vectors subsection of the Applications Information section, page 61). If both of these two vectors were permanently selected, a fault condition of the LL electrode that is shared by those two vectors could prevent all ECG monitoring. This is true even while having good connections to the remaining two electrodes. To guarantee monitoring capability of the vector defined by any remaining two of these three electrodes, the ASIC s ECGO1 channel was made selectable between Leads I and II. (Loss of any of these 3 electrodes naturally prevents monitoring of any Lead V vector; the ability to monitor with just two electrodes requires the use of a cable with an internal RL-LL short; one of the two electrodes must be LL.) In 12-lead (10-electrode) applications, two identical ASICs are used. The inputs and outputs of the first (Primary) ASIC are the same as the 5-lead case, except that input RL is replaced by input from the second chest electrode V 2 and a fourth output vector, Lead V2 is generated. Also, the common mode value (RA+LA+LL)/3 is made available at output AVG3O of the Primary ASIC. The second (Secondary) ASIC is connected to the four remaining chest electrodes (V 3 -V 6 ) and to lead RL. It generates the four corresponding output vectors Leads V3-V6. Here the common-mode value (RA+LA+LL)/3 required for the driven lead is obtained through pin AVG3IN connected externally to output AVG3O of the Primary ASIC. The instrumentation amplifiers amplify the difference between two selected electrodes (or between a selected electrode and a selected average of other electrodes), while rejecting the common-mode signal as much as possible and maintaining high signal-to-noise (S/N) ratio. The amplifiers provide a constant, well-defined gain in the bandwidth of interest. The amplifiers also have a programmable offset capability, resulting in a wider overall input dynamic range. Two bits are used to control the presence or absence of this offset and its polarity when enabled. The nominal input-referred offset can be set to 0V, -230 mv, or +230 mv using this approach. (A ±230 mv nominal offset is used instead of ±200 mv so that even with device fabrication tolerances, the ASIC can still accommodate up to ±500 mv input offsets. The indicated ranges are based on an A/D input voltage range of ±2.5 volts.) Page 14 Copyright Rev. 2

15 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC The offset capability will not often be used by the majority of the expected users of this ASIC, since the AD7716 A/D can handle with no discontinuities the entire ±300 mv range required by AAMI, etc. The offset feature is included for those users that might, at least occasionally, need to tolerate offsets greater than ±300 mv. Two conditions that might benefit from use of the ASIC s offset capability are sustained offset caused by cardiac pacing from (external) body surface electrodes, and the offset transient that follows defibrillation. In the case of a defibrillator discharge transient, having an increased offset range can allow an earlier look at the patient s ECG to see if the defibrillation or cardioversion was successful. Both of these situations can be an issue, even while using silver/silver chloride electrodes. (See Dealing With ECG Offset, page 61.) Offset conditions which likely will not benefit sufficiently from the ASIC s offset capability occur when electrode types that are not silver/silver chloride are used. (See Electrode Offsets Versus Electrode Type, page 19.) The lead fail detection thresholds of all electrodes used by an ASIC are increased while any single ECG offset in that ASIC is enabled because a 500 mv electrode offset might otherwise exceed the (480 mv) lead fail detection threshold all by itself (particularly if a grounded reference electrode is used). The various modes of operation and appropriate input lead selections are set through the serial interface. Reference Electrode Drive Circuit and Issues (Note that the Self Test Diagram on page 64 is helpful for study of the Reference Electrode Drive circuitry below.) The Reference Electrode Drive ( lead-drive ) Circuit establishes a common mode reference point for the ASIC s differential amplifiers and for its lead-fail detection circuits. It also acts as a current sink for the other electrodes lead-fail detection currents. Without that current-sinking action, all the signal electrodes would be indicated as faulted, even if they were all connected to the patient. Any electrode that is attached to the patient may be selected as a reference electrode. Control bits LD1OR2, LDR0, and LDR1 select this electrode. When the Reference Electrode Driver is connected to an electrode, that electrode may either be actively driven by an amplified, inverted, common mode average of the voltages present on a selected choice of signal electrodes, or it may be grounded. Via control bits LDIN0 and LDIN1, an input multiplexer selects the appropriate common mode input from the available values CM1OR2, CM3, and AVG3, as described later in the discussion of the LDR control register. In 3-lead, 5-lead, and in the Primary chip in 12-lead systems, CM1OR2 = (LA+RA)/2 if the LD1OR2 bit in the LDR register is LO, or (LL+RA)/2 if that bit is HI, and CM3 = (LL+LA)/2. In 5-lead, and in the Primary chip in 12-lead systems, AVG3 = (RA+LA+LL)/3. (In 12-lead applications, the Secondary ASIC receives its AVG3 input from the Primary ASIC.) The selected common-mode input is buffered by an internal operational amplifier. The result is made available at the CMOUT output pin for connection to external passive components which, together with a second internal op amp, set the loop gain and compensation time-constants for the reference electrode feedback loop. Placing the components required for this outside the ASIC allows freedom to modify the time-constants and/or loop gain needed in a variety of user applications. Reference Electrode Disconnect, Active Drive, or Grounding Since in a "12-lead" system all electrode connections to its Primary chip are for signal inputs, it is necessary to disconnect the Primary chip s Reference Electrode Driver from all the Primary chip s electrode inputs. This is done by setting that chip s control bit LDOPN = 1. In general, while a chip s LDOPN = 0, its Reference Electrode Driver is connected to the selected reference electrode, which will be driven in response to the selected common mode source if control bit LDROFF = 0, or that reference electrode will be grounded if LDROFF = 1. LDROFF being HI disables the Reference Electrode Driver and CMOUT amplifier, thus saving a small amount of power. It is appropriate to use this mode while putting the chip in its sleep mode, so that the lead fail detection system (which cannot be disabled) will still function, but will take only minimum power Rev. 2 Copyright 2001 Page 15

16 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies In the 12-lead schematic (page 41), both ASICs are shown with fully functional reference electrode drive circuits so that any electrode may be selected as the reference electrode. For 12-lead -only operation where only RL (or V 3 -V 6 ) would ever be the choice for the reference electrode, R14, R15, R17, and C22 may be removed. In this case, short together pins 10 and 11 of U1, and leave pin 9 unconnected. The negative feedback employed by a driven reference electrode scheme gives better dc common mode rejection than a grounded scheme. It forces to zero (from the perspective of the differential amplifiers) the average of the voltages on the signal electrodes used by the selected common mode source. A driven reference electrode scheme also eliminates any problems of excess offset developed by the reference electrode itself with respect to the patient. In circumstances where electrode offsets are high, both offset benefits could prevent a false lead-fail indication, since the lead-fail detection thresholds are relative to ground. For these reasons, it is preferable to actively drive the reference electrode, as opposed to grounding it. In most cases, this results in the following design scheme: Actively drive RL if RL is truly a separate electrode and it is connected to the patient. If there is no RL, but there is a V electrode and it s connected to the patient, then actively drive V. In either case, use AVG3 as the common mode source. Reducing 60 Hz Interference Besides being required to make the lead fail detection system work correctly, and (if used for active drive) to center electrode offsets, the reference electrode serves to significantly reduce the amount of 60 Hz interference in the ASIC s ECG outputs. Most 60 Hz noise in a patient s vicinity is of a common mode nature. However, due to various imbalances in the ECG system s differential amplifiers and their input circuits, a small portion of that common mode interference gets converted to a differential signal. However, the biggest contributor to imbalances is often the differences in contact impedance of the individual ECG electrodes, and the fact that those impedances must drive the non-infinite impedance of ECG input filters and differential amplifiers. If the magnitude of 60 Hz difference between the electrodes and the ECG circuits supply common ("isolated ground") can be reduced, then from the differential amplifiers perspective, their 60 Hz common mode voltage is reduced. By reducing the common mode 60 Hz content, a reduced magnitude of it will be converted to differential interference. Generally, the best way to reduce the 60 Hz voltage difference between the electrodes and the ECG circuits supply common is to provide a low impedance path between the ECG circuits supply common and the patient. (In terms of order of magnitude, such a connection drops the voltage in question from volts to tens of mv.) For best results, this should be done through an additional electrode connection to the patient an electrode connection that is not also used for a signal connection. To explore the reasons for the previous sentence requires examining the pertinent parts of the test circuit that is used for Section of EC13 and other standards CMR testing. For the sake of discussion, assume initially that the LL electrode is used as a "grounded" reference electrode. See the following figure. NOTE: The CMR test defined by EC13 is specifically defined as being done with all electrode inputs tied to the test circuit. In the case of a 5 (or more) electrode system, the RL reference-only electrode will be connected, and the following discussion does not apply. What it does apply to is the use of 3-electrode ECG cables in systems that must generate more than one ECG vector at once. The dominant current path to earth ground from the CMR test fixture s 10 VRMS/200 pf 60 Hz source is through the R3/C3 parallel network, to iso supply common through the ASIC s reference "grounding" impedance "Rgnd", and lastly through the monitor s isolation capacitance "Ciso" to earth. So long as Rgnd is much lower than the shunt impedances to iso common provided by the ECG cable s wire-to-shield capacitance and by the capacitors in the ESIS filters, and much lower than the series impedances of Cin and Ciso, this relationship is fundamentally independent of the shielding of the ECG cable per se, and of the ECG circuits. In EC13 s test setup, the only variable even remotely under the control of the circuit designer is the ECG circuits isolation capacitance to earth. Reducing the latter is accomplished in part by reducing the total volume and surface area of the ECG circuits, and including the largest possible iso barrier space around them. Page 16 Copyright Rev. 2

17 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC Common Mode Rejection Line-operated monitors must use power supply transformers and optoisolators with the lowest possible capacitances across their patient isolation barriers. Battery-operated portable monitors must be surrounded by the thickest tolerable enclosure of material having the lowest dielectric constant one can find. For isolation capacitances to earth of 50, 100, and 200 pf, the voltages dropped across the R3/C3 network are respectively about 15.4, 25.7, and 38.5 mv peak-peak. Certainly, all of these are manageable net common mode voltages for Lead I s differential amplifier. (Without going into further detail, actively driving LL instead of grounding it will lower these voltages with respect to iso common by a factor of roughly two.) Now consider trying to use LL to develop a Lead III signal. The isolation capacitance must drop below 2.6 pf to keep the 60 Hz voltage drop across R3/C3 below 1 mv peak-peak. 1 mv peak-peak is the upper limit for input-referred 60 Hz content allowed by EC13. Note that some additional margin is required for the less-than-perfect common mode rejection of real differential amplifiers. No practical circuit of this configuration with LL grounded will pass EC13 s CMR test except in Lead I. (Nor does it need to, as described in the previous note.) Note that in the above example, if LL were "grounded" at the node between LL s ESIS filter and the Lead III differential amplifier s LL input instead of at the LL electrode, the 60 Hz voltage drop between the right hand side of Cin and the LL amplifier input would be much greater than the numbers listed above. This is because the series impedance of LL s ESIS filter is then added to the net impedance of R3/C3, and the voltage drop in LL s ESIS filter contributes to the net voltage difference between LL and either RA or LA. Alternatively in a 3-wire AAMI ECG cable, the LL electrode may be grounded through the cable s RL-LL short plus the series impedance of RL s ESIS filter. In the latter case, the added voltage drop contributes to an increase in the common mode voltage seen by all differential amplifier inputs, but does not significantly increase the differential voltage between any of them Rev. 2 Copyright 2001 Page 17

18 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Hypothetically, if instead of being driven or grounded, the RL-LL short were to be (externally) tied to a suitably large resistor to a minus supply so that all electrodes were held at nearly ground potential, the 60 Hz interference currents from the CMR fixture would be more equally divided among the CMR fixture s networks for RA, LA, and LL. In such a design, the largest portions of the 60 Hz interference currents would flow through the wire-to-shield capacitances of the ECG cable, and progressively less current would flow through the capacitors of the ESIS filters and resistor to minus supply. Because the total interference current would then be more equally subdivided, this would yield lower 60 Hz content across any individual electrode network in the CMR fixture. As a result, 60 Hz content in each ECG output during the CMR tests would also be lower, but results would still greatly exceed EC13 s CMR test limit. Note also that part of the CMR test requires selective shorting of each electrode network (like R3/C3) in the CMR fixture, to cause deliberate imbalanced conditions. Even if all the ASIC s lead fail detection currents were able to be disabled, lead fail detection was dispensed with entirely, and no reference electrode connection was made at all, EC13 s CMR test would fail. Furthermore, no presently-existing ECG performance standard includes an ESIS test method or requirement, but ESIS performance for all vectors but Lead I will suffer considerably if an RL-LL short is used to provide a reference connection. To obtain good EC13 CMR test results (or for that matter, good ESIS performance) with a 3-wire cable requires restricting the available ECG outputs to just one vector - namely Lead I, Lead II, or Lead III - and forcing the reference electrode in each case to be the one electrode not used in the desired single vector. Best results will be obtained if that reference electrode is driven rather than grounded. All this must be clearly understood for best design results. Having stated all this, it is next appropriate to explore why a designer may choose to use a reference electrode connection through a 3-wire cable s RL-LL short, despite the problems it causes. 1. Many monitoring applications can benefit from being able to obtain or derive a total of 6 ECG vectors from 3 electrodes instead of just one vector. 2. Recall that the ASIC s differential amplifiers have a gain of 8, and the specified A/D used to digitize those amplified signals has a +/- 2.5 V dynamic input. Thus, the system hardware theoretically has sufficient dynamic range to handle up to 26 mv peak-peak 60 Hz signals on top of +/- 300 mv dc offset during the EC13 CMR test. (If the gain of the ASIC or A/D is slightly high, this range is reduced slightly.) If the software that deals with the ECG signals (including the software notch filters) is properly designed so that it cannot saturate or roll over, then the entire system can truly deal with large interference signals. If no part of the system saturates, the system should be able to remove enough 60 Hz to be left with usable signals. Some telemetry systems do just this when using 3-wire cables. 3. Ambulatory ECG monitoring, whether or not its ECG data is transmitted or stored for later usage, brings up the third item. ANSI AAMI EC38:1998 is the standard for ambulatory electrocardiographs. While EC38 and EC13 (and EC11) all use basically the same fixture design for their respective CMR tests, EC38 s CMR performance requirement is "at least 60 db rejection at line frequency and at least 45 db rejection at twice line frequency, both tested with any notch filters enabled". The CMR requirements of EC13 and EC11 amount to at least 89 db rejection at line frequency only, and use of notch filters during the testing is not discussed. (Note that the upcoming revision of EC13 is expected to include a requirement to disable any notch filtering during EC13 s CMR tests.) Finally, note that ambulatory devices spend most of their operating time in a pouch that has very good capacitive coupling to the patient, and very minimal capacitive coupling to earth ground. It is outside the scope of this manual to declare whether or not the above rationale is acceptable from a regulatory perspective. However, if this approach is taken with a system that never uses more than three electrodes, but which uses two ASIC outputs simultaneously, it seems reasonable to expect that such a unit s specifications need to disclose its real CMR performance and how that compares with EC38 s CMR test requirements, and include the rationale behind choosing to do so. Alternatively, a manufacturer may need to restrict the device to use with 5-wire cables, or to provide only one selectable vector when used with 3-wire cables. (Note that using a 5-wire cable with only RA, LA, and LL connected inherently forces the latter restriction.) Page 18 Copyright Rev. 2

19 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC Limitations in 60 Hz Reduction For best reduction of 60 Hz common mode interference, a reference electrode driver needs to apply 60 Hz to the reference electrode with a phase exactly opposite to that of the phase of the 60 Hz present on the patient. The patient s 60 Hz driving through the electrode impedances into the patient cable s capacitances introduces some phase shift in the common mode signal obtained from the ASIC s differential amplifiers and used to feed the driving amplifier. The ESIS filters add a little more phase shift to that incoming common mode signal. On its way back to the patient, the signal intended to drive the reference electrode picks up further phase shift as it goes back through an ESIS filter, and still more due to the low pass filtering action of the ESIS filter s resistance feeding the cable s capacitance. Finally, in order to stabilize the reference-electrode-driving amplifier, the latter must have some high-frequency rolloff of its own. This further slows down the loop response back through the reference electrode. All of these phase shifts between the interfering 60 Hz and the 60 Hz applied to the driven electrode somewhat limit how much common mode rejection benefit a driven reference scheme offers over a grounded reference scheme. (The 60 Hz software notch filter that is almost always present in modern ECG systems should have little difficulty dealing with the remaining 60 Hz with either reference electrode scheme. In tests with circuits like those in the 5-lead application schematics with the notch filter off, using typical patient cables and always with RL as the reference electrode, the driven scheme improved the 60 Hz common mode rejection by about 2 to 2.5:1 over a grounded scheme. Comparisons with other implementations may vary.) Electrode Offsets Versus Electrode Type With present-day silver/silver chloride electrodes, electrode offsets are usually low enough that they are in little danger of exceeding either the maximum allowable dc input offset specifications or the lead fail detection threshold. However, neonatal ECG monitoring applications sometimes use sets of stainless steel needle electrodes, whose offsets are not only high, but which often drift quite erratically. Also, 12 Lead ECG monitoring is sometimes done with suction cup electrodes (which usually have a rubber squeeze bulb attached to a silver-plated brass hemispherical cup). After their silver plating wears off, these brass cup electrodes can have large offsets. It is noteworthy that EC13 Section , Part (d) requires "a clear warning that electrodes of dissimilar metals should not be used unless the cardiac monitor can handle polarization potentials as high as 1 volt". Offsets from any of these electrode types may be high enough to cause false lead fail indications, despite use of the ASIC s offset capabilities, particularly with a grounded reference electrode. (Note that regardless of which reference electrode scheme is used, the reference electrode s dc offset with respect to the patient will likely be larger than the offsets of the signal electrodes. This is because the reference electrode must sink the sum of the lead-fail detection currents of all the attached signal electrodes. The more signal electrodes that are attached, the higher the offset of the reference electrode. A driven reference electrode scheme s dc feedback eliminates any problems with this higher offset.) ECG Cable Issues This subsection applies only to 3-wire ECG cables whose instrument connector may also accept 5 (or more)-wire ECG cables. For reasons listed in the Reducing 60 Hz Interference subsection on page 16, it is advantageous to include an added short between the instrument connector s pins for RL and LL. Such cables allow two valid ECG vectors to be monitored, and from those two, four more may be derived by software. If LL, and only RA or only LA, are connected to the patient, it is still possible in this manner to monitor the single vector that uses LL and that other electrode. See the Chest-Lead-Present Detector section (page 22) for a description of how to identify this type of cable. Note that to take advantage of such an RR-LL short, the short must be in the ECG cable plug. The short cannot readily be added via a semi-conductor switch (or even a relay) on the ECG circuit board, because neither of these can withstand the high voltages present during defibrillator discharges. Yet another alternative for use with 3-signal electrodes is a 4-wire cable with RL as a dedicated reference electrode, and no RL-LL short Rev. 2 Copyright 2001 Page 19

20 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Lead-Fail Detection Function The Lead (Electrode)-Fail Detection function implemented on the ASIC includes low value (nominally 70 na) dc current sources connected to the input electrodes. If an electrode is disconnected, the current source pulls the corresponding input node towards the VDDA supply. The current source connected to input EIN5 is gated by control bit RLPUP/ which is set by software in the lead-fail control register. This allows the pull-up on RL to be disabled when a 3-lead cable is used, thereby preventing a doubling of the pull-up current on LL if the ECG cable plug pins for RL and LL are shorted together (as in the AAMI standard 3-lead ECG cable). Note that RLPUP/ must be LO (for V 2 ) for the Primary ASIC in 12-lead applications. Five identical blocks filter and measure the dc offset for each electrode and set a flag in a register if this offset exceeds a predefined value. The input section of this circuit includes a passive low-pass filter (which rejects high-frequency noise and prevents aliasing), followed by a 7 Hz first-order switched-capacitor (SC) low-pass filter which helps remove 50/60 Hz line noise. A backup oscillator is enabled by control bit LFOSC. It provides the clock required to continue operating these SC circuits when the external clock source (in this case from the external sigma-delta converter) is powered down. The output of the SC filter, predominantly a dc value, is compared with a threshold level. The resulting logic value is stored in one of five locations in a register. Note that all 5 lead-fail indication bits are always active and functional, independent of the choice of 3-lead mode, 5-lead mode, 12-lead mode, etc. The comparator used has built-in hysteresis to prevent undesired chatter, and also has an adjustable threshold. The nominal inputreferred rising threshold is set at 0.48 V when all ECG amplifiers are set in the zero offset mode. Programming any of the ECG channels with a nonzero offset automatically raises the rising threshold of all the lead-fail comparators to nominally 0.73 V. These values are for positive-going transitions in the input electrode potential. For falling transitions (high to low), the built-in hysteresis reduces each of these thresholds to approximately 84% of the value of the rising threshold. Note that all of these thresholds are relative to ground. The outputs of the lead-fail comparators are connected to a logic block which contains exclusive OR gates and latches to process the electrode connection status. The logic block generates an output LDCH/ when the status of any electrode changes. The lead-fail status latch that is included in the LFS register always reflects the current electrode conditions. Reading the LFS register via the ASIC s serial interface always causes output pin LDCH/ to go HI. Any change in the connection status of the 5 ECG electrodes will cause LDCH/ to go LO until the LFS register is read again. The LDCH/ output is held at a HI level during a read operation, thereby preventing any concurrent changes in electrode status from causing additional interrupts during this time. There are two different categories of speed requirement for the response time of the ECG lead fail detection system. One category needs fast response, but can accommodate some uncertainty. The other category needs more accurate response and can accommodate greater processing delays to achieve that better accuracy. Applications that use the ASIC to get trigger information for synchronizing an external action to each heart beat (e.g. cardiac balloon pumps, defibrillators in synchronized cardioversion mode, demand pacemakers, etc.) need to know as soon as possible when an electrode comes unhooked so they can prevent an unwanted action or reaction. This is true even if the exact status change may not settle out until a bit later. Those applications almost certainly need to react as soon as LDCH/ goes LO. If there is any problem with the actual electrode connection status, the system can ignore a few beats until it resolves the problem. The other group of applications deal with what the system should do when it loses monitoring capability and has to give an equipment alert for lead fail, or declare certain vectors invalid (hence affecting their availability as sources for pacer detection, QRS picking, common mode source, and individual electrode s availability as a reference electrode, etc.). For these circumstances, it is acceptable to have a longer interruption in the trace and data stream in exchange for elimination of stuttering in the control response if the condition is erratic for a short time. The 7 Hz low pass filters in the lead fail detectors remove all ambiguities in electrode connection status for all interferences but one defibrillator discharges. Page 20 Copyright Rev. 2

21 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC While the 7 Hz low pass filters in the lead fail detectors do an excellent job of dealing with large amounts of 50/60 Hz pickup on floating lead wires, there is still a reason to require software debounce on the lead fail status before acting upon a change in it. The issue is what happens during a defibrillator discharge. The voltages at the ASIC inputs during a defibrillator discharge WILL be high enough for a long enough time to trip the lead fail detectors (and the chest-lead-present detector as well). This behavior would occur even with a lead fail detector that contained a theoretically perfect, linear, 7 Hz low pass filter and comparator, both with infinite dynamic range. During a defibrillator discharge, the voltages at EIN1-EIN5 are rapidly pulled to (and beyond) the ±5V supply rails. For the output of a singlepole, 7 Hz low pass filter to swing from an initial voltage of zero to 0.48 V under these conditions takes less than 2.3 msec. Using the defibrillator test circuit from EC13 (and other standards) yields a discharge time constant of about 3.5 msec. Actual defibrillators may use larger capacitor values than EC13 s circuit in order to guarantee 360 joules are delivered to a low impedance patient. 40 uf has been observed. This increases the time constant to 4 msec. The IEC (the worst case) defibrillator withstand test develops a peak voltage across its 100 ohm load resistor of 4.5 kv. Assuming a real world capacitor value of 40 uf, a decay time constant of 4 msec, and a final value of 0.4 V (lead reconnection threshold) at the electrodes, this takes about 37 msec for a 10- electrode (worst case) system. However, for a driven reference electrode (at the ASIC pin itself) to drop below 0.4 V, the (~dc) gain (21.5X) of its driver must be considered as well. That consideration requires all electrodes of the selected common mode source to fall below 0.4/21.5 volts during the defib test. This takes a total of about 50 msec. To a first-order approximation, the 7 Hz lead fail low pass filters take an additional 57 msec to settle to the lead reconnection threshold. (For reference, the chest-lead-present detector settles faster than this.) Practically speaking, the system software should probably allow a minimum debounce interval of at least three to four times this 107 msec total (321 to 428 msec) due in part to the lingering voltages that are contributed by dielectric absorption effects in the defibrillator s storage capacitor (at least for the duration that the defibrillator s discharge relay is held closed). Besides its being insignificant in most applications, this additional delay should ensure that the monitor passes all defibrillator recovery tests without triggering an automatic ECG vector change in response to a "failed" electrode. On the subject of delays, note that certain patient simulators can cause a delayed (~10 sec) return of an ECG trace following reconnection of a disconnected electrode. (This is different than delayed detection of a reattached electrode.) For example, at least some models of Dynatek patient simulators have a sort of capacitive coupling of their ECG outputs, although all ECG signal outputs have a 1 Mohm resistor to RL. (Such capacitive coupling necessarily has a long time constant to be able to adequately pass ST segment information.) This arrangement allows the common mode voltage of the simulator s ECG outputs to float with respect to the common mode output voltage of the simulator s IBP outputs, etc. With these simulators, all of the connected signal electrodes will be about 70 mv above RL due to the ASIC s 70 na lead fail detection current flowing through each of the simulator s 1 Mohm resistors. Disconnecting a signal electrode will cause the voltage at that electrode to settle to the voltage of the RL electrode. Reconnecting the previously-disconnected electrode causes it to charge back up to 70 mv above RL. It is this latter charging that requires extended settling time. With these input conditions, such settling behavior will be observed whether the reference electrode is grounded or driven. This settling delay does not exist with simulators that have no ac coupling (or with a real patient) Rev. 2 Copyright 2001 Page 21

22 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Lead Fail Detection Example The ECG system cannot tell what electrodes are connected without driving (or grounding) a reference electrode of some sort the reference electrode is the only path for sinking the lead fail detection currents below the lead fail detection threshold. While it looks like no electrodes are connected, the simplest approach is to use a grounded reference scheme, enable RLPUP/ in the (or both) ASIC(s), and first try using RL as the reference electrode (for a half second to allow the lead fail detector filters to settle). If no electrodes other than RL show in the LFS registers as being connected, it cannot yet be determined whether RL is the only electrode connected or whether RL is simply one of the electrodes not connected. To differentiate, try using one of the V ("C") electrodes as a grounded reference for half a second, then read the LFS registers again. If only this V electrode shows connected, try the same approach with another V electrode and then sequentially through all the electrodes that a given cable type is defined to have. The sequence order is not particularly important. Keep doing this sequence until any electrode besides the reference electrode indicates that it is connected. (Ignore as a reason for halting the sequence any intentional shorts between RL and LL, etc. that may be built into the cable.) When any second legitimate electrode shows as being connected, any subsequently-added electrodes will inherently show up in the LFS registers without further change of choice of reference electrode. Hence, keep that particular reference electrode as the reference, and keep polling the LFS register (or wait for an interrupt from LDCH/) until enough other electrodes show up as connected to be able to generate the simplest vector the ECG system will allow (like lead I, II, or III). Alternatively, with a 10-electrode cable, the system software may choose to not do anything else until at least RA, LA, LL, RL and one of the V electrodes indicate connection. Due to normal variations in the electrode attachment sequence, there will be instances where RL is not first seen to be connected while other electrodes are connected (so one of the connected electrodes is chosen as the reference electrode). In those instances, it is important to have the ECG system continue checking to see if RL later becomes connected. If RL is later found to be connected, the system should switch over to using RL as the reference electrode so that additional ECG vectors can be obtained. As part of the ongoing self tests, software should always verify that (after debounce) the reference electrode shows up as being connected. (This applies whether the reference electrode is driven or grounded.) If the reference electrode does not show as connected within 0.5 seconds after being selected, this constitutes an equipment problem, and the user should be alerted. For ECG lead-fail detection to work during sleep mode, the selected reference electrode must be able to pull down on the signal electrodes through the patient. (Otherwise, there is nothing to pull a connected ECG input below the lead-fail detect threshold.) The Reference Electrode Driver amplifier itself cannot do this while it is disabled, but a FET is included to pull the reference electrode to ground then. Setting the LDROFF bit high in the EMD register powers down this amplifier and turns on that FET. As long as the LDOPN bit in the LDR register is not set, this path to ground is functional for the reference electrode. Depending on the application, it may be best to periodically change the choice of reference electrode to search for the first available combination of connected electrodes. While using a 3-wire cable that contains an internal connection between RL and LL, it always looks like these two "electrodes" are connected to each other, just as it does when not in sleep mode. The chest-lead present detector can sort out this connection, but not while in sleep mode. See Sleep Mode Issues (page 52) for power consumption tradeoffs of lead-fail conditions while not in sleep mode. Chest-Lead-Present Detector The remaining function in the Lead-Fail Detection section is a chest-lead-present detector. (More correctly, it detects the presence in a patient cable of a wire whose intended connection is a V or chest electrode.) It is used primarily to confirm whether the chip s RL lead-fail detection status bit (LF5) is correct. If a chest wire is present (whether it is connected to the patient or not), it is certainly in a cable that contains a distinct RL connection. Based on the answer to that question, it can then be determined if enabling the lead-fail detection current for RL will violate regulatory limits on current through an active ECG electrode (namely LL in this case). Page 22 Copyright Rev. 2

23 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC The 3-lead ECG cables that meet the requirements of AAMI ECGC 5/83 are required to contain an internal connection between LL and the pin reserved for RL in 5-lead cables that use the same style 6-pin connector. Other styles of 3-lead ECG cables also contain this internal connection. Still other 3-lead cables do not contain such an internal connection. The problem arises of how to distinguish between a 3- lead cable that has an internal RL-LL short versus a 5-lead cable that has RA, LA, LL, and RL connected to a patient, yet does not have its chest wire connected for whatever reason. In either case, the LF5 bit will show RL to be present if RA, LA, and LL are all connected to a patient (whether or not RL s lead-fail detection current is enabled) and one of RA, LA, LL, or RL is used as a reference electrode. Somehow, the system needs to know what is really connected to what. It is convenient to have the lead-fail detection current for RL be enabled so that if RL is connected after the ECG system has already chosen a reference electrode, it can still detect when RL gets connected. The system can then select RL as the reference electrode. If RL s lead-fail detection current is disabled, then while RL is unhooked, the status of LF5 is indeterminate. However, there is a regulatory issue to consider which precludes always leaving RL s lead-fail detection current enabled. As it is pointed out on page 79, the maximum allowable dc current that may be passed through an active electrode is limited (to 100 na). If RL s lead-fail detection current is enabled while a 3-lead cable with an RL-LL short is in use, LL s current becomes ~140 na with this ASIC, and is in violation of ANSI/AAMI ES1 (see related documents section). The higher current would cause the LL electrode s dc offset to rise faster and rise to higher voltages because of it. In any ECG system that can guarantee no RL-LL (or RL-to-any other electrode) short will ever occur in its cable, NONE of the chest-lead-present detection system is required at all, and RL s lead-fail detection current should always be enabled. (Be aware that companies like Fogg Systems make many varieties of adapter cables and substitute cables, so an alternative cable design might crop up after product introduction.) In any case, there is no reason to use any portion of the chest-lead-present detection circuitry in the Secondary ASIC in a 12-lead system. See the Reference Electrode Drive Circuit section on page 15 for more details about the advantages or disadvantages of grounding versus driving the reference electrode. How the Chest-Lead-Present Detector Works The chest-lead-present detector works by injecting an ac signal from CLPCLK through an external high impedance into the V (chest wire) pin of the instrument s ECG connector, and having a comparator monitor the peak voltage swing injected into the V pin. The difference in capacitive loading at the chest wire s terminal due to the presence or absence of the chest wire in an ECG cable affects the amplitude of this signal at the ECG connector. An amplitude greater than a certain threshold (set by an external reference) indicates a low capacitance, implying that a chest wire is absent. A lowered impedance may be caused by the capacitance between a chest wire and the cable shield, or by a conductive path through the patient, or both. If the peak swing at the comparator input is reduced by such loading, the comparator does not trip, and the CLP bit in the ECG lead-fail status register is high. A debounce circuit in the ASIC removes the 32 khz content that would otherwise be present in that CLP bit. The frequency of the injected ac signal is exactly half of that used by the ASIC s respiration circuits, so that the latter s synchronous detector output is totally unaffected by the signal used by the chest-lead-present detector. This is appropriate since a signal injected on the chest wire gets capacitively-coupled into the wires used by respiration, and could otherwise interfere with the detected respiration signal. Note that the CLP bit is indeterminate while CLKIN is not running, whether or not the ASIC s internal lead-fail oscillator is running. It is important to use the status of the CLP bit only at the particular instant in time when software is deciding what electrode is present to be used as a reference, rather than constantly monitoring it for changes. This is because the detector reacts quickly to peak swings above its comparator s trip threshold, and reacts slowly to peak swings that stay below its trip threshold. Under these circumstances, a single noise spike (from ESD, for example), or multiple noise spikes (from electrocautery, for example) can cause the CLP bit to falsely go low for a time (up to 30 msec or so) even when a 5-wire cable is truly connected Rev. 2 Copyright 2001 Page 23

24 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies The chest-lead-present detector must be able to distinguish between the total of the capacitive loading of the chest (V) electrode s ESIS (or simple input) filter, capacitance of the instrument s internal ECG cabling (if any), capacitance of the circuit board s ECG connector, and other parasitic capacitances, and that total plus the capacitive loading of the ECG cable with the lowest expected capacitance. Note that the sum of all non-patient cable loading effects can be significant relative to the loading effect of a short patient cable! The trip point of the CLP comparator may be matched to the system s needs by setting the dc voltage input at CLPIP, relative to one-half of VDDRSP. Note that the ac voltage at CLPIN will be centered inherently at VDDRSP/2. This is because it is dc-coupled from CLPCLK which swings from 0 V to VDDRSP and it has a 50% duty factor. Ideally, CLPIP s dc voltage is set at a level that is centered between the peak CLPIN voltage while no cable is attached, and the peak CLPIN voltage while the lowest capacitance cable is connected to the instrument but not to the patient. Because of the high impedance and dc level of the signal at CLPIN, the loading effect of a 10 MΩ scope probe causes too great an error (particularly dc) when trying to directly observe this signal. Also, the signal applied to the CLPIN input of the comparator has a basically triangular waveshape, and when only brief tips of that triangle exceed the level on CLPIP, the comparator may not respond (due to its finite gain and response time). The most accurate method of determining the required level for CLPIP requires setting up the system so that the status of the CLP bit may be monitored more or less continuously, and temporarily making CLPIP be easily adjustable between 2.5 V and the level of VDDRSP. Monitor the dc voltage at CLPIP. Then, with no cable plugged into the instrument s ECG connector, determine the trip threshold for CLPIP. Next, with the lowest capacitance ECG cable plugged into the instrument, determine the new trip threshold for CLPIP. Pick suitable fixed resistance values to set the final value of CLPIP at the point midway between these two trip thresholds. If VDDRSP and the other +5 V supplies are derived from the +2.5 V reference as recommended in the power supply discussion, the CLP threshold accuracy is greater if the CLPIP s voltage is developed by a voltage divider between VDDRSP and the +2.5 V reference, rather than by a divider between VDDRSP and ground. Note that depending on the design of the actual +2.5 V reference used, it may be necessary to limit the current through this divider to less than the sum of the minimum currents supplied to ground through the reference s other loads. Alternatively, if the reference cannot sink current, or if its minimum load current to achieve regulation is greater than the sum of its existing loads, it may be necessary to add a suitable load resistor between the reference s output and ground to maintain the needed minimum loading. If the Chest-Lead-Present Detector s function is not needed, connect its pins as shown in the 12-lead application schematic. Pacer Detector Circuit The Pacer Detector Circuit is based on a proprietary self-adapting scheme. One of the four ECG channel outputs is selected by a multiplexer that is controlled by two select bits, PDLS0 and PDLS1, and fed to the pacer detector. WARNING: It is the responsibility of the manufacturer integrating the ECG ASIC into a host system to make sure that the pacer detector s selected source is only allowed to be an ECG channel which is enabled by the ECG mode bits (MODE0 and MODE1), and which makes use of no electrodes that are not connected. The Pacer Detector Circuit contains switched capacitor filters whose characteristics facilitate distinguishing pacer pulses from environmental noise pulses and from QRS complexes generated by the heart. The detector includes a full-wave rectifier to deal equally well with pacer pulses of either polarity. A comparator checks the peaks of the filtered signal relative to a threshold level. Page 24 Copyright Rev. 2

25 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC It is important to note that it is the filtered signal which is compared against the comparator s trip point. This filtering attenuates pulses with widths progressively more narrow than 0.2 msec to a progressively greater degree. In the discussion below, note the distinctions between input-referred pulse amplitudes and filtered pulse amplitudes. Three Modes of Operation for the Comparator The comparator has three modes of operation: 1. Nonadaptive, with a fixed input-referred threshold that detects 3.0 mv pulses of 0.1 msec pulse width, and 2.0 mv pulses of 0.2 to 2.0 msec pulse widths. 2. Adaptive, with an adjustable input-referred threshold limit that detects 3.0 mv pulses of 0.1 msec pulse width, and 2.0 mv pulses of 0.2 to 2.0 msec pulse widths in the absence of noise pulses whose filtered pulse amplitudes exceed the filtered pulse amplitudes of these pacer pulses. For systems which limit the pacer detector mode of operation to just one choice, this mode provides the best overall choice. 3. Adaptive, with no intentional lower bound on the input-referred threshold (i.e., the threshold is effectively set by the noise level). NOTE: Be aware that narrow QRS complexes from some neonates may trigger the pacer detector in this third mode. These modes are set by the control bits ADPT and THMIN. The fixed threshold is proportional to the 2.5 V reference applied to the ASIC. The adaptive threshold is obtained by detecting the peak value of the filtered input signal or noise spikes and setting the threshold slightly higher than this filtered peak value. An external RC network (connected between pins PDCAP and PDFB) holds the peak-adjusted threshold level and slowly decays this level between input pulses, so that the detection threshold returns back to a low level by the end of a normal A/V sequential pacing period. For faster input pulse repetition rates (e.g. due to noise spikes that occur at two times the line frequency), the adapted threshold does not have enough time between consecutive pulses to decay appreciably. Therefore, the detection threshold for pacer pulses is forced to be slightly higher than the filtered peak amplitude of the noise pulses. Under these conditions, and up until the adaptive circuits saturate, only pacer pulses with filtered peak amplitudes greater than the filtered noise peak amplitudes will cause an output from the pacer detector comparator. Although performance is not included in the specifications, for 50 µsec-wide pulses at 120 Hz into the 2-stage ESIS filter, the detector in either adaptive mode will typically pick an occasional pulse at mv referred to input, and generally pick all pulses mv referred to input, depending on polarity. The non-adaptive input-referred threshold for these 50 µsec-wide pulses is about ±5.5 mv. The adaptive feature of the pacer detector is best at rejecting noise pulses that are of fairly consistent amplitude. (Most line-frequency-related noise spikes are like this.) Noise spikes during sparking of electrocautery are not only more random in amplitude, but may have time intervals between spikes that are long enough for the adaptation to decay. Therefore, it is not realistic to expect the adaptive feature to eliminate false pacer detector trippings during electrocautery. Also, there is a non-zero response time required for the detection threshold to adapt. The adaptation time depends on the amplitude, width, and time separation of the offending noise spikes. Practically speaking, this means that several spikes may trip the detector before adaptation is complete in instances where noise spikes occur in bursts separated by more than 50 msec or so. The PDCMPIN pin is a connection to one of the pacer detector s comparator inputs. There is an internal smoothing capacitor connected to this pin. It is important to prevent capacitive coupling of external digital signals into this pin Rev. 2 Copyright 2001 Page 25

26 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Pacer Detector Output PDETO PDETO is the output of the pacer detector. In general, the host system s ECG processor must respond immediately to PDETO to reject pacemaker pulses and their overshoots, and prevent them from being counted as heart beats. To help accomplish this, the rising (leading) edge of PDETO may be used to trigger a fairly high-priority interrupt to the ECG processor. Those users desiring to use PDETO to generate an interrupt should be aware that PDETO s logic HI=VDDA, not VDDIO. Alternatively, some sigma-delta A/D converters allow for a digital signal input which PDETO may drive. This digital signal is then embedded in the data stream of the converter s output along with the A/D conversion value. (The AD7716 converter includes this feature. In the AD7716, DIN1 gets latched into the AD7716 s output register right before its DRDY/ goes LO true.) This allows tight coupling of the pacer detector output with the first waveform conversion result that is certain to be corrupted by a pacemaker pulse. This coupling is achieved without using an interrupt line. The duration of a PDETO output pulse is stretched by the ASIC to be longer than the expected A/D conversion update interval in the ASIC s intended applications, so that at least one sample is always flagged with the pacer detection status. The user should be aware that all pacer pulse detectors have some amount of delay before indicating a pulse is detected. Because of that delay, some corruption may occur in the ECG data conversion sample prior to the pacer detector s response. Therefore, whether the signal processing system uses a digital input to the A/D converter or an ECG processor interrupt, the system should not consider an ECG sample to be uncorrupted by pacer pulses until the next sample following it does not contain a pacer detector flag. (This causes the display or other use of ECG samples to be one sample behind, but that delay is insignificant.) Pacer Pulse Detection Issues One of the two main reasons for using a pacer detector is to tell an ECG system that includes a heart rate meter function that a pacer pulse has occurred, and the rate meter shouldn t count the pacer pulse (or more likely its overshoot) as a heart beat. The second main reason is to discern if a patient s implanted pacemaker is working properly. For both reasons, the detector must be capable of determining when an actual pacer pulse has occurred and must somehow notify the user. Be aware that from the rate meter perspective, if a pacer pulse in a given ECG vector is too small to be detected, then its overshoot is too small to be counted as a heart beat. (The area under the curve in an overshoot cannot exceed the area under the curve of the main pacer pulse, since the pacemaker itself capacitively-couples the pulses. That capacitive coupling creates the actual overshoot.) Following are items that affect the amplitude of pacer pulses at the body surface, and thus their likelihood of being detected. The monitored ECG vector and the pacer pulse s electrical vector may be orthogonal to each other through the patient s body. If so, there will be very little, if any, of the pacer pulse present to be detected in such an ECG vector. If a multichannel ECG system s only pacer detector is assigned to an ECG vector which is orthogonal to the pacer pulse s vector, and a second ECG vector that is more nearly parallel to the pacer pulse s vector is used without benefit of pacer detection, a problem arises. Under these circumstances, pacer pulses and their overshoots can be large enough in the second ECG vector for them to be falsely counted as heart beats, yet no pacer detection is given. To deal with this possibility, some 5-electrode multi-channel ECG systems include a pacer detector permanently dedicated to each hardware-derived vector they offer (usually three). No matter how many simultaneous ECG vectors have dedicated pacer detectors, there will always be monitored patients (and not just a rare one) on which the pacer pulses are not reliably detectable due to low pulse amplitude at the body surface. Therefore, the clinical users must inevitably be prepared to deal with situations where pacer pulse detection is uncertain. Contributors to this include (at least) the design and settings of the pacemaker, the implant location of the pacemaker if it is a unipolar type, the location and contact impedance of its implanted electrode(s), the location of the monitoring electrodes, how much body surface fat or scar tissue, etc., underlies those electrodes, and the ECG vectors used. Page 26 Copyright Rev. 2

27 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC While having a detector per channel improves the chances of detecting real pacer pulses, it also carries liabilities. The most notable liability is how to decide which detector output(s) to use. (For telemetry systems, this decision perhaps must be made at a central station, if it is not made in the monitoring device.) The outputs of detectors on invalid channels (ones without enough electrodes connected to develop the intended vector, or ones with an electrode that has too much offset for the system to deal with) must somehow be ignored, whether by hardware or software means. Lead-fail detection and offset measurements drive those decisions. A more difficult situation is one in which a channel has all its electrodes connected and they have sufficiently low offset, but their contact with the patient is poor (due to insufficient skin preparation, dry skin, oily skin, dried-out electrolyte, or the electrodes have been worn for days and they re peeling off, etc.). These conditions may not cause an ECG lead-fail indication, but they cause a much greater likelihood of picking up environmental noise spikes, and thus yielding a much higher rate of pacer indication. Noise pickup problems may be exacerbated by using non-shielded electrode lead wires. The question then arises of how to ignore the noisy channel s detector, yet use the detector output from channels that work better. In some systems, a voting scheme may be established, whereby at least two of the channels must give an indication before using their outputs. However, a voting scheme cannot really take full advantage of multiple pacer detectors, since only one may be providing an accurate output. If the user has to make the choice of which channel s detector to use, it may be most appropriate to let that choice be consciously made at the time of connecting the monitor. For the above reasons, it is beneficial to consciously dedicate the ASIC s single pacer detector to the primary ECG vector on which rate monitoring is to occur. There is arguably a chance that using lead II for this purpose provides a better likelihood of including a decent portion of the pacer pulse s electrical vector, but that may not always be the case. If a different ECG vector is used for rate derivation, that vector should feed the pacer detector. WARNING: ANSI/AAMI EC13 requires the inclusion in the operator s directions for use of various warning statements, such as a warning about not leaving unattended those patients who have implanted pacemakers, and relying on heart rate meters on such patients. It is also appropriate to consider sources of internal ambient noise spikes. Among these are models of implantable pacemakers which inject narrow (< 30 µsec wide) pulses into the body for the purpose of doing impedance pneumography. From these, the pacemaker is able to extract respiration rate and minute volume information. When the minute volume is seen to increase (usually due to increased exertion), the minimum pacing rate is also increased to cope with that increased exertion. The response of the ASIC s pacer detector to these pulses depends on several factors. The basic technique used in (almost any) pacer detector hardware to decide what is and what is not a pacer pulse consists of a band pass filter/amplifier, followed by a full wave rectifier and comparator. Because of the filtering, pulses more narrow than 100 µsec can still trip the detector if their amplitudes are increased sufficiently. In fact, the more troublesome environmental noise spikes are often more narrow than 50 µsec, yet they can trip many pacer detectors. The band pass filter in the ASIC s pacer detector is designed to do a better job of rejecting narrow pulses than are pacer detectors that will detect 2 mv tall, 100 µsec wide pulses. (Note that its detection threshold for 100 µsec pulses is specified at 3 mv, and the ASIC s typical detection threshold for that width is closer to 2.8 mv.) If an incorrect filter is used between an ASIC ECG output and the input of the A/D, such a filter causes peaking of the ECG output due to capacitive loading. If the pacer detector is set to use such a peaked-up ECG output for its input, the detector s response to narrow pulses may also be affected. Finally, the ESIS filters used in front of the ASIC attenuate and stretch noise pulses to a degree dependent on the ESIS filters design. All of these items contribute to how the ASIC and associated circuits respond to narrow pulses Rev. 2 Copyright 2001 Page 27

28 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Pacer Detector Trip Thresholds for Very Narrow Pulses When coupled with the designs of ESIS filter and output low pass filter given in the 5-lead application circuit, the ASIC pacer detector s trip thresholds at any human heart rate are roughly as follows for the nonadaptive and adaptive-with-min-threshold modes (amplitudes are R.T.I.): 25 mv for 10 µsec pulses 13 mv for 20 µsec pulses 8.7 mv for 30 µsec pulses 5.2 mv for 50 µsec pulses Note that threshold means different things to different people. For some, if you feed the circuit 100 pulses of the same amplitude and it picks 2 of them, that amplitude is the threshold. For others, it must pick 98 out of 100 at that amplitude to constitute the threshold. The ASIC pacer detector s band pass filters use switched capacitor technology, and therefore have a variable in addition to amplitude that effects whether this detector will trip or not on a particular pulse. More specifically, the particular instant in time the peak of the (filtered) pulse occurs with respect to the sampling of these filters can also affect whether tripping occurs. With that sampling variability, plus the circuit s internal noise, plus the additive environmental noise spikes that inevitably get into the system to some degree, there is always some uncertainty in pulse detection for pulses whose amplitude is near the detection threshold. The above thresholds are for picking about 50% of the pulses on the average. While the ASIC s detector is used in its adaptive mode, the rate at which such pacemakers inject these very narrow pulses may affect how well they are rejected. In the case of one particular pacemaker, this pulse rate is 20 Hz, which is too slow a rate to get any benefit from the adaptive mode. If a pacemaker uses a pulsing rate that is faster than about 80 Hz, and the detector is used in its adaptive-with-min-threshold mode, then the ASIC s pacer detector will probably not trip on them for amplitudes approaching 1.6x those listed above. Even higher amplitudes will not trip the detector in this mode if the pulse repetition rate is higher. Such rates continue to change as pacemaker technology evolves. The design of the ASIC s single pacer detector is intended to maximize its utility in a wide variety of monitoring situations. Its adaptive feature allows it to ignore most repetitive ambient environmental (both internal and external) noise spikes, while still tripping on real pacer pulses whose amplitude (after being filtered by the detector) is above that of the noise spikes. The filtering used in the pacer detector attenuates the more narrow environmental spikes more than it attenuates real pacer pulses anyway, so even high amplitudes of very narrow noise pulses do not significantly change the adaptive detector s sensitivity to real pacer pulses. Furthermore, the detector s sensitivity to moderate-width pacer pulses is noticeably greater than that required by AAMI EC13, so it is more likely to pick up low amplitude pulses of those moderate widths even when the pacer and ECG vectors are nearly orthogonal with respect to each other. By comparison, the sensitivity of the pacer detectors in some ECG systems available today are notably less sensitive than EC13 requires or suggests, possibly to reduce their being tripped by many environmental noise spikes. Even using three such detectors does not guarantee better overall detection of real pacer pulses relative to the use of the ASIC s single optimized detector. Miscellaneous Causes for False Pacer Detection Reconnecting an electrode can cause a false tripping of the ASIC s pacer detector, even when the reconnected electrode is not used in developing the ECG vector which feeds that pacer detector. Disconnection of such an electrode does not trip the pacer detector. During connection, a transient is produced in the ASIC s ECG output which feeds the pacer detector, and that transient is large enough to legitimately trip the pacer detector. Conclusive experiments have shown that this problem is not due to inter-wire capacitive coupling in the ECG cable, but is one of capacitive coupling between physicallyadjacent ECG input pins of the ASIC itself (and perhaps between interconnection traces on the ASIC s actual die). When an electrode is disconnected, its ASIC input will rise to very nearly +5 V. A disconnected input is pulled up only by a ~ 70 na current source inside the ASIC, and when that 70 na must drive the capacitance of the ESIS filter and of the ECG cable s signal wire, the rise time is relatively slow. Page 28 Copyright Rev. 2

29 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC It is slow enough, in fact, that the capacitive current injected by a rising signal pin into a physically adjacent input pin can nearly all be bled off (to the potential of the reference electrode) through the ESIS filter of a connected input. Hence, the net disturbance to the adjacent input pin s signal is only a brief, negligible, voltage shift. (This is why no pacer detection occurs at electrode disconnect.) While an electrode is connected, the voltage at an ASIC ECG input is nearly zero. Reconnecting an electrode through a relatively low impedance to ground, etc. pulls the affected ASIC ECG input quite rapidly back to approximately ground. During this much faster fall time, the capacitive current injected into a physically adjacent pin cannot be bled away rapidly enough through the ESIS filter of an already-connected input, and that current forces the adjacent input negative by several mv or more. When only one of an active vector s ASIC inputs gets this current injection, a large-enough differential signal results, and the pacer detector "legitimately" fires. Causing a several mv shift in a high impedance input pin adjacent to a pin that rapidly drops by 5 volts is not unusual. Even if the ASIC s package and die were revised to fix this particular issue, unsnapping an electrode that is used by the pacer detector s input would still always fire the detector. Hence, the system must deal with a portion of these events anyway. Besides, electrodes do not get continually reconnected, so the incidence of such problems should be satisfactorily low. From a software perspective, note that depending on which vector is selected as the pacer source, changing any bit in the LDR register may trigger the pacer detector because the change truly causes a small, fast differential signal to be injected. Any change to LD1OR2 naturally will affect the ECGO1 output signal, and consequently the pacer detector if that is the detector s source. Changing LDR0 and LDR1 to change the choice of reference electrode from RL to LA will cause the LA "electrode voltage" to drop by about 8.4 mv (120 Kohm ESIS filter resistance times the 70 na lead fail detection current that then goes into the reference electrode driver inside the ASIC instead of through the ESIS filter resistance). Changing LDOPN determines whether or not an electrode used by that ASIC is or is not used as a reference electrode, which can cause at least as much delta in that electrode as the previous 8.4 mv example. Changing LDIN0 or LDIN1 will change the voltage that needs to be applied to the reference electrode, and that may or may not be large enough to trip the pacer detector (depending on the magnitude of change, any electrode impedance mismatches and the common mode rejection of the ASIC). In the PDL register, using PDLS0 and PDLS1 to change the source used by the pacer detector will almost certainly trip the detector. Possibly changing CLPOFF can cause a large enough transient to trip it also, but this is less likely. Other than possibly PDOFF, changing the other bits in the PDL register seem unlikely to cause spurious detector trippings. ECG Self-Test Circuits To help understand the following discussion, refer to the ECG Self-Test Control Register description on page 38, and the figures on page 13 and page 64. The ECG self-test circuits aid in the power-up diagnostics of the ECG section of the instrument. While these circuits are not intended to provide a complete test to the published specifications of this ASIC, they do facilitate verification of the proper functionality of most of the ASIC s basic ECG functions. Making use of these self-test capabilities can satisfy many of the needs identified by an FMEA (Failure Modes and Effects Analysis; the REGULATORY AND SAFETY ISSUES section on page 78 refers to an FMECA, which adds an analysis of probability and criticality to the basic FMEA). An FMEA analyzes what problems can occur in a system, and how the instrument can detect those problems. The internal circuit nodes shared by the RF low pass filters, lead-fail detection pullups, lead-fail detectors, and inputs to the ECG mode-select multiplexers (which feed the four differential amplifiers) can be fed by several different signals Rev. 2 Copyright 2001 Page 29

30 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies During normal ECG operation, these internal nodes are fed by the patient electrode signals, via the external passive ESIS filters and input pins EIN1-EIN5. When control bit INOPN is HI, the internal circuit nodes are disconnected from the electrode signals. This allows ECG testing to be done whether or not a patient is connected. While INOPN is HI and control bit TSTON is LO, the lead-fail detection pullup current sources will pull the internal circuit nodes nearly to the VDDA supply, simulating a lead-fail condition on all five inputs. While INOPN and TSTON are both HI, combinations of these internal nodes are fed by either internally-generated test signal VTST, or ground. Control signal TSEL selects which internal nodes are grounded and which receive VTST. The VTST signal is the summation of two internally-generated dc signals. One signal is nominally +130 mv or -130 mv, with its polarity being determined by control bit SIGN. The other signal is approximately mv with fixed polarity, which is turned on by control bit PDTST. Both signals are zero volts while control bit TSTON is LO, regardless of the states of SIGN or PDTST. Besides serving as an input to the differential amplifiers, VTST is also selectable as an input to the Reference Electrode Driver Circuit. For more details about how to use the self-test capabilities, refer to the Applications Information section on page 39. Respiration Function The Respiration function includes circuits for generating three-state, high-frequency (approximately 65 khz) signals for driving a selectable pair of electrodes, and circuits for generating Lead-select control for the external respiration circuits. The associated external hardware must include circuits for applying, amplifying, and measuring the resulting signal across the selected pair of electrodes, for performing a synchronous demodulation of the received signal, and for filtering the result and providing an output voltage related to thoracic impedance. The portions of this system implemented on-chip include the differential drivers for injecting currents through patient electrodes, a digital phase reference for the synchronous demodulator, and logic circuits to control the external respiration circuits. Portions of the impedance measurement circuit (synchronous demodulator, amplifier, etc.) have been left off-chip since their parameters need to be adjusted for different implementations. The on-chip driver circuits generate a simple step approximation to a sine wave in order to reduce the lowpass filtering requirements for the drive signals. (Refer to the RESP Circuit Timing Diagrams on page 11.) The output signal levels in the low, middle, and high states are respectively at the voltages of ground (0 V), RSPMID (2.5 V), and VDDRSP (5 V). The circuits present a relatively low output impedance in all three states. The circuits generate drive signals at the output RSPORA for driving the RA electrode, and a complementary (inverted) drive signal at either one of the outputs RSPOLA or RSPOLL, depending on the setting of the SEL bit in the respiration control register. The circuits also generate a square-wave phase reference signal at the respiration carrier frequency at output RSPREF for use by an external synchronous detector. Developing a respiration monitoring waveform by the impedance pneumography technique requires injecting into the ECG electrodes a current whose frequency is high by physiological standards, and generating an output wave form that is responsive to the changes in the impedance between electrodes. The total impedance seen by the impedance pneumography circuit is the sum of the defibrillator protection resistances in each wire of the ECG cable (often 1 kω per wire), the impedances of the electrodeto-skin interfaces (typically about 50 to 700 Ω each), the body s bulk tissue impedance between the electrodes (about 100 to 500 Ω), and the variations in the latter that occur during a breath (0.2 to 5 Ω peakto-peak). Except for the resistors in the ECG cable, all other impedances are frequency-dependent, and the stated values are given for the range of frequencies typically used for impedance pneumography (50 to 80 khz). The wire-to-wire and wire-to-shield capacitances in the ECG cable appear as impedances in parallel with most or all of these other impedances, depending on whether the ECG cable s defibrillator protection resistors are at the cable s instrument end or at the patient end respectively. Such shunting has a much greater affect on total perceived impedance when electrode-to-patient impedance is high, which typically occurs when the electrode gel has dried out or the adhesive is letting go. Page 30 Copyright Rev. 2

31 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC The Respiration Circuit Issues section of the Applications Information section (page 39) provides more details about how the external respiration circuits function. Voltage Reference Input and Bias Generator The 2.5 V reference input is used by the ASIC to scale all of its voltage-related functions. Independent of the 2.5 V reference, the external 1 MΩ RBIAS resistor is used to scale all internal currents. The ECG leadfail detection thresholds and their hysteresis, the switchable ECG offsets, the pacer detector threshold, and the self-test voltages are all ratiometric to the voltage reference input. Because 2.5 V is also the mid-point of the +5 V analog supply, it is appropriate to use that same voltage reference as the mid-level voltage supply for RESPMID, and as an external reference point for use by the chest-lead-present detector. For the most stable performance of RESP in particular, it is advisable to have the VDDRSP analog supply proportional to that same 2.5 V reference, and to also use that 2.5 V reference as the voltage reference for the A/D converter used by RESP. For most modes of ASIC operation, the current drawn by the VREF input is about 50 na. However, when any input channel has an offset enabled (EOS register), or the self-test voltage is enabled (EST register), its current draw increases to about 63 µa. The user s system needs to allow for this. Clock Divider Circuit The Clock Divider Circuit uses an external clock signal CLKIN (nominally MHz) and on-chip frequency dividers to generate all the various clock signals required by the ASIC. The frequency chosen for CLKIN was dictated by the needs of the AD7716 A/D converter in Welch Allyn Protocol s initial application of the ASIC. That converter s oscillator frequency needed to be MHz to provide the desired converter filter bandwidth and sample update rate in that application. The ASIC was designed to directly use that oscillator s output. Note that the CLKIN input has Schmitt-trigger characteristics so that it will work equally well with a sine wave clock input (assuming voltage levels are sufficient), or with a full logic swing square wave input. The timing of all digital signals inside the ASIC is derived from this CLKIN input. The frequency of all the respiration signals is CLKIN divided by 80. The frequency of CLPCLK is CLKIN divided by 160. The frequency responses of the ASIC s switched capacitor filters for the pacer detector and for the lead-fail detector s low-pass function are also directly proportional to CLKIN. Finally, the pulse width of the pacer detector s PDETO output is inversely proportional to CLKIN. Any changes to the CLKIN frequency affects all of these functions. WARNING: The frequency for respiration needs to be one that cannot beat with a frequency that is present elsewhere in the application system (such as a switching power supply frequency, for example) or in the end-user s operating environment, so that a resultant beat signal falls within the respiration pass band. If care is not taken to prevent this, it is likely that such a beat note signal will occur, and will sufficiently resemble a breathing signal so that it may prevent apnea detection by the host system. Changes of ±5 % or so to the CLKIN frequency will not affect pacer detector performance significantly, but larger changes should first be investigated by the designer to determine their acceptability for the intended application. The low-pass filters in the ECG lead-fail detectors are 3 db at 7 Hz when CLKIN is MHz, so they still provide reasonable rejection of power line frequencies for any change in CLKIN that causes acceptably small changes in pacer detector performance Rev. 2 Copyright 2001 Page 31

32 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Miscellaneous Control Functions The ASIC provides a way to power down its various functions through the serial interface by writing the appropriate control bits to the appropriate registers. In this way, portions of the ECG circuits and the respiration circuits can be turned ON or OFF independently under software control. The only circuits that cannot be turned OFF are the bias generator and lead-fail detection circuits (these consume very little current). Also provided is a hardware test input, HWTST, which can be used to force the ASIC s control registers into known states where most circuits are active. (HWTST is only used during manufacturing testing. It does not need to be asserted like a power-up reset signal, but should be tied to ground.) HWTST does not affect the serial interface, and does not force any output into a high impedance state. Details of this are discussed in the Control Register Description on page 33. Serial Interface Description The serial interface provides read/write access to the on-chip control registers which set the ASIC in its various operating modes. Communication with an external controlling agent such as a host processor or controller is achieved through four signal lines as shown below. Serial Interface Control Lines Signal Function CS/ SCLK DIN DOUT Not Chip-Select Serial Clock Serial Data In Serial Data Out Serial Interface Operation Operation of the serial interface can be explained with the help of the timing diagrams for the WRITE and READ functions as shown on page 10. Initially, while CS/ is held at a logical high (HI) level, the serial interface is disabled and held internally in a reset condition. Communication is enabled when CS/ makes a transition to a logical low (LO) state. It is required that the serial clock input SCLK be held HI just prior to and during this transition. Considering the WRITE operation first, the host processor is required to set up a string of 16 bits on signal line DIN in the following sequence: 1. The first three bits (I2, I1, I0) define the instruction to be executed. Note that I2 is ignored, and from I1 and I0, only two instructions (READ and WRITE) are defined as shown below: Read/Write Bits Function I2 I1 I0 READ x 0 0 WRITE x The next five bits (A4-A0) define the address of the on-chip register to be accessed. Bits A3 and A4 are not decoded. Only the lower 7 of the addresses defined by A0-A2 contain actual registers. 3. The last eight bits (D7-D0) constitute one byte of data to be written to the desired on-chip register. In each input field (instruction, address and data), the bits occur in sequence with the most-significant bit (MSB) first. It is convenient, but not required, for the bits to be generated by the host processor on the rising edges of the serial clock (SCLK). The ASIC loads these bits in sequence into an intermediate register on the falling edges of SCLK. For the WRITE operation, the selected on-chip register is updated with the new data on the 16th rising edge of SCLK while CS/ is still LO. The WRITE operation is safely aborted (i.e. the register is not updated) if CS/ goes HI before the end of this required interval. Page 32 Copyright Rev. 2

33 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC For the READ operation, the first eight bits on DIN define the instruction and register address fields, just as for the WRITE operation. The data from the addressed on-chip register is made available on the dataout line DOUT on the falling edges of SCLK (starting at the ninth falling edge of SCLK after CS/ goes LO). Again, the data is presented in sequence with the MSB occurring first. It is convenient, but not required, for the host processor to read the data on DOUT on the rising edges of SCLK. The DOUT output of the ASIC is held in a high-impedance condition at all times except when data is being read out, and is returned to a high-impedance state when CS/ goes HI during or at the end of a read cycle. NOTE: It is highly recommended that the host system do its shifting out and clocking in of data on the rising edges of the SCLK it generates, and leave SCLK HI between transfers. If constraints of the host processor dictate that it shift and latch data on the falling edge of SCLK, then the host software will need to compensate for what may be perceived as a one-cycle delay in ASIC communications. Note that from a data-transfer perspective, the ASIC cares only about 16 falling clock EDGES of SCLK while CS/ is low, not necessarily SCLK cycles. Serial Interface Timing Since the serial interface is used only to set the ASIC in specific operating modes (and verify the desired settings), fast operating speed was not a primary design requirement. Also, the fact that the ASIC is implemented in a primarily analog process with fairly conservative design rules (compared with a submicron digital process, for example), the operating speed of the interface is fairly slow. This limits the maximum toggle frequency of SCLK to 500 khz. See the Specifications for more timing details. The logic levels for the serial I/O pins SCLK, CS/, DIN, and DOUT are 0 V (LO) and VDDIO (HI). ASIC input HWTST does not affect the serial interface. Register Map The following table defines the address mapping of all on-chip control/status registers: Control/Status Registers A2 A1 A0 READ/WRITE REGISTER DEFINITION NAME R/W ECG mode and lead-select register EMD R/W ECG lead-drive control register LDR R/W ECG offset voltage control register EOS R/W Pacer detector and lead-fail control register PDL R Lead-fail status register LFS R/W ECG self-test mode control register EST R/W Respiration circuit control register RSP Not Used - Control Register Description As mentioned previously, the ASIC can be set-up in several operating and test modes by writing to several registers through the serial interface. The following describes the various registers used to set the various ECG modes. The "R/W" notation in the boxes below indicates bits that were included as spares in the ASIC design. They have read/write capability, but do not affect any ASIC operation. Note that "x" terms in the boxes below are for bits that do not exist in the indicated registers. Writing to those bits has no effect. Even though those bits act like high impedance nodes when read, each read cycle precharges those nodes LO so that they always read back LO. The default condition is the collection of states to which all bits are forced while HWTST is asserted. (Logic HI for HWTST=VDDIO.) Rev. 2 Copyright 2001 Page 33

34 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies ECG Mode Control Register (EMD, Read/Write, Address=0): This register sets the ECG operating modes and enables the Reference Electrode Driver Circuit as shown: ECG Mode Control Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x R/W R/W LDROFF MODE1 MODE0 ECGOFF Default x x ECGOFF: Turns OFF all ECG differential amplifiers, effectively forces PDETO LO, forces ECGON LO, and forces RSPOFF HI for ECGOFF=1. If ECGON is connected (externally) to also disable CLKIN, then setting ECGOFF=1 also halts CLPCLK, RSPREF, RSPORA, RSPOLA, and RSPOLL in their previous states. MODE0, MODE1: Control operating modes of the ECG circuits according to the following table: Mode Control MODE1 MODE0 Mode Definition Lead Primary Mode Lead Secondary Mode Lead Mode Lead Mode These mode control bits set the various input multiplexers and turn ON (or OFF) the appropriate ECG amplifiers to provide the required input-output relationships for the different modes of operation listed above. They do not affect functions such as the the Reference Electrode Driver, pacer detector, etc. However, the pacer detector output will inherently stay LO while its source is selected from a differential amplifier which is turned off by the ECG mode selection, since then there is no signal to trigger the pacer detector. The resulting input-output relationships in the different modes are listed in the table below, where the following Lead and signal definitions apply: I = LA - RA, II = LL - RA, III = LL - LA, AVG3 = (LA+LL+RA)/3, V(n) = V (n) - AVG3 (n = 1 6). Note: In the 12-lead Secondary mode, AVG3 is obtained from AVG3IN which must be connected to the AVG3O pin of the Primary ASIC. Inputs/Outputs for 3-Lead, 5-Lead, and 12-Lead Modes Inputs/Outputs 12-lead Primary 12-lead Secondary 5-lead 3-lead IN1 LA V 3 LA LA IN2 LL V 4 LL LL IN3 RA V 5 RA RA IN4 V 1 V 6 V Disabled IN5 V 2 RL RL Disabled OUT1 Lead I / II Lead V3 Lead I / II Lead I / II OUT2 Lead III Lead V4 Lead III Lead III OUT3 Lead V1 Lead V5 Lead V Disabled OUT4 Lead V2 Lead V6 Disabled Disabled AVG3IN Disabled Enabled Disabled Disabled AVG3OUT AVG3 Disabled AVG3 AVG3 When AVG3IN is disabled, this external input is disconnected prior to the common mode selection multiplexer. When AVG3O is disabled, it goes to a high impedance condition. Page 34 Copyright Rev. 2

35 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC LDROFF: Turns OFF the Reference Electrode Driver amplifier and common mode output buffer for LDROFF=1. It also sets the output level of that driver to analog ground (0 V) through a FET. Note that if LDOPN is set HI in the LDR register, LDROFF cannot ground the selected reference electrode, but can still turn off that driver amplifier. ECG Reference Electrode (Driven-Lead) and Lead-Select Control Register (LDR, Read/Write, Address=1): This register is used to select the reference electrode and the common-mode input source to the Reference Electrode Driver as described below: ECG Reference Electrode and Lead-Select Control Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x LDIN1 LDIN0 LDOPN LDR1 LDR0 LD1OR2 Default x x LD1OR2: Selects Lead I (LA-RA) for LD1OR2=0 as the output of ECG channel 1, or selects Lead II (LL-RA) for LD1OR2=1. This bit is ignored by ECGO1 (but not by the Reference Electrode Driver output multiplexer or by the common mode source multiplexer) when the ASIC is set to the 12-lead Secondary mode. LDR0, LDR1: Determine the selection of the reference electrode according to the following table: Selection of Reference Electrode LDR1 LDR0 LD1OR2 Reference Electrode 0 0 x DRV5 0 1 x DRV4 1 0 x DRV DRV DRV1 In the last column of the previous table, driven-lead DRVi is equivalent to the ith ECG input pin of the ASIC. The selected input and reference electrode pin definitions correspond to the actual patient electrodes as defined in the table below. Reference Electrode and Patient Electrodes Input Pin Reference Electrode 3- Lead System 5-Lead System 12-Lead System (Primary ASIC) 12-Lead System (Secondary ASIC) EIN1 DRV1 LA LA LA V 3 EIN2 DRV2 LL LL LL V 4 EIN3 DRV3 RA RA RA V 5 EIN4 DRV4 - V V 1 V 6 EIN5 DRV5 RL-LL cable short RL V 2 RL LDOPN: Making LDOPN=1 disconnects the Reference Electrode Driver circuit from all of the EIN1-EIN5 pins of the ASIC (regardless of the state of LDROFF in the EMD register). For LDOPN=0 the reference electrode is selected by LDR0, LDR1 as described above Rev. 2 Copyright 2001 Page 35

36 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies LDIN0, LDIN1: Select the common-mode source for the Reference Electrode Driver according to the following table: Reference Electrode Driver Common-Mode Source LDIN1 LDIN0 Common-Mode Source 0 0 AVG3 0 1 CM1OR2 1 0 CM3 1 1 VTST CM1OR2 = (LA+RA)/2 when Lead I is selected (LD1OR2 = 0), CM1OR2 = (LL+RA)/2 when Lead II is selected (LD1OR2 = 1), CM3 = (LL+LA)/2, and AVG3 = (RA+LA+LL)/3. AVG3 is obtained from the internally-generated signal (the same that drives AVG3O) except while in 12 lead Secondary mode when AVG3 is obtained from input pin AVG3IN. The signal VTST is the internally-generated test signal that is enabled by the EST register. The VTST test voltage generator is enabled, then that generator s outputs affect all four of the above common mode selections, not just VTST. Also note that the CM1OR2 and CM3 selections still function, but are not appropriate for use while in 12-lead Secondary mode. ECG Offset Voltage Control Register (EOS, Read/Write, Address=2): This register individually controls the offset voltage (and hence the input range) for each of the four ECG amplifiers as described below: ECG Offset Voltage Control Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OSGN4 OSON4 OSGN3 OSON3 OSGN2 OSON2 OSGN1 OSON1 Default The values OSONi (i=1-4) respectively turn ON (or OFF) the offset for each individual ECG channel (outputs ECGO1-ECGO4) while OSGNi (i= 1-4) determine the polarity of the offset according to the following table: Offset Control OSON OSGN Offset Definition Input Range 0 x No Offset -300 mv to +300 mv mv Offset -70 mv to +530 mv mv Offset -530 V to +70 mv Note that while any channel has its offset turned on, the lead-fail detection thresholds are raised for all four channels. (See the Lead-Fail Detection Function section on page 20.) Pacer Detector Mode, Lead-Fail Control Register (PDL, Read-Write, Address=3): This register sets the pacer-detector and lead-fail detector operating modes as described below. Pacer Detector and Lead-Fail Control Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RLPUP/ LFOSC CLPOFF PDLS1 PDLS0 THMIN ADPT PDOFF Default PDOFF: Turns OFF the pacer detector and forces PDETO to stay LO when PDOFF=1. Bits PDLS0, PDLS1, THMIN, and ADPT are ignored while PDOFF is HI. Page 36 Copyright Rev. 2

37 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC ADPT: Selects adaptive pacer detector mode when ADPT=1. The pacer detector is in fixed-threshold mode (VTH 1.8 mv for 0.2 and 2.0 msec pulses) when ADPT=0. THMIN: Sets minimum threshold in adaptive mode. VTH 1.8 mv for 0.2 and 2.0 msec pulses when THMIN=1, and VTH 0.5 mv (noise-floor in practice) when THMIN=0. This bit is ignored in non-adaptive mode (ADPT=0). PDLS0, PDLS1: Selects the pacer detector source (from the outputs of the ECG amplifiers) as defined in the following table: Pacer Detector Source PDLS1 PDLS0 Pacer Detector Source 0 0 ECGO1 0 1 ECGO2 1 0 ECGO3 1 1 ECGO4 Note that if an "off" channel is selected (like ECGO3 or ECGO4 while in 3-lead mode), PDETO stays LO. CLPOFF: Turns OFF the chest-lead-present detector and forces the CLPCLK output and CLP bit in the LFS register both LO when CLPOFF=1. LFOSC: When LFOSC=1, the switched-capacitor circuits in the on-chip lead-fail detector operate from an internal clock oscillator. This allows the lead status to be continuously monitored even when the rest of the ECG system is powered down, including the external sigma-delta A-D converter which generates the MHz clock. When LFOSC=0, the required clock is derived from CLKIN. RLPUP/: Enables the RL lead-fail pull-up current source for RLPUP/=0 and disables this current source for RLPUP/=1. (Note that this affects the pull-up on EIN5, regardless of that pin s definition based on ECG mode. More specifically, it is necessary to set RLPUP/ to LO to do lead-fail detection on V 2 when in 12- lead Primary mode. Lead-Fail Status Register (LFS, Read Only, Address=4): The bits in this register represent the outputs of the lead-fail detector and chest-lead-present detector. An open electrode connection on any input EINi (i=1...5) causes the corresponding lead-fail bit to be set (LFi = 1, i=1...5). Conversely, a good electrode connection to the ith input results in LFi=0. LF1-LF5 are indeterminate while CLKIN is stopped and LFOSC is LO. CLP=1 indicates the presence of the chest (V) wire in a 5-wire ECG cable, whether or not the V electrode is connected to the patient. All lead-fail detectors are fully functional, even on inputs not used by 3-lead ECG mode. The LFS register always reflects the current status of electrode connections. When any input changes connection status, output bit LDCH/ goes LO and stays LO until the LFS register is read, at which time LDCH/ goes HI again. CLP functions whether or not respiration is enabled. CLP is indeterminate if CLPOFF is LO while CLKIN is stopped, regardless of the state of LFOSC. Lead-Fail Status Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x LF5 LF4 LF3 LF2 LF1 CLP Rev. 2 Copyright 2001 Page 37

38 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies ECG Self-Test Control Register (EST, Read/Write, Address=5): This register controls the operation of the ECG self-test functions built into the ASIC: ECG Self-Test Control Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x x PDTST SIGN INOPN TSEL TSTON Default x x x TSTON: Turns ON the ECG self-test signal-generator for TSTON=1. Its output is internal signal VTST. PDTST, SIGN, and TSEL are ignored while TSTON is LO. See note below. TSEL: Selects the inputs to which the generated test signal VTST is applied according to the following table: VTST Input Selection TSEL VTST applied to inputs Inputs grounded (0V) 0 EIN1, EIN3, EIN5 EIN2, EIN4 1 EIN2, EIN4 EIN1, EIN3, EIN5 INOPN: Opens (disconnects) all five input pins (EIN1-EIN5) for INOPN=1. This allows the internal input nodes to float and be pulled up by the lead-fail current sources which allows testing of lead-fail functionality. See the note below. SIGN: Determines the polarity of the dc test signal. VTST = +130 mv for SIGN = 1 and VTST = -130 mv for SIGN=0. SIGN does not affect the polarity of the PDTST signal. PDTST: Adds a minus ~4.25 mv dc shift to the test signal when PDTST=1. Does not affect test signal when PDTST=0. NOTE: The output of the self-test circuits feeds the lead-fail detectors and X8 differential amplifiers. (See the Self Test Diagram on page 64.) These self-test outputs are controlled by VTST, SIGN, and PDTST only while both INOPN and TSTON are HI simultaneously. Because EIN1 and EIN3 are controlled together, no output change should occur in Lead I. However, verifying no change in Lead I plus verifying proper changes in Leads II and III constitutes a complete test of the first ECG channel. VTST may also be selected by the common mode source multiplexer as the input to the Reference Electrode Driver amplifier. Respiration Circuit and General Purpose Output Register (RSP, Read-Write, Address=6) Resp Circuit and General Purpose Output Register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x R/W GPO4 GPO3 GPO2 GPO1 SEL RSPON Default x RSPON: Turns ON respiration circuits. Also affects the RSPOFF output bit for turning off all external respiration monitoring circuits. When RSPON is LO, it forces RSPREF and RSPORA to 0 V, and forces RSPOLA and RSPOLL to VDDRSP. Note that while the RSPON register bit itself is not affected by it, having the ECGOFF bit set HI in the EMD register forces the RSPOFF output pin HI. Also, if the ECGON output is connected (externally) to stop CLKIN when ECGON is LO, then RSPORA, RSPOLA, RSPOLL, and RSPREF will be halted in their last states. SEL: Selects the pair of electrodes to be driven by the respiration drive signal outputs. SEL=0 causes outputs RSPORA, RSPOLL (right arm, left leg) to be selected, while SEL=1 causes outputs RSPORA, RSPOLA (right arm, left arm) to be selected. Page 38 Copyright Rev. 2

39 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC GPO1-GPO4: General-Purpose Output bits are made available externally through pins 23 to 26 to control the lead selection of external respiration circuits and other user-defined circuits. CAUTION: Because these pins are pulled to VDDRSP or RSPGND, changes in the output currents supplied by GPO1-GPO2 can couple into the respiration outputs. If any loading other than logic inputs will occur, it is strongly recommended to avoid cycling these pins at rates within the (external) respiration channel s passband to avoid such problems. (Avoid repetitive cycling at rates slower than about 10 Hz.) Note that even though the above descriptions call out the use of the RA, LA, and LL electrodes, the user can choose to connect any other combination of ECG electrodes to the external respiration circuits. APPLICATIONS INFORMATION Following are representative schematics for 5-lead and 12-lead ECG circuits and their A/D converters. Also shown are peripheral circuits (like respiration, hardware shutdown control, pacer detector, chestlead-present detector, etc.) that may be added or deleted in whatever combination the user desires. ECG input filtering sufficient to suppress most common-mode electrocautery noise is shown, as well as a simpler filter to use when ESIS is not required. Where appropriate, instructions are included to adapt the designs to a particular user application. Many additional application details are included that have been gained through decades of experience with these applications. Respiration Circuit Issues The external respiration circuits perform the following functions: bandpass filtering of the respiration carrier to achieve a more nearly sine wave signal for driving the patient, providing series capacitors to the patient for fault protection, bandpass filtering the carrier signals from the patient, providing defibrillator discharge protection clamping, and providing respiration lead selection, synchronous demodulation, final low-pass filtering, and respiration circuit power-down. Respiration circuit signal conditioning begins by subtracting a fixed offset from the rectified (demodulated) average magnitude of the signal developed across the patient. The difference is greatly amplified, bandpass filtered, and then processed by a breath-picking software algorithm. The subtraction must be done to remove the portion of the total carrier signal magnitude that is dropped across the defibrillator protection resistors in series with each of the ECG wires. Because the gain is significant after the subtraction, slight changes in the applied carrier amplitude, changes in the attenuation or phase shifts of any filtering in its path, or changes in the gain or phase shift of amplifiers prior to the subtraction can have a larger effect on the dc output level of the synchronous demodulator. That dc level is used as an indication of total impedance in the measurement path. It determines the threshold for indicating a lead failure unique to respiration, etc. Although it is not a highly accurate ohmeter, this dc level still needs to be reasonably consistent from unit to unit. For this reason, many of the capacitors in the filtering circuits require tighter tolerances than one might otherwise expect. Note that the respiration channel is highly sensitive to noise on its VDDRSP supply, and will include much of that noise in the channel output at U3, pin 1. See ASIC Power and Connections and Issues (page 53) for more details. WARNING: Portions of the respiration circuits are subject to high voltages and currents during defibrillator discharge. See Component Voltage and Power Rating (page 59), and Layout Considerations (page 73) for more details. WARNING: The 0.1 µf capacitors (C1, C4, C7) between the respiration carrier generators and the patient cable connections for RA, LA, and LL normally do not contribute significantly to signal conditioning. They are also not required to block dc from the ECG signals. Instead, they serve only as a secondary means to prevent a single fault (like a shorted 220 pf capacitor from a carrier generator) from causing excessive dc currents through the patient while a respiration driver like RSPOLA is at 5 Vdc (either due to respiration being turned off completely, or due to the respiration vector being RSPORA and RSPOLL). This redundant protection is a regulatory requirement Rev. 2 Copyright 2001 Page 39

40 ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies Sample Schematic for 5-Lead ECG with RESP and Power Shutdown Page 40 Copyright Rev. 2

41 Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC Sample Schematic for 12-Lead ECG Rev. 2 Copyright 2001 Page 41