Towards reliable FPGA-based satellite systems - the RUSH experiment
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1 Towards reliable FGA-based satellite systems - the RUSH experiment Ediz Cetin Department of Engineering ediz.cetin@mq.edu.au 19 April 2017
2 COTS FGAs in Space The processing speed, cost and flexibility requirements of future satellitebased applications cannot be satisfied with conventional radiationhardened processors or custom integrated circuits. Growing international interest in the development of space missions based on low-cost nano-/microsatellites demands new approaches to the design of reliable, low-cost, reconfigurable digital processing platforms SRA-based Field rogrammable Gate Arrays (FGAs) provide an opportunity for meeting these requirements with off-the-shelf hardware. SRA-FGAs ride oore s law (unlike radiation-hardened counterparts) As a group we are undertaking research into designing highly reliable COTS SRA-FGA based reconfigurable systems for space applications 2
3 ESA Sentinel 2 ission ayload latform Std. ASIC 5% Total Std. ASIC 4% ASIC 14% ASIC 32% icroprocessor 10% ASIC 29% icroprocessor 9% FGA 86% FGA 53% FGA 58% IC Type Quantity latform Quantity ayload FGA Custom ASIC 72 6 icroprocessor 23 0 Standard ASIC 10 0 * Data from: Trends and patterns in ASIC and FGA use in space missions and impact in technology roadmaps of the European Space Agency, Roger Boada Gardenyes, aster Thesis, T. U. Delft and ESA, 15th August
4 FGA Fabric and the SEUs SRA-based FGA can be thought of consisting of two layers: an application layer: Where user circuits live and operate a configuration layer: Where specific information is written or downloaded into the SRA-based configuration memory to configure the FGA to implement user applications (in the application layer). Configuration Layer Application Layer 4
5 FGA Fabric and the SEUs FGAs, however, are particularly susceptible to radiation-induced Single Event Upsets (SEUs): Deposited charge causes a change of state in dynamic circuit elements Affects both datapath (application layer) and configuration memory (configuration layer) Datapath Bit SEU A=1 B=0 01 C=0 F=1 F=0 5
6 Configuration emory Error Recovery - Scrubbing 6 a b z c Energy wasted since the system is scrubbed even if there are no errors Increased ean Time to Detect (TTD) Errors Robust error recovery technique
7 Configuration emory Error Recovery odule Based 7 a b z c Low energy consumption Rapid TTD No error recovery in the configuration bits of the shaded region
8 RUSH ayload Will test and compare traditional scrubbing approach with odule Based Error Recovery (ER) approach. Xilinx Artix 7 SRA-FGA Actel (icrosemi) SmartFusion Flash-FGA 8
9 Research Questions ost RUSH ayload How do you deal with non-triplicated resources (or resources that cannot be triplicated)? Use FER: A hybrid error recovery technique (best of both worlds) See: Agiakatsikas et. al, FER: A Hybrid Configuration emory Error Recovery Scheme for Highly Reliable FGA SoCs. 26 th International Conference on Field-rogrammable Logic and Applications (FL 16), a b z c
10 Research Questions ost RUSH ayload In which order and how should one check the TR voters? Application layer Off-chip memory TR 1 TR 2 Reconfiguration controller TR N Configuration layer ICA hysical link between the application and configuration layers See: Nguyen et.al. Dynamic Scheduling of oter Checks in FGA-based TR Systems, International Conference on Field-rogrammable Technology (FT 16),pp Zhao et. al., Fine-grained odule-based Error Recovery in FGA-based TR Systems, International Conference on Field-rogrammable Technology (FT 16), pp Agiakatsikas et. al., Reconfiguration Control Networks for TR Systems with odule-based Recovery, IEEE Symposium on Field-rogrammable Custom Computing achines (FCC 16), 10 pages 88 91, 2016.
11 Do I need to be an FGA and Reliability Expert to Implement Fault-tolerant Circuits on FGAs? Yes but not for long! (We hope ) Introducing TLegUp Given high level C code, generates low level highly reliable FGA implementations that are already triplicated and ready to deploy on FGAs. See: Lee et. al, TLegUp: A TR Code Generation Tool for SRA-Based FGA Applications Using HLS, To appear IEEE Symposium on Field-rogrammable Custom Computing achines (FCC 17), ay
12 Team embers (artial) 12
13 Funding Research work supported by the Australian Research Council: ARC Linkage Grant (L ) ARC Discovery Grant (D ) artners: 13
14 What s Next for RUSH ayload on FloripaSat (Late 2017) in Collaboration with Federal University of Santa Catarina (UFSC) Brazil RUSH RUSH-SDR : Dual RF channel 70 Hz 6 GHz Software Defined Radio (SDR) with on-board FGA-based processing (under development) Research: Looking for use cases from the CubeSat Community 14
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