IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER

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1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER A Millimeter-Wave (24/31-GHz) Dual- Band Switchable Harmonic Receiver in 0.18-m SiGe Process Mohamed El-Nozahi, Student Member, IEEE, Ahmed Amer, Student Member, IEEE, Edgar Sánchez-Sinencio, Fellow, IEEE, and Kamran Entesari, Member, IEEE Abstract A dual-band switchable harmonic receiver for downconverting the industrial-scientific-medical and local-multipoint-distribution-service bands at 24 and 31 GHz is proposed in this paper. The front end utilizes a new technique for band selection. Mathematical formulation, including the effect of mismatches, for the new switchable harmonic receiver is provided in this paper. In addition, new circuit techniques for the low-noise amplifier and millimeter-wave mixer implementations are presented. The receiver is implemented using m BiCMOS technology with a total power consumption of 60 mw. Measurements show a band rejection higher than 43 db, gain of 21 and 18 db, NF lower than 8 and 9.5 db, and third-order intercept point of 18 and 17 dbm for the 24- and 31-GHz frequency bands, respectively. Index Terms BiCMOS, dual band, millimeter wave, receiver, switchable harmonic, wideband. I. INTRODUCTION T HE GROWING number of wireless applications in the communication market is one of the main drivers of the semiconductor industry. With the increasing demand for high-data-rate communication, and the congestion of the low-gigahertz frequency bands, moving to the largely unused spectrum at millimeter-wave (mm-wave) frequencies is necessary. Some system applications include the IEEE wireless metropolitan-area network (WiMAN) for point-point wireless communications at the GHz frequency range, automotive short-range and long-range radars for collision avoidance at and 77 GHz, and cognitive radios. Several complementary metal oxide semiconductor (CMOS)/BiCMOS single-band transceivers are reported for mm-wave applications [1] [11]. The idea of combining multiple bands is also very appealing for mm-wave transceivers on silicon to increase the versatility and save the chip area. Single-band receivers at mm-wave frequencies have been the main focus of a lot of literature until now. The first 24 GHz Manuscript received February 03, 2010; accepted July 01, Date of publication October 25, 2010; date of current version November 12, This work was supported in part by the Semiconductor Research Corporation (SRC) and in part by the Semiconductor Industry Association (SIA). M. El-Nozahi is with Marvell Semiconductor, Santa Clara, CA USA. A. Amer, E. Sánchez-Sinencio, and K. Entesari are with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX USA ( melnozahi@ieee.org; ahmed.amer00@ieee.org; e.sanchez@ieee.org; kentesar@ece.tamu.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TMTT CMOS front end in a m process was reported in [1]. A receiver front end that incorporated a folded microstrip geometry to create resonance at the 60-GHz band in a common-gate low-noise amplifier (LNA) and active quadrature mixers was realized in m CMOS technology [2]. Guan et al. [3] reported a fully integrated 8-channel phased-array heterodyne receiver at the 24-GHz industrial-scientific-medical (ISM) band in BiCMOS technology. Receiver chip sets for gigabit per second wireless communications in the 60-GHz ISM band in BiCOMS and CMOS technologies were demonstrated in [5] [9]. A fully integrated phased-array receiver with integrated dipole antennas for long-range automotive radar applications at 77 GHz was designed and fabricated in a m BiCMOS process in [11]. As can be seen, most of the efforts have concentrated on developing the first generation of single-band commercial silicon receivers at 24, 60, and 77 GHz. A mm-wave dual/multiband silicon-based receiver is necessary to reduce the size and cost of the transceiver to avoid several front ends for each band. These receivers will be necessary to cover the GHz frequency range for many applications occupying different bands, such as wireless applications. A similar requirement exists for low-gigahertz applications, such as WiFi at 2.4 GHz and 5.2 GHz. Dual/multiband receivers design poses many challenging problems at mm-wave frequencies as follows: 1) Frequency synthesizers need to span over a very wide frequency range to cover the entire band of interest. As a result, they are power hungry or very hard to implement due to the wide tuning range of a voltage-controlled oscillator (VCO) and 2) front-end building blocks including LNA and mm-wave mixers have to support a very wide frequency range. Hence, receiver architectures, which rely on frequency synthesizers running at lower frequencies and new front-end topologies, which support the multi-gigahertz frequency range need to be developed to overcome the aforementioned challenges. The first dual-band 22 29/77 81 GHz transceiver for automotive radars have been recently reported using BiCMOS technology [12]. The transceiver is based on a direct conversion receiver architecture along with a dual-band LNA and frequency synthesizer. To avoid having a very wide tuning range of the VCO, this receiver architecture uses two local oscillators (LOs) for each separate band. In addition, these LOs have to run at 22 and 77 GHz, which result in high power consumption. This receiver shows that direct conversion receivers are not suitable for multiband operation at mm-wave frequencies because of the limited tuning range of the LO. To the best of our knowledge, /$ IEEE

2 2718 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 Fig. 1. Proposed switchable harmonic receiver architecture. there is no other reported dual/multiband silicon-based radio at mm-wave frequencies. In this paper, a new dual-band receiver architecture is proposed to downconvert the ISM and local multipoint-distribution system (LMDS) bands at 24 and 31 GHz, respectively. The receiver is targeted for the single carrier wireless metropolitan-area network standard (IEEE ). The IEEE SC is specified for the GHz applications. This standard supports channel bandwidths of 20, 25, and 28 MHz, with quadrature phase-shift keying (QPSK), 16-quadrature amplitude modulation (QAM) and 64-QAM modulation schemes for bit rates up to 134 Mb/s [13]. In the proposed architecture, each of the 24- and 31-GHz bands has a bandwidth of 250 MHz, including 9 channels with 25-MHz bandwidth and QPSK modulation. The receiver relies on a switchable harmonic mixer for band selection. The switchable harmonic mixer allows the LO to run at a lower frequency, hence eliminating the need for a wideband VCO (challenge 1). In addition, new circuit techniques for a wideband LNA and wideband mm-wave mixer are employed to cover the frequency band of interest and to further reduce the power consumption (challenge 2). The receiver is implemented using m SiGe BiCMOS technology 70/170 GHz/GHz). The paper is organized as follows: In Section II, the proposed switchable harmonic receiver architecture is presented. Different building blocks of the receiver, including the wideband LNA, the wideband mm-wave mixer, and the switchable harmonic mixer, and their implementation are discussed in Section III. The measurement results are then shown in Section IV. Finally, the conclusion is presented in Section V. II. PROPOSED RECEIVER ARCHITECTURE A. Basic Idea The proposed receiver architecture and its frequency planning are demonstrated in Figs. 1 and 2, respectively. Similar to the heterodyne receiver, the desired band is downconverted to baseband through an intermediate frequency. The two Fig. 2. Frequency planning of the proposed switchable harmonic receiver (Channel bandwidth = 25 MHz, total RF band Bandwidth = 250 MHz). frequency bands, at 24 and 31 GHz, are initially amplified using a two-stage wideband LNA. Then, a wideband mm-wave mixer and a LO (LO1) running at GHz (effective mixing frequency is 20.5 GHz) is used to downconvert the 24- and 31-GHz bands to intermediate frequencies of 3.5 and 10.5 GHz, respectively. The second mixing stage is a switchable harmonic mixer (SWHM) for band selection and final downconversion of signals to baseband. The second LO (LO2) operates at a frequency of 3.5 GHz and the band selection is achieved by either mixing the input signal with the fundamental or thirdorder harmonic component of LO2. The IF amplifier is used to filter out higher unwanted frequency components, drive the high input capacitance of the switchable harmonic mixer, and provide higher gain at the upper band to compensate the 9-dB systematic gain difference between the lower and upper bands due to SWHM as discussed later in this section. The basic idea of the band selection is to adjust the harmonics of the second mixing stage. If the 24-GHz band is desired, the second mixing stage mixes the input signal with the 3.5-GHz fundamental component, and the third-order harmonic component at 10.5 GHz is suppressed. On the other hand, if the 31-GHz

3 EL-NOZAHI et al.: MM-WAVE (24/31-GHZ) DUAL-BAND SWITCHABLE HARMONIC RECEIVER 2719 band is desired, the fundamental component of the second oscillator is suppressed and the third harmonic component, at 10.5 GHz, is amplified. Since the architecture is based on a heterodyne scheme, the LNA should provide image rejection to achieve a high signal-to-noise ratio (SNR) from the received data. If the image rejection provided by the LNA is not sufficient for the necessary rejection, an external bandpass filter (such as a switchable RF microelectromechanical-system (MEMS) filter at GHz similar to the one reported in [15]) can be added in front of the receiver to remove unwanted image signals that are placed at 17 and 10 GHz for the 24- and 31-GHz frequency bands, respectively. To demonstrate the advantage of the proposed receiver architecture, it is compared to one of the existing Weaver-based dualband receivers [14]. The Weaver-based architecture requires a LO running at 27.5 GHz compared to one running at 20.5 GHz in the proposed architecture. Having a lower oscillating frequency reduces the power consumption while achieving better phase noise. For the second mixing stage, both architectures are using the same LO frequency. Another advantage is that the Weaver architecture requires two mixers operating at 27 GHz compared to a single mixer operating at 20.5 GHz, thus reducing the power consumption as well as the complexity in the layout due to the coupling among various components. It is important to mention that both architectures require a tuning scheme, such as least mean square (LMS), to efficiently reject one of the bands and receive the desired one [14]. In this implementation, two control lines are used for external tuning (Fig. 1). The first one adjusts the phase error, while the other one adjusts the gain error. Fig. 3. Basic idea of the switchable harmonic mixer. where,, and are the amplitudes of the three different waveforms, and and are phase shifts. In these equations, is selected as the reference signal and, therefore, 0. The effective mixing signal is generated by summing the three waveforms as follows: With assumptions of and, the effective mixing signal can be written as follows: (2) B. Switchable Harmonic Mixer Mathematical Analysis The switchable mixer mixes the input signal at 3.5 or 10.5 GHz with either or, respectively. Fig. 3 demonstrates the basic idea of the switchable mixer, where a single LO source with three different phases is required to mix the input signal with the fundamental or the third-order harmonic, and suppress unwanted components. The three waveforms are considered square waves because this is the effective signal seen by any Gilbert-cell-based mixer. The fundamental or third harmonic components cancellation is achieved by summing the three LO signals, with proper phase and amplitude scaling. Using Fourier series analysis, the three waveforms are written in terms of their first five harmonics as follows: (1) The fundamental or the third harmonic component in (3) are eliminated by adjusting the values of amplitudes and phases of three waveforms. Several amplitudes and phases can perform this functionality. Fig. 4 shows the required amplitude ratio for each value of to cancel either the fundamental or the third harmonic component. Among these solutions, three practical sets are selected. Table I summarizes coefficients and component values for these sets. For the proposed receiver, the first set is selected because it reduces the hardware complexity. For this set, only the phase of controls the band selection by changing its polarity. The lower frequency band is selected by tuning the switchable harmonic mixer for, and the upper frequency band is selected by adjusting the mixer to. On the other hand, Sets 2 and 3 require a polarity and amplitude change of to perform the band selection, and add to the complexity of the receiver implementation. Another advantage of selecting the 45 phase shift is in the Q-mixer implementation shown in Fig. 1. Only an additional 90 phase shift is required for the signal. The 90 is inherently generated for the and signals. This is because shifting by 90 provides the inverted signal of, which is already used to drive the I-mixer. This (3)

4 2720 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 TABLE I COEFFICIENTS VALUES OF THE SWITCHABLE HARMONIC MIXER FOR TWO POSSIBLE COMBINATIONS (A = A ) Fig. 4. Phase and amplitude conditions for the fundamental or third harmonic component cancellation. gain difference of 9 db between the fundamental and the third harmonic component. This systematic gain difference is adjusted by using the IF amplifier, to provide a flat gain for both frequency bands. Having an almost constant gain for both bands reduces the overall power consumption by relaxing the noise figure and IIP3 requirements of the following blocks [16]. The idea of harmonic rejection/selection is verified using SIMULINK 1 simulations and results are shown in Fig. 5. As depicted, the third and fundamental components are suppressed by adjusting the proper values of coefficients. Higher order harmonics are easily filtered out by using a low-pass filter in the baseband section. The proposed switchable harmonic receiver is not limited to the fundamental or the third-order harmonic components, and can be applied to higher order harmonics. C. Frequency Planning The proposed dual-band switchable harmonic receiver architecture can be employed to downconvert any arbitrary pair of frequency bands by properly selecting the frequencies of the LOs. A general approach to determine the operating frequencies of the two LOs is derived, and the resulting equations are as follows: (4) Fig. 5. Simulated spectrum of I using Simulink when the third harmonic component (top) or fundamental component (bottom) is cancelled using the information of Set 1 in Table I. is not the case for Sets 2 and 3 and, therefore, the 45 phase shift relaxes the receiver complexity. Table I also shows the conversion gain of the mixer for each frequency component. For Set 1, there is a systematic where and are frequencies of the LO shown in Fig. 1, and and are the lower and upper frequencies of the two desired bands. For the 24- and 31-GHz bands, and are 20.5 and 3.5 GHz, respectively. In this architecture, is further reduced to GHz by using a frequency doubler to reduce the power consumption of the LO generation circuitry. In this receiver, the total RF band bandwidth is less than 250 MHz and, therefore, the third harmonic of LO1 at GHz is not important. However, if the targeted application bandwidth is higher than 250 MHz, then the frequency doubler may not be used and, hence, has to be 20.5 GHz. Another example for the frequency planning is the WiFi standards at 2.4 and 5.2 GHz. In this case, and have to be 1 and 1.4 GHz, respectively. D. Sensitivity to Parameter Mismatch The amount of the undesired harmonic rejection depends on the matching between various parameters in Table I. A mismatch analysis is performed to investigate the effect of process 1 SIMULINK:

5 EL-NOZAHI et al.: MM-WAVE (24/31-GHZ) DUAL-BAND SWITCHABLE HARMONIC RECEIVER 2721 variations on the amount of rejection, and shows the importance of having an automatic tuning scheme for this architecture. Both amplitude and phase mismatches are considered. The amount of rejection is defined as the ratio of the unwanted harmonic of to the desired one. Assuming that the third harmonic component is rejected, the unwanted component is given by (5) where and are amplitude mismatches, and and are phase mismatches of and. In (5), the component of is selected as the reference, and mismatch variations are assumed to happen to the components of and. In the ideal case of infinite rejection, should be zero, and this is achieved if,,, and. By applying the condition of ideal rejection to (5) and after some mathematical simplifications, is approximated as follows: Fig. 6. Worst-case rejection for amplitude and phase mismatches of 2% and 2, respectively. worst-case rejection in this case is higher than 28 db. Phase and amplitude tuning schemes can increase the amount of rejection to values higher than 55 db, similar to the tuning scheme used in the Weaver architecture [14]. In addition, the external GHz RF MEMS-switchable bandpass filter provides part of the rejection. Combining both rejection values results in high rejection that is sufficient to obtain the required high signal-to-noise ratio (SNR). III. CIRCUIT IMPLEMENTATION The total power of is obtained by summing the square value of coefficients of sine and cosine functions in (6) as follows: Finally, the rejection ratio of the unwanted third harmonic component to the fundamental one is given by where is the amplitude of the fundamental component. A similar analysis can be performed for the case of the fundamental component cancellation to find. Equations (6) (8) indicate that the amount of the rejection is a function of amplitudes and phases of the original waveform. In addition, these mismatches can add together to worsen the amount of rejection. Fig. 6 shows the worst-case rejection versus the value of for and using system-level simulations. The worst-case rejection is when all mismatches are added coherently. In this simulation, an amplitude mismatch of 2% for and, and a phase mismatch of 2 for and are considered. The simulations in Fig. 6 indicate that the worst-case rejection depends on the selected value of amplitudes and phases, which are determined from Fig. 4. The lowest value of is for, while the lowest value of is for. In this implementation, is selected to be 45 because it reduces the receiver complexity as mentioned earlier in Section II-C. The (6) (7) (8) A. Wideband LNA A two-stage wideband low-noise amplifier (LNA) is used to amplify both bands at 24 and 31 GHz. The wideband LNA architecture is shown in Fig. 7 and the circuit element values are summarized in Table II [17]. In this architecture, a wideband input-matching network is designed using inductors and. The input-matching network is similar to the narrowband approach at the low-gigahertz range [18]; however, the same components can be used for wideband matching at mm-wave frequencies using BiCMOS technology. This is because the quality factor of the input-matching network decreases at higher frequencies, hence allowing for wider matching at the input. The wideband gain is obtained by using a coupled resonator as the load of each amplifier stage. Coupled resonators can result in two peaks depending on their coupling coefficient. Cascading two of these coupled resonators (,,, and,, and ) with unequal peaking frequencies, results in a wideband response [17]. Two gain stages with two different coupled-resonator loads are implemented to provide the wideband response for the proposed LNA. In addition, these two stages increase the voltage gain across the desired wideband frequency range. The loading effect of the second stage and the routing parasitics, including capacitance and inductance, are considered during the design of the first stage. This concept is verified using postlayout simulations and the results are shown in Fig. 8 for the voltage gain and reflection coefficient. The LNA has a voltage gain of 12 and 11 db for 24- and 31-GHz frequency bands, respectively. Also, simulations show a reflection coefficient better than 12 db for both frequency bands. The LNA provides an image rejection of

6 2722 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 Fig. 9. Schematic of the wideband mm-wave mixer. Fig. 7. Schematic of the wideband mm-wave LNA. TABLE II CIRCUIT ELEMENT VALUES FOR THE IMPLEMENTED LNA Fig. 8. Postlayout simulated gain and an input reflection coefficient of a wideband LNA. 22 and 47 db for the image frequencies at 10 and 17 GHz, respectively. The noise due to the cascode transistor is reduced by adding the inductor to resonate with the parasitic capacitance at the emitter of [6], [8], [19]. Hence, the emitter of is degenerated with high impedance, and the noise current of is not injected to the output of the first stage. Instead, the noise current will circulate within. is added to decrease the dc current through ; hence reducing its size and associated parasitics. This technique results in a worst-case noise figure of 6 db at the 31-GHz frequency band. The IIP3 of this architecture is better than 6 dbm. All of the aforementioned techniques enable the design of an LNA with a large and high gain, low wideband input-referred noise, and low power consumption of 15 mw from a 1.8-V supply. B. Wideband MM-Wave Mixer The mm-wave mixer downconverts the 24- and 31-GHz bands to 3.5 and 10.5 GHz intermediate-frequency (IF) frequency, respectively. This mixer should provide a constant gain for the two bands to relax the noise figure and IIP3 requirements of the following blocks [16]. As a result, the mixer should have at least 7 GHz of 3-dB IF-bandwidth. All of the reported mixers in the literature have an IF bandwidth not more than 3.5 GHz within the -band [21] [26]. Implementing the mm-wave mixer using a conventional mixer is not possible because of the internal parasitics that limit the IF-bandwidth to few gigahertz. To increase the IF-bandwidth of the conventional mixer, the size of LO switches and the value of load resistance have to be reduced to push the parasitic poles to higher frequencies. This comes at the cost of reducing the conversion gain and increasing the noise figure. In addition, the conventional mixer requires an LO running at 20.5 GHz, which means increasing the power consumption of the LO and degrading its phase noise. In this receiver, the frequency doublers are used to reduce the operating frequency of LO to GHz. This approach reduces the power consumption of the LO, and provides better isolation in addition to reducing the LO self-mixing problem [20]. Fig. 9 shows the proposed wideband mm-wave mixer and the circuit element values are summarized in Table III. The mixer consists of two frequency doublers and a mixing stage ( and ). The LO signal, running at GHz, with four phases (0,90, 180, and 270 ) is injected into the gate of frequency doublers. The required four phases are generated from an external differential LO signal using an on-chip LC phase shifter. Twice the LO frequency (20.5 GHz) appears at the source of ( and ). Both signals at and are out of phase. The inductor is added to resonate with the parasitic capacitance for increasing the swing at and. As a result, increases the conversion gain and lowers the noise figure of the mixer. Fig. 10 shows and of the doubler versus the injected. To fully switch the BJT transistors, and have to be around 100 mv, which is adjusted by applying a 300-mV LO signal at the doubler input according to Fig. 10. To extend the IF bandwidth, the pi-network consisting of (,, and ) is introduced. Without the pi-network, the mixing stage is similar to the conventional active mixer. For the conventional mixer, the gain drops by 40 db/dec for high IF frequencies because of internal parasitic capacitance. These parasitic capacitances result in two real poles one at the emitter of and

7 EL-NOZAHI et al.: MM-WAVE (24/31-GHZ) DUAL-BAND SWITCHABLE HARMONIC RECEIVER 2723 Simulated output swing versus the input voltage amplitude of the dou- = 1 ma). Fig. 10. bler (I TABLE III CIRCUIT-ELEMENT VALUES FOR THE IMPLEMENTED WIDEBAND mm-wave MIXER Fig. 11. Postlayout simulations of the conversion gain and gains of RF and IF sections in the wideband mm-wave mixer. the other at the output node; hence, the IF bandwidth is limited. The pi-network results in two complex poles that are adjusted to produce peaking. This peaking is aligned with the output pole to extend the operating bandwidth. Extending the bandwidth using this approach introduces inband ripples, which are adjusted using the quality factor of the complex pole. The quality factor and the location of the two poles are specified by the component values of the pi-network (,, and ). Reducing,,or increases the bandwidth and inband ripples and lowers the conversion gain. In this design, inband ripples of 0.3 db are considered and the IF bandwidth is adjusted to 13 GHz through. The IF bandwidth is limited to 13 GHz to avoid downconverting the noise at higher frequencies in the second mixing stage. Table III summarizes the component values for the mixer including the pi-network. Depending on the parasitic of and in Fig. 9 is not enough to implement the required quality factor of the complex poles and, therefore, and are implemented using MOM capacitors. This idea of extending the bandwidth is demonstrated through postlayout simulations, and Fig. 11 shows the overall conversion gain and gains of the RF and IF sections in the mixer. As depicted, input signals above the mixing frequency (20.5 GHz) exhibit a peaking of 10 db at 31 GHz. After the mixing operation, this peaking appears at an IF frequency of 10.5 GHz, and it cancels the degradation in conversion gain due to the output pole. In this design, the output pole appears at 5 GHz. This approach shows a simulated 3-dB IF bandwidth of 13 GHz with a conversion gain of 4 db, which is difficult to achieve without the pi-network. Another important feature of the pi-network is that it does not amplify the image frequencies at 17 and 10 GHz by the same amount as the required bands at 24 and 31 GHz. This Fig. 12. Postlayout simulations of noise figure versus the output IF frequency of the wideband mm-wave mixer. is because the peaking occurs mainly in the upper side of the LO frequency. The image signals at 17 and 10 GHz are downconverted with a conversion gain of 1 and 6 db, respectively. Combined with the image rejection (IR) provided by the LNA, the total IR is 27 db and 57 db for 17 and 10-GHz image frequencies without the effect of the external mm-wave filter. Finally, the size of main transistor is maximized based on the maximum capacitance that can be loaded by the LNA. BJT switches are used because they require an LO with lower voltage swing. The mixer shows a simulated noise figure of 12.7 db and 10.4 db for the 24-GHz and 31-GHz bands as shown in Fig. 12. Simulated LO-to-RF (20.5 GHz to RF) isolation is higher than 45 db. The mixer and the frequency doublers consume 10 ma from a 1.8-V supply. C. Switchable Harmonic Mixer and IF Amplifier This section discusses the implementation of the switchable harmonic mixer and its supporting circuits, including the IF amplifier and polyphase generation circuitry. 1) Switchable Harmonic Mixer: Fig. 13 shows the implementation of the switchable harmonic mixer, which is similar to the implementation in [27] used in a highly linear transmitter. The mixer in Fig. 13 consists of three Gilbert-cell mixers each driven with an LO signal having a different phase. According to Table I, the middle mixer provides a conversion gain times higher than the other two mixers. This is achieved by scaling the

8 2724 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 Fig. 13. Architecture of the switchable harmonic mixer. The selection of either the fundamental or the third-order harmonic component is achieved by changing the phase of the middle mixing stage. transconductance value of to a value of times higher than the transconductance value of and. This is achieved by increasing the biasing current through the transistor and its size. Only increasing the size of increases the parasitic capacitance at its drain and, hence, attenuates the signal close to 10.5 GHz. The current of the middle mixing stage can be adjusted in an automatic tuning scheme, which is not implemented in this receiver, to overcome the finite amount of rejection of the unwanted band due to process mismatches and variations. NMOS RF transistors are chosen for the RF input stage to minimize the loading on the preceding stage in the receiver. Also, they have the advantage of better linearity compared to bipolar junction transistors (BJTs), which need some linearization technique and make the matching between the three mixing cells a harder design problem. The biasing transistors,, and are designed to be large enough to reduce the overdrive voltage for higher voltage headroom, and to help increase the matching between the devices. BJTs are used for the LO input stage to minimize the flicker noise of the switches. In addition, bipolar transistors require a small LO signal amplitude 100 mv) for switching. The number of base fingers of each bipolar transistor is increased to reduce its generated output noise. The PMOS current steering technique is used to increase the conversion gain and available headroom as shown in Fig. 13. Current steering is implemented through the transistor and resistor. This is because the output dc voltage is determined by the gate overdrive voltage of PMOS devices. During ac operation, the passive resistor appears and controls the conversion gain. This technique does not require a common-mode feedback circuit since provides a local feedback to stabilize the output dc voltage. The area of PMOS transistors is increased to minimize their flicker noise contribution at the output. The flicker noise of,, and will be upconverted to [28]. Slight degradation in the linearity is observed due to the nonlinear output resistance of PMOS transistors. The LO signals are driven from the same source, and they have the same frequency of 3.5 GHz but are different in phase, according to Table I. This mixer provides downconversion of the signals at 3.5 and 10.5 GHz, which are the IF frequencies of 24- and 31-GHz frequency bands. The fundamental (3.5 GHz)/ third-order harmonic (10.5 GHz) selection is achieved by controlling the phase of the input LO signal of the middle mixer in Fig. 13. If the phase of LO signal is 0, then the fundamental component is selected while the third harmonic component is rejected. On the other hand, if the phase is 180, then the third harmonic component is selected and the fundamental one is rejected. This approach enables the use of a single switch to control the required band selection. 2) IF Amplifier: The proposed switchable harmonic mixer has a high input capacitance due to employing three mixing stages. This input capacitance can limit the performance of the previous stage (mm-wave mixer) at higher frequencies. Reducing the input capacitance comes at the cost of reducing the conversion gain and increasing the noise figure. To overcome this problem, an IF amplifier is located between the mm-wave and switchable harmonic mixers as a buffer. This amplifier, shown in Fig. 14, employs shunt peaking to provide higher gain at the 10.5-GHz band. Fig. 15 shows the simulated gain and noise figure of the IF amplifier. The IF amplifier provides gain of 6 db and 7.7 db, and a noise figure of 12.3 db and 10.5 db for 3.5 GHz and 10.5 GHz, respectively. The higher gain at the 10.5-GHz band is necessary to compensate for the systematic gain difference of 9 db between the two bands as pointed out in Table I and the gain reduction due to the parasitic capacitances. The 6-dB loss at 3.5 GHz is not problematic because the mixer has higher gain at this band. Increasing the size of the input transistor in Fig. 14 to avoid the 6-dB loss is not possible because it would lower the gain of the previous stage. The cascode architecture is used to ensure stability of the amplifier. 3) Polyphase Shifter: A two-stage polyphase shifter, shown in Fig. 16, is used to generate the required phase shifts precisely with the drawback of 3-dB loss [29]. Simulations across the process corners show a precise phase shift of 90 between nodes and in Fig. 16 as long as nodes 1 and 2 are not loaded. The 0 /180 phase shifts are taken from the main LO input signal (, ) to reduce the loading on nodes 1 and 2, and they are injected to a multiplexer. The control line of this multiplexer determines the desired band. Due to the additional multiplexer, the phase shift is not 0 /180, and an additional RC phase shifter, shown in Fig. 17, is added to reduce

9 EL-NOZAHI et al.: MM-WAVE (24/31-GHZ) DUAL-BAND SWITCHABLE HARMONIC RECEIVER 2725 Fig. 14. IF amplifier with shunt peaking (W=L = 27/0.18, W=L = 19/0.18, R = 25, L = 1.1 nh}). Fig. 16. Two-stage polyphase shifter (R = 200, C = 230 ff). Fig. 17. RC phase shifter with electronic tuning (R = 170, C = 260 ff, including loading parasitics). Fig. 15. Post-layout simulations of the conversion gain and noise figure of IF amplifier. the amount of phase mismatch. The resistance is externally controlled through the transistor to account for the phase mismatch between and that are generated due to process variations. In addition, this phase shifter reduces the amplitude of, so that the driving amplitude of the switches is the same for the three mixers for better matching. The capacitor is chosen to double the value of the capacitor of the polyphase filter to almost have the same amplitude for all LO output signals. The phase control voltage in Fig. 17 can be used in an automatic tuning scheme to provide the necessary phase correction and, hence, increase the amount of rejection of the unwanted band. Fig. 18 shows the variation of the output phase of versus. 4) Possible Automatic Tuning Implementations: Manual tuning is used for the implemented-switchable harmonic mixer. However, possible implementations of the phase and amplitude automatic tuning circuits are demonstrated. An implementation for automatic phase tuning is shown in Fig. 19. In this scheme, and are sensed and multiplied separately with, yielding a dc component proportional to the phase shift. The difference between the two multiplication operations is then integrated and the output of the amplifier holds the voltage required for. At steady-state condition, both multiplications lead to the same output and, therefore, the integrator holds the required voltage for tuning. This scheme adjusts exactly in between and. The 90 Fig. 18. Output phase variation of LO2 versus V of the circuit in Fig. 17. phase shift between and is guaranteed by the polyphase shifter. For amplitude tuning, the calibration loop in Fig. 20 could be used. Considering the rejection of the 3.5-GHz band, a low-frequency test tone, less than 10 MHz, is upconverted using the 3.5-GHz LO2 signal, yielding a tone at 3.5 GHz. This signal is injected to the SWHM which downconverts it back to baseband. In this case, the SWHM is tuned to downconvert the 10.5-GHz band, and ideally, no signal should appear at the output. A bandpass filter tuned at filters out the downconverted signal, which is mixed with the original tone, resulting in a dc level proportional to the finite rejection. The dc level is compared to zero, which is the level corresponding to

10 2726 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 Possible implementation of the automatic phase-tuning control cir- Fig. 19. cuitry. Fig. 22. Postlayout simulations of the switchable harmonic mixer and IF amplifier noise figure for the 3.5- and 10.5-GHz frequency bands versus the LO2 voltage amplitude. Fig. 20. Possible implementation of an automatic calibration loop for amplitude tuning. Fig. 23. Postlayout simulations of the switchable harmonic mixer and IF amplifier IIP3 for the 3.5- and 10.5-GHz frequency bands versus the LO2 voltage amplitude. Fig. 21. Postlayout simulations of the switchable harmonic mixer and IF amplifier conversion gain for the 3.5- and 10.5-GHz frequency bands versus the LO2 voltage amplitude. infinite rejection. Finally, a successive approximation algorithm adjusts the amplitude control signal to the required level. In the case of the 10.5-GHz signal, a frequency tripler is used to generate a 10.5 GHz tone. The SWHM is adjusted for the 3.5-GHz band, and the bandpass filter is tuned at. Mixing the downconverted tone with the original tone also produces a dc level that is proportional to the finite rejection, which is used by the successive approximation algorithm to adjust the amplitude control signal. 5) IF Amplifier and Switchable Harmonic Mixer Simulation Results: The postlayout simulation results for the conversion gain, noise figure, and IIP3 of the combined switchable harmonic mixer and IF amplifier versus the amplitude of LO2 are shown in Figs , respectively. In this design, the voltage of is adjusted to 100 mv to provide sufficient gain and reduce the noise figure of the 10.5-GHz band. At this amplitude, there is degradation of IIP3 at the 3.5-GHz band; however, it is higher than the one at 10.5 GHz. Also, simulations show LO-to-RF and 3LO-to-RF isolations of SWHM higher than 100 db, which is expected due to the differential nature of the SWHM mixer. The conversion gain versus the baseband frequency for the 3.5- and 10.5-GHz frequency bands is shown in Fig. 24. The mixer has a conversion gain of 6.7 and 5.2 db for the 3.5- and 10.5-GHz bands, respectively. Only 1.5-dB difference in gain is achieved due to the effect of the gain peaking introduced by the IF amplifier. The conversion gain varies by 1 db across the amplitude tuning range. Simulations also showed a rejection higher than 60 db. This value is hard to achieve without a tuning scheme in the measurement as mentioned in Section II-D and will be shown in Section IV. A simulated noise figure of 17.1 and 18 db at baseband are obtained for the 3.5- and 10.5-GHz frequency bands, respectively. The 10.5-GHz band has slightly higher noise figure due to the additional losses. The IIP3 of the mixer and IF amplifier is 7 and 1 dbm for the 3.5- and 10.5-GHz band, respectively. Simulations are performed with a two-tone separation of 10 MHz. The IIP3 at 10.5 GHz is lower due to the effect of the higher gain introduced by the shunt peaking IF amplifier. However, the 1 dbm IIP3 is still within the required specification.

11 EL-NOZAHI et al.: MM-WAVE (24/31-GHZ) DUAL-BAND SWITCHABLE HARMONIC RECEIVER 2727 Fig. 24. Post-layout simulations of switchable harmonic mixer and IF amplifier conversion gain for the 3.5- and 10.5-GHz frequency bands versus the baseband frequency. Fig. 27. Measured and simulated S for the dual-band receiver. Fig. 25. Die photo of the switchable harmonic receiver. Fig. 28. Measured conversion gain and rejection of the proposed switchable harmonic receiver (V = 0.25 V). Fig. 26. PCB for the switchable harmonic receiver. The total current consumptions of the SWHM and IF amplifier are 8 ma and 7 ma from a 1.8-V supply, respectively. IV. EXPERIMENTAL RESULTS The switchable harmonic receiver is fabricated using 0.18 m BiCMOS technology provided by Jazz Semiconductor. The cutoff frequency of this technology is 70 and 50 GHz for the BJT and MOS transistors, respectively. The die micrograph is shown in Fig. 25, where the total area is 0.7 mm, excluding pads. An FR-4 printed-circuit board (PCB), shown in Fig. 26, is designed to test the dual-band receiver. The PCB is used to apply the dc signals, monitor the low-frequency output, and apply the LO signals. The chip is packaged in a quad flat-no-lead (QFN) package. The input signal is injected using a GSG RF probe to avoid degrading the performance of the receiver. The output of the receiver is applied to an off-chip instrumentation amplifier for the differential-to-single-ended conversion necessary for the measurements. The 3.5- and GHz LO signals are applied externally and injected to the chip through SMA connectors. An Agilent N5230A network analyzer is used to inject the mm-wave signal and to measure the reflection coefficient of the LNA. LO signals are applied using the HP-8673C signal generator and HP 8719ES network analyzer.

12 2728 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 Fig. 30. Measured rejection versus phase control voltage V 31- or 24-GHz band is rejected. when the TABLE IV CIRCUIT ELEMENT VALUES FOR THE IMPLEMENTED-SWITCHABLE HARMONIC MIXER Fig. 29. Measured rejection in the baseband when (a) the 24-GHz band or (b) the 31-GHz band is selected. The measured reflection coefficient of the receiver is shown in Fig. 27. A reflection coefficient of better than 12 db is obtained for the two frequency bands. The overall measured conversion gain versus the baseband frequency (dc-15 MHz) for 24- and 31-GHz frequency bands is shown in Fig. 28. These plots are obtained by measuring the output signal using the HP 3588A spectrum analyzer and substracting the gain of the instrumentation amplifier. An overall conversion gain of 21 and 18 db is measured for the 24- and 31-GHz frequency bands, respectively. Fig. 29 shows the spectrum of the output signal for various conditions. Fig. 29(a) demonstrates the case where the 24-GHz band is selected and the 31-GHz band is rejected, while Fig. 29(b) presents the opposite scenario. In this measurement, the 24- and 31-GHz input signals are adjusted to have the same amplitude. Measurements show a rejection of the unwanted signal better than 43 db for two different cases after manual tuning of the phase and amplitude mismatches 1.26 V). The widening in the downconverted 31 GHz is due to the Agilent N5230A network analyzer that is used to generate the 31-GHz input signal. This network analyzer generates the widened spectrum shown in Fig. 29(b) at the input of the receiver and, therefore, the same shape appears at the output. The simulation results show a rejection of better than 60 db. The discrepancy is mainly due to mismatches, inaccurate models, and substrate coupling. Automatic tuning schemes can be applied later for this dual-band receiver to increase the amount of rejection. Fig. 30 shows the measured rejection versus the phase control voltage when the amplitude control (Fig. 13) is kept at its default value. As depicted, optimum values of phase control voltage for maximum rejection of 24- and 31-GHz bands are 1.3 and 1.24 V, respectively. Optimum values are different for the two bands because the mismatches and process variations have a different impact on the rejection for the fundamental and third-order harmonic components. This optimum value can be obtained by using an automatic tuning scheme. Nonlinearity measurements are performed for the 24- and 31-GHz frequency bands. The dc-40 GHz Agilent N5230A network analyzer and 60-GHz Anritsu MG3696 signal generator are used as the input sources. The two input signal tones are applied with a separation of 1.2 MHz. The main output signals tones are at 7 and 8.2 MHz and the third-order intermediation signal appears at 5.8 and 9.4 MHz. For the input signal at 24 GHz, the measured output spectrum shows a difference between the main tones ( 19-dBm output) and the third-order intermodulation tone of 44 db. This results in an output-referred third-order intercept point (OIP3) of 3 dbm equivalent to an input-referred IIP3 of 18 dbm. Similar steps are performed for the 31-GHz input signal, and an IIP3 of 17 dbm is obtained. The noise figure of the implemented receiver front end is obtained by measuring the output noise level using a spectrum analyzer and, hence, estimating the input-referred noise. A measured noise figure of 8 and 9.5 db is obtained for the 24- and 31-GHz band, respectively. The complete dual-band receiver consumes 60 mw from a 1.8 V. Finally, the measured performance summary of the switchable harmonic receiver and its building blocks is shown in Table V.

13 EL-NOZAHI et al.: MM-WAVE (24/31-GHZ) DUAL-BAND SWITCHABLE HARMONIC RECEIVER 2729 TABLE V DUAL-BAND-SWITCHABLE HARMONIC RECEIVER MEASURED PERFORMANCE SUMMARY V. CONCLUSION A dual-band-switchable harmonic receiver architecture is introduced in this paper. Mathematical formulation and frequency planning of the receiver are provided. Mismatch analysis shows that a 2% variation in the amplitude and a phase shift of 2 reduces the amount of rejection of the unwanted band to 28 db. However, automatic tuning can increase the amount of rejection. A prototype is fabricated using m BiCMOS technology with 0.7 mm of chip area. The receiver is implemented for the ISM and LMDS bands at 24 and 31 GHz, targeting the IEEE standard. Measurements show a band rejection higher than 43 db, gain higher than 18 db, NF lower than 9.5 db, and an IIP3 higher than 19 dbm. The receiver consumed 60 mw from a 1.8-V supply. ACKNOWLEDGMENT The authors would like to thank Jazz Semicondutor for chip fabrication. REFERENCES [1] X. Guan and A. Hajimiri, A 24-GHz CMOS front-end, IEEE J. Solid- State Circuits, vol. 39, no. 2, pp , Feb [2] B. Razavi, A 60 GHz CMOS receiver front-end, IEEE J. Solid-State Circuits, vol. 41, no. 1, pp , Jan [3] X. Guan, H. Hashemi, and A. Hajimiri, A fully integrated 24-GHz eight-element phased array receiver in silicon, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [4] E. Ragonese, A. Scuderi, V. Giammello, E. Messina, and G. Palmisano, A fully integrated 24 GHz UWB radar sensor for automotive applications, in Proc. IEEE Intl. Solid-State Circuits Conf. Dig., Feb. 2009, pp [5] B. Floyd, S. Reynolds, U. Pfifer, T. Beukema, J. Gryzb, and C. Haymes, A silicon 60 GHz receiver and transmitter chipset for broadband communications, in Proc. IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2006, pp [6] B. Razavi, A millimeter-wave CMOS heterodyne receiver with on-chip LO and divider, IEEE J. Solid-State Circuits, vol. 43, no. 2, pp , Feb [7] C. Marcus et al., A 90 nm low-power 60 GHz transceiver with integrated baseband circuitry, in Proc. IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2009, pp [8] B. Afshar, Y. Wang, and A. Niknejad, A robust 24 mw 60 GHz receiver in 90 nm standard CMOS, in Proc. IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2008, pp [9] A. Parsa and B. Razavi, A 60 GHz receiver using 30 GHz LO, in Proc. IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2008, pp [10] Y. Kawano, T. Suzuki, M. Sato, T. Hirose, and K. Joshin, A 77 GHz transceiver in 90 nm CMOS, in Proc. IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2009, pp [11] A. Babakkhani, X. Guan, A. Komijani, A. Natarajan, and A. Hajimiri, A 77 GHz 4-Element phased array receiver with on-chip dipole antenna in silicon, in Proc. IEEE Int. Solid-State Circuits Conf. Dig., Dec. 2006, pp [12] V. Jain, F. Taeng, and P. Heydari, A single-chip dual-band GHz/77 81 GHz BiCMOS transceiver for automotive radars, in Proc. IEEE Intl. Solid-State Circuits Conf. Dig., Feb. 2009, pp [13] IEEE Standard for Local and Metropolitan Area Networks, Part 16: Air Interface for Fixed Broadband Wireless Access Systems, IEEE Standard , [14] L. Der and B. Razavi, A 2-GHz CMOS image-reject receiver with LMS calibration, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp , Feb [15] K. Entesari and G. M. Rebeiz, A GHz 3-Pole RF MEMS tunable filter, IEEE Trans. Microw. Theory Tech., vol. 53, no. 8, pp , Aug [16] M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, Power aware multi-band/multi-standard CMOS receiver system-level budgeting, IEEE Trans. Circuits Syst.. II, Exp. Briefs, vol. 56, no. 7, pp , Jul [17] M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, A millimeterwave (23 32 GHz) wideband BiCMOS low noise amplifier, IEEE J. Solid-State Circuits, vol. 45, no. 2, pp , Feb [18] D. K. Shaeffer and T. H. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-State Circuits, vol. 32, no. 5, pp , May [19] M. Zargari, S. Jen, B. Kaczynski, M. Lee, M. Mack, S. Mehta, S. Mendis, K. Onodera, H. Samavati, W. Si, K. Singh, A. Tabatabaei, M. Terrovitis, D. Weber, D. Su, and B. Wooley, A single-chip dual-band tri-mode CMOS transceiver for ieee a/b/g wireless LAN, IEEE J. Solid-State Circuits, vol. 37, no. 12, pp , Dec [20] T.-Y. Yang and H.-K. Chiou, A 28 GHz sub-harmonic mixer using LO doubler in 0.18-m CMOS technology, in Proc. Radio Frequency Integrated Circuit Symp., San Francisco, CA, Jun [21] A. Verma, L. Gao, and K. K. O. J. Lin, A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-m CMOS technology, IEEE Microw. Wireless Compon. Lett., vol. 15, no. 8, pp , Aug [22] C.-S. Lin, P.-S. Wu, H.-Y. Chang, and H. Wang, A 9 50-GHz Gilbertcell down-conversion mixer in 0.13-m CMOS technology, IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp , May [23] F. Ellinger, GHz CMOS mixer, Electron. Lett., vol. 40, no. 22, pp , Oct [24] F. Ellinger, GHz resistive mixer in 90-nm VLSI SOI CMOS technology with high linearity for WLAN, IEEE Trans. Microw. Theory Tech., vol. 53, no. 8, pp , Aug

14 2730 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 [25] M. Bao, H. Jacobsson, L. Aspemyr, G. Carchon, and X. Sun, A 9 31-GHz subharmonic passive mixer in 90-nm CMOS technology, IEEE J. Solid-State Circuits, vol. 41, no. 10, pp , Oct [26] T.-Y. Yang and H.-K. Chiou, A GHz mixer using broadband multilayer balun in 0.18-m CMOS technology, IEEE Microw. Wireless Compon. Lett., vol. 17, no. 7, pp , Jul [27] J. A. Weldon, R. S. Narayanaswami, J. C. Rudell, L. Lin, M. Otsuka, S. Dedieu, L. Tee, K.-C. Tsai, C.-W. Lee, and P. R. Gray, A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp , Dec [28] H. Darabi and A. A. Abidi, Noise in RF-CMOS mixers: a simple physical model, IEEE J. Solid-State Circuits, vol. 35, no. 1, pp , Jan [29] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, CMOS mixers and polyphase filters for large image rejection, IEEE J. Solid-State Circuits, vol. 36, no. 6, pp , Jun Mohamed El-Nozahi (S 00) received the B.Sc. and M.Sc. degrees in electrical engineering from Ain Shams University, Cairo, Egypt, in 2000 and 2004, respectively, and the Ph.D. degree from Texas A&M University, College Station, TX, in From 2000 to 2004, he was a Teaching and Research Assistant with the Electronics and Communications Engineering Department, Ain Shams University. In 2007, he was a Design Intern with Texas Instrument Incorporated, Dallas, TX. In 2009, he was a Design Intern with Qualcomm Inc., San Diego CA. Since 2006, he has been with Marvell Semiconductor Inc., Santa Clara, CA, where he is a Senior RF Design Engineer. His research interests include transceivers system and circuit design at millimeter-wave frequencies and power management integrated circuits. Mr. El-Nozahi was the co-recipient of the 2009 Semiconductor Research Corporation (SRC) Design Challenge Award, and TI Excellence Fellowship from 2006 to Ahmed Amer (S 05) received the B.Sc. degree in electronics and communications (Hons.), and the M.Sc. degree in electronic engineering from Ain Shams University, Cairo, Egypt, in 2002 and 2006, respectively, and is currently pursuing the Ph.D. degree from Texas A&M University, College Station. From 2002 to 2006, he was a Teaching and Research Assistant in the Electronics and Communications Engineering Department at Ain Shams University. From 2004 to 2006 he was an RFIC design engineer with SysDSoft Inc., Cairo. During 2008 and 2009, he was an Intern in the medical group at Texas Instruments Incorporated, Dallas, TX. Mr. Amer was the co-recipient of the SRC/SIA Design Challenge Award in 2009, the Fouraker/Ebensberger Fellowship in 2007, and Texas Instruments Excellence Fellowship in 2008 and His research interests include powermanagement electronics, biomedical electronics, and wideband/multiband RF receivers design. Edgar Sánchez-Sinencio (F 92) was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, in 1966, the M.S.E.E. degree from Stanford University, Stanford, CA, in 1970, and the Ph.D. degree from the University of Illinois at Champaign-Urbana in His research work has more than 2650 citations according to the Thomson Reuters Scientific Citation Index. He has graduated 42 M.Sc. and 34 Ph.D. students. He is a coauthor of six books on different topics, such as RF circuits, low-voltage low-power analog circuits, and neural networks. Currently, he is the TI J. Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. His research interests are in the area of power management, RF communication circuits, as well as analog and medical electronics circuit design. Dr. Sánchez-Sinencio is a former Editor-in-Chief of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. Dr. Sánchez-Sinencio received the Honoris Causa Doctorate from the National Institute for Astrophysics, Optics and Electronics, Mexico, in This degree was the first honorary degree awarded for microelectronic circuit-design contributions. He is a Co-Recipient of the 1995 Guillemin-Cauer Award for his work on cellular networks. He was also the Co-Recipient of the 1997 Darlington Award for his work on high-frequency filters. He received the IEEE Circuits and Systems Society Golden Jubilee Medal in He also received the prestigious IEEE Circuits and Systems Society 2008 Technical Achievement Award. He was the IEEE Circuits and Systems Society s Representative to the IEEE Solid-State Circuits Society during He was a member of the IEEE Solid-State Circuits Society Fellow Award Committee from 2002 to He is a former IEEE Circuits and Systems Vice President-Publications. Kamran Entesari (S 03 M 06) received the B.S. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1995, the M.S. degree in electrical engineering from Tehran Polytechnic University, Tehran, in 1999, and the Ph.D. degree from the University of Michigan, Ann Arbor, in In 2006, he joined the Department of Electrical and Computer Engineering at Texas A&M University, College Station, where he is currently an Assistant Professor. His research interests include the design of radio-frequency/microwave/millimeter-wave integrated circuits and systems, RF microelectromechanical systems, related front-end analog electronic circuits, and medical electronics. Dr. Entesari was the Co-Recipient of the 2009 Semiconductor Research Corporation (SRC) Design Contest Second Project Award for his work on dual-band millimeter-wave receivers on silicon.