HDMI 1.4 Redriver Source-side Application

Transcription

1 HDMI.4 Redriver Source-side Application Features ÎÎHDMI TM.4 compliant re-driver ÎÎOperation upto.4 Gbps per lane (40MHz pixel clock) 4K x K 4Hz(97MHz) D Video formats(080p, 080i, 70p) ÎÎSupport up to 48-bit per pixel Deep Color TM ÎÎConvert low-swing DC or AC coupled differential input Open-drain current steering Rx terminated differential output Support Dual Mode DisplayPort source devices ÎÎProvide Output Squelch function to turn off TMDS common mode output buffer when TMDS clock is not present ÎÎBuilt-in Rx sense detection function ÎÎProgrammable equalizer, emphasis and amplitude settings to achieve optimized HDMI signal integrity ÎÎIntegrated Passive DDC level shifter.v source to 5V sink ÎÎIdle clock detection function for output squelch and auto standby ÎÎProgrammable input TMDS termination control (on or off) ÎÎ.V Power supply required ÎÎIntegrated ESD protection on I/O pins 8kV contact per IEC , level 4 8kV HBM ÎÎPackaging Pb-free & Green -contact TQFN (ZL)Description Application ÎÎNotebook computers and docking station ÎÎSet-Top Box(STB) ÎÎA/V Home entertainment systems ÎÎDongle and switch boxes Description PIHDMI5 is TMDS Redriver supporting HDMI.4 and DVI specifications up to a data rate of.4gbps with 48-bit per pixel Deep Color TM. It also support enhanced robust ESD/EOS protection of 8kV, which is required by many consumer video networks today. It converts the DC and AC coupled source devices into the HDMI compliant signal with proper signal swing, espically in the Notebook HDMI and Dual mode DP PC systems. Programmable termination settings at TMDS input help to avoid the compatibility issue caused by non standard HDMI source to determine the connection status of TMDS channel with proper termination voltage setting. With Pericom's intelligent power management techniques, the PIHDMI5 can automatically enter low power states when no valid signal presents on the TMDS link. Pin Configuration OUT_D0- VDD CEXT IN_D- IN_D+ IN_D- IN_D+ IN_D0- IN_D0+ IN_CLK- IN_CLK+ HPD_SRC GND PIHDMI5 TQFN SDA_SRC GND SCL_SRC /OE GND HPD_SINK TEST SDA_SINK OC_S0 SCL_SINK OUT_D+ VDD OUT_CLK- OUT_D- OUT_D+ OUT_D- OUT_D0+ OUT_CLK+ EQ_S0

2 Pin Description Pin # Pin Name Type Description CEXT PWR IN_D- I 4 IN_D+ I 5 IN_D- I 6 IN_D+ I 7 IN_D0- I 8 IN_D0+ I 9 IN_CLK- I 0 IN_CLK+ I LDO output for internal core supplier. External capacitor. to 4.7μF should be added to GND. TMDS inputs. R T =50 ohm HPD_SRC O HPD output; internal pull-down at 00K ohm SDA_SRC IO DDC Data on source side SCL_SRC IO DDC Clock on source side 5 Test I Must be tied LOW for normal operation 6 OC_S0 I 7 EQ_S0 I 8 OUT_CLK+ O 9 OUT_CLK- O 0 OUT_D0+ O OUT_D0- O OUT_D+ O 4 OUT_D- O 5 OUT_D+ O 6 OUT_D- O TMDS output pre-emphasis selection. See OC_S0 truth table for functionality. This pin has internal 00K ohm pull-up TMDS input equalization selection. If LOW or floating, EQ is set at 9dB for all TMDS data inputs If HIGH, EQ is set at 5dB for all TMDS data inputs (please note, TMDS clock inputs are always set to db EQ) This pin has an internal 00K ohm pull-down TMDS outputs. 7 SCL_SINK IO Sink side DDC Clock 8 SDA_SINK IO Sink side DDC Data 9 HPD_SINK I Sink side hot plug detector input; internal pull-down at 0K ohm. 0 /OE I Output Enable control. Active low. Internal 00K ohm pull-down. See truth table for functionality., VDD PWR.V power supply 4,, GND Ground Power Ground

3 Block diagram: CEXT HPD_SRC VDD LDO VDD 00K ohm 0K ohm HPD_SINK RX_CTRL RX_SENSE RT RT IN_CLK+/- IN_Dx+/- RXSEN TX OUT_CLK+/- OUT_Dx+/- Clock Detection VDD 00K ohm /OE Control Logic OC_S0 EQ_S0 00K ohm SCL_SRC SDA_SRC SCL_SINK SDA_SINK Description of Operation Squelch function: Squelch control is using low frequency signal detection. When TMDS input clock frequency is less than 0MHz, it will show no input signal. When input signal is not present, IC will enter power-down mode. Rx-sense detector: The PIHDMI5 will check 50 ohm termination resistor(r T ) within HDMI Rx chipset. If the R T =50 ohm is not present, we assume no valid HDMI Rx is connected. Therefore, IC will turn off our 50 ohm input termination resistor for all TMDS data and clock channels.when no valid R T = 50 ohm is detected in the HDMI Receiver, the IC will enter to the power-down mode. OC_S0 Truth Table TMDS Output Pre-emphasis Setting Note OC_S0 (internal pull-up) Single-end Vswing (mv) Pre-emphasis (db) (open drain) (open drain) For clock channel, pre-emphesis value is fixed to 0 db. TMDS Input Equalization Setting Note EQ_S0 Equalization (db) 0 9dB 5dB For CLK channel, the EQ value is fixed to db. /OE Truth Table /OE Operation 0 Normal Operation Mode Power Down Mode

4 Absolute Maximum Ratings Item Rating Supply Voltage to Ground Potential 5.5V All Inputs and Outputs -0.5V to V DD +0.5V Storage Temperature -65 to +50 C Junction Temperature 50 C Soldering Temperature 60 C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operation Conditions Parameter Min. Typ. Max. Unit Ambient Operating Temperature C Power Supply Voltage (measured in respect to GND).0..6 V DC Specification Parameter Parameter Conditions Min. Typ. Max. Unit V DD Operating Voltage. V I DD Idd_Squelch Idd_Rx Sense I stb V OL_HPD I OFF_HPD I OZ_HPD V DD Supply Current Supply Current in squelch mode supply current when no 50ohm detected in Rx Standby mode Open Drain Output Low Voltage Off leakage current Open drain Output leakage current Output Enable (open drain 500mV single-ended 0dB pre-emphasis) Input TMDS signal not valid, /OE = Low Input TMDS is valid, but 50ohm Rx Sense(RXSEN) is not detected /OE = Low V DD =.6V, HPD_SINK=0, /OE = High 0 50 ma ma 4 5 ma 4 5 ma I OL = 4 ma V V DD =0, V IN =.6V 0 V DD =0, V IN =5.5V 40 V DD =.6, V IN =.6V 0 V DD =.6, V IN =5.5V 40 µa 4

5 HPD_SINK I IH High level digital input current V IH =VDD 5 40 µa I IL Low level digital input current V IL = GND -0 0 µa V IH High level digital input voltage V DD =.V.0 V V IL Low level digital input voltage V Control Pin (/OE) I IH High level digital input current V IH =VDD 0 45 µa I IL Low level digital input current V IL = GND -0 0 µa V IH High level digital input voltage.0 V V IL Low level digital input voltage V DDC Channel Block C IO Input/Output capacitance V I peak-peak = V, 00 KHz 0 pf R ON On resistance I O = ma, V O = 0.4V 5 50 Ω V pass Switch Output voltage V I =.V, I I =00uA V DD =.V, External pull-up to VDD(5K ohm ~ 5K ohm) V Control Pins(OC_S0 with 00K ohm pull-up) I IH High level logic input current V IH =VDD 0 µa I IL Low level logic input current V IL =GND 5 50 µa Control Pins(EQ_S0 with 00K ohm pull-down) I IH High level logic input current V IH =VDD 5 50 µa I IL Low level logic input current V IL =GND 0 µa TMDS Differential Pins 5

6 V OH V OL V swing V OD(O) V OD(U) V OD(U) Single-ended high level output voltage Single-ended low level output voltage V DD -0 V DD +0 mv V DD -600 V DD -400 mv Single-ended output swing voltage mv Overshoot of output differential voltage () V DD =.V, Rout=50 ohm 80 mv Undershoot of output differential voltage () 00 mv Change in steady-state common-mode output voltage between logic Short Circuit output current - I OS Short Circuit output current at double termination mode -4 4 V I(open) Single-ended input voltage under high impedance input or open 5 mv I I = 0uA V DD -0 V DD +0 mv R T Input termination resistance V IN =.9V Ω I OZ Leakage current with Hi-Z I/O V DD =.6V, /OE=High 0 µa Note:. Overshoot of output differential voltage V OD(O) = (V SWING(MAX) * ) * 5%,. Undershoot of output differential voltage V OD(U) = (V SWING(MIN) * ) * 5% ma 6

7 AC Characteristics (Over recommended operating conditions unless otherwise noted) TMDS Differential Pins t pd t r t f Propagation delay Differential output signal rise time (0% - 80%) Differential output signal fall time (0% - 80%) V DD =.V, Rout = 50-ohm t sk(p) Pulse skew 0 50 t sk(d) Intra-pair differential skew 50 t sk(o) Inter-pair differential skew 00 t jit(pp) t jit(pp) Peak-to-peak output jitter CLK residual jitter Peak-to-peak output jitter DATA Residual Jitter Data Input =.65 Gbps HDMI data pattern CLK Input = 65 MHz clock t en Enable time 000 t dis Disable time 0 ps ps ns DDC I/O Pins (SCL_SRC, SCL_SINK, SDA_SRC, SDA_SINK) t pd(ddc) Propagation Delay C L = 0pF ns Control and Status Pins (HPD_SINK, HPD) t pd(hpd) Propagation Delay C L = 0pF, pull-up resistor=k ohm, Open drain output 0 ns 7

8 Packaging Mechanical: -Contact TQFN (ZL) DATE: 0/09/09 DESCRIPTION: -contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZL (ZL) DOCUMENT CONTROL #: PD-044 REVISION: A Please check for the latest package information on the Pericom web site at Pericom Semiconductor Corporation

9 Related DisplayPort/Dual Mode DisplayPort Products Part Number Product Description Availability PIHDMI0 DisplayPort. Re-driver with built-in AUX listener Now PIVDP40 Dual Mode DisplayPort to HDMI Level Shifter and Re-driver Now PIHDMI6.4G HDMI.4 Re-driver for Sink application, supporting Dual Mode DisplayPort Now PIVDP -Lane DisplayPort. Compliant Switch Now PIVDP4 4-Lane DisplayPort. Compliant Switch Now PIHDMI4AD : Active.4Gbps HDMI.4 compliant Splitter/Re-driver Now PIHDMI5 :.4Gbps HDMI.4 Switch/Re-driver with built-in ARC and Fast Switching support for Source Application Now PIHDMI6 :.4Gbps HDMI.4 Switch/Re-driver with built-in ARC and Fast Switching support for Sink Application Now PIHDMI6 : Active.4Gbps HDMI Switch/Re-driver with I C control and ARC Transmitter Now Reference Information Document AN VESA Description PIHDMI5 HDMI.4 Application Note VESA DisplayPort Standard Version Revision, Video Electronics Standards Association, January 5, 00 VESA DisplayPort Dual-Mode Standard Version, Video Electronics Standards Association, February 0, 0 VESA DisplayPort Interoperability Guideline Version.a, Video Electronics Standards Association, February 5, 009 HDMI High-Definition Multimedia Interface Specification Version.4, HDMI Licensing, LLC, June 5, 009 Ordering Information Ordering Number Package Code Package Description PIHDMI5ZLE ZLE Pb-free & Green -Contact TQFN Thermal characteristics can be found on the company web site at E = Pb-free and Green X suffix = Tape/Reel 9

10 Revision Histroy Date Changes 07/9/ Add Tr in the block diagram, IDD,Istb with Passive DDC level shifter. 0

11 Appendix A: Generic Application Information Eye Diagram Performance: Figure : Eye Diagram at 90x080p 48bit Deep Color with 48 Input Trace, 9dB Equalization, 500mV Swing,.5dB Preemphasis.

12 Measurement setup: Figure : Test Setup of AC-coupled TMDS Input Figure : Test Setup of DC-coupled TMDS Input

13 Application Information: Figure 4: Application Diagram For more detailed application information, please refer to PIHDMI5_HDMI_ApplicationInformation.doc.

14 Recommended Power Supply Decoupling Circuit Figure 5 is the recommended power supply decoupling circuit configuration. It is recommended to put a 0.μF decoupling capacitors on each VDD pin of our part. Four 0.μF decoupling capacitors are put in Figure 5 with an assumption of only four VDD pins on our part. On top of 0.μF decoupling capacitor on each VDD pin, it is recommended to put a 0μF decoupling capacitor near our part s VDD for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the power supply conditions of other circuits. Figure 5 Recommended Power Supply Decoupling Circuit Diagram 4

15 Requirements on the Decoupling Capacitors i: There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R. ii: 0.uF decoupling capacitor in 040 package is recommended. Layout and Decoupling Capacitor Placement Consideration i. Each 0.μF decoupling capacitor should be placed as close as possible to each VDD pin. ii. VDD and GND planes should be used to provide a low impedance path for power and ground. iii. Via holes should be placed to connect to VDD and GND planes directly. iv. The width between the traces should be as wide as possible. v. Trace length should be as short as possible. vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria. vii. 0μF capacitor should also be placed close to our part and should be placed in the middle location of 0.μF capacitors. viii. Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes, since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part. Figure 6 Layout and Decoupling Capacitor Placement Diagram 5

16 PIHDMI5 Appendix B: Evaluation Board Schematic and Layout 5 4 +V D C SHELL 0 CON_HDMI_Plug 0.u C04 +5V_A +5V 47K R0 JP0 47K R0 JP0 IN_D+ 4K7 R0 4.7u C0 0.u C0 0.u C0 C05 4.7u +V U0 /OE HPD_SINK SDA_SINK HGND GND GND OE/ 0 HPD_Sink 9 SDA_Sink 8 J0 D+ D SHIELD D- 4 D+ 5 D SHIELD 6 D- 7 D0+ 8 D0 SHIELD 9 D0-0 CK+ CK SHIELD CK- CEC 4 NC 5 SCL 6 SDA 7 PGND 8 +5V 9 HPD J0 D+ D SHIELD D- D+ 4 D SHIELD 5 D- 6 D0+ 7 D0 SHIELD 8 D0-9 CK+ 0 CK SHIELD CK- CEC NC 4 SCL 5 SDA 6 PGND 7 +5V 8 HPD 9 VDD SCL_Sink 7 VDD_REG OUT_D0-6 IN_D0- OUT_D0+ 5 IN_D0+ OUT_D- 4 IN_D- OUT_D+ PIHDMI5 IN_D+ TQFN- VDD IN_D- OUT_D- IN_D+ OUT_D+ 0 IN_CLK- OUT_CLK- 9 IN_CLK+ OUT_CLK+ 8 HPD_SRC EQ_S0 7 SDA_SRC SCL_SRC GND Test OC_S SCL_SINK +5V K K JP0 JP04 SCL_SINK SDA_SINK +5V HPD_SINK OUT_D+ OUT_D- OUT_D+ OUT_D- OUT_D0+ OUT_D0- OUT_CK+ OUT_CK- R04 R05 IN_CK- IN_D0- IN_CK+ IN_D- IN_D0+ IN_D- IN_D+ 0 SHELL SHELL SHELL4 SHELL D C SDA_SRC SCL_SRC CON_HDMI_Recept HPD_SRC +V B External Wiring SW0 R06 4K7 R07 4K /OE Test OC_S0 EQ_S0 4K7 R08 4K7 R09 B SW_X4_Half_Pitch External Wiring A J0 VBUS D- D+ ID 4 GND 5 CON_USB.0_MiniB_SMT +5V_A D0 B050LW +5V_USB D0 B050LW 4.7u C06 JP05 C07 00u + +5V u C08 0 R0 U0 REG7-.V VIN VOUT ADJ/GND R NP u C09 +V C0 u + Title PIHDMI5 DEMO BOARD SCHEMATIC Size Document Number Rev A A 5 4 Wednesday, April 5, 0 Date: Sheet of Appendix B: PIHDMI5 Demo Board Rev.A Schematic Appendix A: PIHDMI5 Demo Board Rev.A ORIGINATE DATE April 4, 0 EDIT DATE May, 0 6 DOCUME