Analysis and Implementation of Discrete Time PID Controllers using FPGA

Transcription

1 International Journal of Electrical an Comuter Engineering. ISSN Volume 2, Number 1 (2010), International Research Publication House htt:// Analysis an Imlementation of Discrete Time PID Controllers using FPGA Sreenivasaa B.V. an Dr. Uaykumar R.Y. Research Scholar, sreebms@gmail.com, sreebms@nitk.ac.in Professor & Hea, uaykumarry@yahoo.com Deartment of EEE, National Institute of Technology Karnataka Surathkal, Mangalore , Inia Abstract In this aer analysis an imlementation of Proortional Integral Derivative (PID) controller using Fiel Programmable Gate Array (FPGA) is resente. Different tyes of iscrete time PID controllers are analyze with their frequency resonse using Matlab tool. The controller algorithm is synthesize, simulate an imlemente using Xilinx Sartan3e XC3S100E boar with XilinxISE 9.1i as a tool an synthesize an simulate using Altera Cyclone EP1C12Q240C8 with Quartus II 6.1 as a tool. The two results are comare in terms of their ower consumtion, see, memory usage, Look U Tables (LUTs) an number of Multiliers, Aers/Subtractors. Keywors: Proortional Integral Derivative (PID) controller, Fiel Programmable Gate Array (FPGA), Backwar Difference (BD), Look U Tables (LUTs). Introuction Proortional Integral Derivative (PID) controllers have been wiely use over the ast five ecaes ue to their simlicity, robustness, effectiveness, an alicability for a broa class of systems. Desite the numerous control esign aroaches that have aeare in the literature, it is estimate that nowaays PID controllers are still emloye in more than 95% of inustrial rocesses [1]. An imortant feature of this controller is that it oes not require a recise analytical moel of the system that is

2 72 Sreenivasaa B.V. an Dr. Uaykumar R.Y. being controlle. For this reason, PID controllers have been wiely use in robotics, automation, rocess control, manufacturing, transortation, an interestingly in real time multi tasking alications [2]. Imlementation of igital PID controller has gone through several stages of evolution, from the early mechanical an neumatic esigns to the microrocessor base systems but these systems have the rawback of emaning control requirements of moern ower conitioning systems will overloa most of the microrocessors an the comuting see limits the use of microrocessor in comlex algorithms. Microrocessors, Microcontrollers an Digital Signal Processors (DSPs) can no longer kee ace with the new generation of alications that requires more flexible an higher erformance without increasing cost an resources. Further more the tasks are execute sequentially which takes longer rocessing time to accomlish the same task in Microcontrollers an DSPs. Recently, Fiel Programmable Gate Arrays (FPGA) have becoming alternative solution for the realization of igital control systems. The FPGA base controllers offer avantages such as high see comutation, comlex functionality, real time rocessing caabilities an low ower consumtion [3]. In this aer we consier iscrete time PID controller an is imlemente in a eicate FPGA. Following the stanar igital esign ractices, the controller functionality is escribe in Very High See Integrate Circuit Harware Descrition Language (VHDL). Using synthesis tool, the esign is then targete to the FPGA boar. The organization of this aer is as follows: In section II ifferent iscrete time PID controllers are reviewe. Imlementation of PID controller algorithm using FPGA is exlaine in section III. The simulation an FPGA imlementation results are iscusse in section IV. Discretization of PID Controller The general form of PID controller given in most of the text book is the stanar form. where t 1 e() t ut () = K et () + e( τ ) τ T T + (1) i t 0 K is the Proortional gain, T i is the Integral time, T is the erivative time, et () is the error signal an ut () is the outut of the controller. The ieal arallel form of the PID controller shown in Fig. 1 is reresente by a mathematical equation as t e() t ut () = Ket () + K e( τ) τ + K (2) t i 0

3 Analysis an Imlementation of Discrete Time PID Controllers 73 Figure 1 : Block iagram of PID controller The gain arameters are relate to the arameters of the stanar form through K Ki = an K = KT Ti This arallel form is shown in Fig 1, where the arameters are treate as simle gains, is the most general an flexible form. However, it is also the form where the arameters have the least hysical interretation an is generally reserve for theoretical treatment of the PID controller. The urose of integral action is to increase the low frequency gain an thus steay state error reuces. The erivative action as hase lea, which imroves stability an increases system banwith. Fallowing [3], from a ractical oint of view, imlementation of equation (2) has certain limitations. Firstly, actuator saturation can cause integrator winu, leaing to sluggish transient resonse. Seconly, the ure ifferentiation term amlifies noise, leaing to eterioration of the control comman. Finally, the ifferentiation term acts on the error signal, taking the erivative of the comman signal as well. This roceure can lea to sikes in the comman signal when a user changes reference inut abrutly. This aer rooses the two methos for control algorithm that overcomes the above roblems is shown below. A. Metho # 1: Differentiating both sies of equation (1) gives u ( t) = K e ( t) + K e( t) + K e( t) (3) i In orer to imlement the control algorithm using igital technology, equation (3) has to be iscretize. The iscretization can be erforme in number of ways with the alication of Lalace Transform to equation (1). 1 z 1. Backwar Euler Metho s = Ts 1 z 2. Forwar Euler Metho s =. Ts z

4 74 Sreenivasaa B.V. an Dr. Uaykumar R.Y. 3. Bilinear Transformation or Tustin Metho 4. Backwar Difference Metho 21 z s = Ts 1+ z We choose the Backwar Difference Metho [4] to iscretize the controller. Alying Backwar Difference (BD) Metho to equation (3) gives u( u( e( e( = K + K ie( Ts Ts e ( e( + K (4) Ts Again alying BD Metho on ė( an ė ( in equation (4) gives u( u( e( e( = K + K ie( T T s e( e( e( e( n 2) T T s s s + K (5) Ts Solving for u ( finally gives the iscrete-time PID controller { e( e( } K T e( ) u( = u( + K n + K { e( 2e( + e( n 2) } (6) Ts In equation (6) Ts = Samling time of the Analog to Digital (A/D) Converter shown Fig.2 u( = Discrete time PID controller outut e( = r(-y( = Error signal r( = Reference signal y( = Measure outut n = Discrete interval of time is an integer K, Ki, K = Proortional, Integral, Derivative gain constants resectively. i s Figure 2 : Block iagram of a Discrete Time PID controller

5 Analysis an Imlementation of Discrete Time PID Controllers 75 To stuy the frequency resonses of the PID controller take z-transform to equation (6) with zero initial conitions U ( z) = z U ( z) + K { E( z) z E( z) } + KiTs E( z) 2 { E( z) 2z E( z) + z E( z) } K + (7) Ts On simlification of the above equation, we get K 2 2K K K + KT i s + z K + z+ Ts Ts Ts GM 1( z) = (8) 2 z z U( z) where GM 1( z) = = Transfer Function of Metho #1 in z-omain = G z E( z) The frequency resonse (Boe iagram) of the equation (8) is shown in Fig. 3. At 100 khz frequency the gain of the iscrete time PID controller is 60 b an hase is egree. Figure 3 : Frequency resonse for Metho #1 (Continuous-Gc & Discrete-Gz) with K=0.1, Ki=10, K=0.01, Ts=10µs Metho # 2: An alternate equation for a iscrete time PID controller can be reresente by the following exression [5]. u( k) = u( k 1) + ( K + K + K ) e( k) i + ( K K 2 K ) e( k 1) + K e( k 2) (9) i

6 76 Sreenivasaa B.V. an Dr. Uaykumar R.Y. To stuy the frequency resonses, take z-transform on both sies of equation (9) with zero initial conitions. U z z U z K K K E z ( ) = ( ) + ( + i + ) ( ) + + (10) 1 2 ( Ki K 2 K) z E( z) Kz E( z) On simlification of the above equation, we get 2 ( K + Ki + K) z + ( Ki K 2 K) z+ K M 2( z) = 2 G z z U ( z) Where GM 2( z) = = Transfer Function of Metho #2 in z-omain = G z E( z) Fig. 4 shows the frequency resonse (Boe iagram) for the equation (11). At 100 khz frequency the gain of the iscrete time PID controller is 20.1 b an hase is 0 egree. (11) Figure 4 : Frequency resonse for Metho #2 (Continuous-Gc & Discrete-Gz) with K=0.1, Ki=10, K=0.01, Ts=10µs Imlementation of PID Controller using FPGA Having obtaine the iscrete time equation, now our focus is on the imlementation of the equation. In this work we have imlemente the equation (9) of Metho #2 using two FPGAs (simulate, synthesize an imlemente using Xilinx FPGA.. An only simulate an synthesize using Altera FPGA). The inut for the control algorithm is taken from the outut of PCF8591, 8-bit, 4 channel, InterIC (I2C) base Analog to Digital Converter (ADC) an a constant variable c voltage of 0 to

7 Analysis an Imlementation of Discrete Time PID Controllers 77 4V is alie at the inut of ADC to test the controller. To achieve a fast ynamic resonse the ADC must samle the voltage at the rate at least equal to the switching frequency. In aition, the ADC resolution must be high enough to meet voltage regulation secifications. A iscrete time controller comutes the igital uty-cycle comman. To convert this igital uty cycle comman into analog, the Digital Pulse With Moulator (DPWM) which serves the urose of Digital to Analog Converter (DAC) is imlemente using a fast clocke counter an a igital comarator [7]. This aroach is commonly use in motor rive alications. Imlementation using Xilinx FPGA In this FPGA, First the controller was imlemente using VHDL language with Xilinx ISE9.1i as a founation tool [8] an simulate at the Register Transfer Level (RTL) to verify the correctness of the esign using Moelsim 6.2C simulator tool from Mentor Grahics. By using the Xilinx ISE Founation tools, the logic synthesis was carrie out to otimize the esign an the lacement an routing were carrie out automatically to generate the FPGA imlementation file i.e. Bit file. The file is targete to a Sartan3E XC3S100E-TQ144 with a see grae of 5 to obtain the Pulse With Moulate (PWM) ulses.the technology schematic of the controller is shown in Fig. 5. Figure 5 : Technology Schematic of the equation (9). Imlementation using Altera FPGA In this FPGA, the control algorithm is first imlemente an synthesize using Altera Quartus II 6.1 as a founation tool [9] an simulate with the internal simulator tool. The equation (9) is reresente in Fig. 6 in grahical language. The register error block stores values of e(k), using D-FF(Fli-Flo) shift oeration is one to obtain e(k-1)an e(k-2). These error signals are multilie with control gain arameters K,

8 78 Sreenivasaa B.V. an Dr. Uaykumar R.Y. Ki, K. Finally, counter base DPWM is imlemente to obtain the PWM ulses. Figure 6 : Equation (9) grahical language imlementation an the PID Controller simulation Interface. Simulation an FPGA Imlementation Results Using Xilinx FPGA an Moelsim Simulator: The RTL level imlementation of PID controller an DPWM was escribe using VHDL language. To verify the behavior (functio of the controller, controller was simulate with Moelsim simulator. The simulate results are shown in Fig. 7. Figure 7 : Simulation of PID Controller Using Xilinx Moelsim Simulator.

9 Analysis an Imlementation of Discrete Time PID Controllers 79 Table I : Device Utilization Summary Of Xilinx Fga Table I shows how much logic resource of FPGA is use to imlement the whole system, an as shown in the table almost every item is below 40%. It means one can select a smaller an cheaer FPGA to further reuce the cost, or one can also buil u a microcontroller Intellectual Proerties (IP) into FPGA to imlement more sohisticate control algorithm. Figure 8 : Estimate Power Summary of PID Controller Using Xilinx FPGA. Timing Summary Reort: Minimum erio: ns Minimum inut arrival time before clock: ns Maximum outut require time after clock: ns Maximum combinational ath elay: ns Total Memory usage: kbytes Using Altera FPGA an Quartus II Simulator:

10 80 Sreenivasaa B.V. an Dr. Uaykumar R.Y. Figure 9 : Simulation of PID Controller Using Altera Quartus II Simulator. Figure 10 : Analysis an Synthesis Summary Using Altera FPGA Figure 11 : Estimate Power Summary of PID Controller Using Altera FPGA. Figure 12 : Timing Analyzer Summary Using Altera FPGA.

11 Analysis an Imlementation of Discrete Time PID Controllers 81 Figure 13 : FPGA Base PID Controller Setu. Table II : Comarision Between Xilinx an Altera Fga Parameters Xilinx FPGA Altera FPGA Multiliers 2 3 Aers/Subtractors 3 4 Counters 2 1 Comarators Inut LUTs Fli-Flos 3 3 Clock Perio ns ns Power Consumtion 34mw 82.54mw Memory Usage 110MB 128kB Conclusion In this aer, two FPGA latforms have been roose for the imlementation of PID controller. The results of both FPGA are comare for many arameters. The Xilinx FPGA gave a romising result for Multiliers, Aers/Subtractors, ower consumtion an see comare to Altera FPGA. But for memory usage, Counters, an LUTs, Altera FPGA gave a goo result. Future work will involve the imlementation an integration of PID controller into a comlete control system consisting of analog an igital inut-outut with high frequency DC-DC converter. Also we lan to investigate the quantization an limit cycle oscillations effect of the controller on DC-DC converter.

12 82 Sreenivasaa B.V. an Dr. Uaykumar R.Y. References [1] K.J. Åström an T. H. Hagglun, New Tuning Methos for PID Controllers. Proc. of 3r Euroean Conference, , [2] K.J. Åström an B. Wittenmark, Comuter Controlle Systems. Printice Hall, New Jersery, USA, [3] B. Wittenmark, K.J. Astrom an K.E. Arzen, Comuter Control: An Overview, Technical Reort, Deartement of Automatic Control, Lun Institute of Technology, Sween ( Aril [4] Mukhoaya.S., A.Patra an G.P. Rao, New Class of Discrete Time Moels for Continous Time Systems, International Journal of Control, 55, [5] Samet, L. Masmoui; N. Kharrat, M.W. Kamoun, L. A igital PID Controller for Real Time an Multi Loo Control: a Comarative Stuy. IEEE International Conference on Electronics, Circuits an Systems, , vol.1, [6] Klotchkov, I. V.; Peersen, S. A Coesign Case Stuy: Imlementing Arithmetic Functions in FPGAçs. IEEE [7] A.M. Wu, J. Xiao, D. Markovic, S.R. Saners, Digital PWM Control: Alication in Voltage Regulator Moels, IEEE PESE, 1999, [8] Xilinx ISE9.1i Software Manuals, Xilinx Inc., California, USA ( [9] Altera Quartus II 6.1 Software Manuals, Altera Inc., San Jose, CA (