Development of 3D detectors and

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1 Development of 3D detectors and ITC-irst Maurizio Boscardin boscardi@itc.it

Trento 250 researchers working on: information technology

2 ITC-irst ITC (Istituto Trentino di Cultura) is a public research institute in Trento mainly funded by the local government ITC-irst Trento 250 researchers working on: information technology microsystems & physics An entire division (60) is working on silicon sensors

3 Silicon Radiation Detectors R&D activity TCAD simulation CAD design Fabrication Device testing Standard technology From the specifications given by the user we design, produce, and (electrical) test the detector. single/double-sided strip detectors p-on-n/n-on-n pixel detector R&D activities Development in cooperation with the partners very thin detectors detectors made on radiation hard silicon substrates 3D detectors silicon photomultipliers Development of 3D sensors and SiPM is being carried out in the framework of a collaboration between INFN and ITC-irst

4 MT - LAB Furnaces We process 4 wafers MICROFAB. LAB. Ion Implanter Furnaces Litho (Mask Aligner ) Dry&Wet Etching Sputtering & Evaporator On line inspection Dicing and bonding Automatic probe station (cassette-to-cassette double side testing) TEST LAB. Automatic probe station Manual probe station Optical bench

5 3D - Outline standard 3D - concept 3D detectors: status Development of 3D ITC-irst ITC-irst activity Single-Type Column 3D detector concept Simulation, Design, Process and First Characterization Future Activity

6 Standard 3D detectors - concept Proposed by Parker et al. NIMA395 (1997) n-columns p-columns ionizing particle wafer surface Short distance between electrodes: low full depletion voltage short collection distance n-type substrate more radiation tolerant than planar detectors!!

7 3D status SLAC (Sherwood Parker) double columns filled with doped polisilicon, deep hole (entire wafer thickness) University of Glasgow double columns Schottky & diffused diode, deep hole, more info on VTT Semi 3D: single column boron doped on n-type Si; limited depth ( µm) ITC-irst Single Type Columns: single column phosphorus doped on p-type Si; limited depth ( µm). CNM workshop on 3D in february 2006 at Trento :

8 3D ITC-irst 1.Simulations of 3D-STC detectors 2.Technology used in the first two fab. runs 3.Electrical characterization of first prototypes 4.Future Activity on 3D

Single-Type-Column 3D detectors - concept NIM A 541 (2005) 441 448 Development of 3D detectors.. C.

9 Single-Type-Column 3D detectors - concept NIM A 541 (2005) Development of 3D detectors.. C. Piemonte et al n + electrodes p-type substrate ionizing particle electrons are swept away by the transversal field n + n + holes drift in the central region and diffuse towards p+ contact Uniform p+ layer Main feature of proposed 3D-STC: column etching and doping performed only once holes not etched all through the wafer bulk contact is provided by a backside uniform p + implant Simplification of the fabrication process

10 Simulated potential distribution (1) Potential distribution (vertical cross-section) 50µm in scale not in scale 0V -5V Potential distribution (horizontal cross-section) null field lines 300µm -10V -15V

Simulated potential distribution (2) Simulation of the electric field along a cut-line from the electrode to the center of the cell Na=1e13 1/cm 3 Na=5e12 1/cm 3 Na=1e12 1/cm 3 DRAWBACK:

11 Simulated potential distribution (2) Simulation of the electric field along a cut-line from the electrode to the center of the cell Na=1e13 1/cm 3 Na=5e12 1/cm 3 Na=1e12 1/cm 3 DRAWBACK: 3D-stc: once full depletion is reached it is not possible to increase the electric field between the columns To increase the electric field strength one can act on the substrate doping concentration

Capacitance simulations 1) V bias =0V 2) V bias =2V 3) V bias =5V 4) V bias =20V Do not consider the hot spot in the pictures, it is the charge released by a particle.

12 Capacitance simulations 1) V bias =0V 2) V bias =2V 3) V bias =5V 4) V bias =20V Do not consider the hot spot in the pictures, it is the charge released by a particle. The 1/C 2 curve of the col-to-back capacitance can be used to extract both the intercolumn as well as the col-to-back full depletion. C^-2 (pf-2) pitch=80um pitch=80um simulation M. Boscardin Bias Voltage (V) IWORID-08 4

Full charge collection time First phase Transversal movement 250µm e h Second phase Hole

the worst case of a track centered the central region, 50% of the charge is collected at t ~

0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.

13 Full charge collection time First phase Transversal movement 250µm e h Second phase Hole vertical movement Same V bias, different impact point (10,10) (20,20) (25,25) 50µm In the worst case of a track centered the central region, 50% of the charge is collected at t ~ 300ns Outside this region, 50% of the charge is collected within 1ns. Collected charge (a.u.) um_ um_ um_10-10 charge collected is ¼ for interaction in the middle point 1E-12 1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 Time (s)

14 Mask layout Large strip-like detectors Small version of strip detectors Planar and 3D test structures 1. Low density layout to increase mechanical robustness of the wafer 2. Strip detector = easy to electrical test

15 Strip detectors - layout Inner guard ring (bias line) metal p-stop hole Different strip-detector layouts: Number of columns from to Inter-columns pitch µm Holes Ø 6 or 10 µm Contact opening n +

16 3D process (1) hole metal strip First Process p-type Si DRIE ~ 150µm no hole filling single column single side p-stop hole Hole depth ~ 120µm n + column uniform p + layer

good contact metal oxide hole No hole filling (with polysilicon)

17 3D process (2) Deep RIE performed at CNM, (we will have the D-RIE in IRST within this year) Wide superficial n+ diffusion around the hole to assure good contact metal oxide hole No hole filling (with polysilicon) Passivation of holes with oxide n+ diffusion contact Surface isolation: p-stop or p-spray

3D diode layout: Guard ring 10x10 holes matrix p-stop Bulk p-stop Ileak = 0.68 ± 0.

0E-09 1.0E-10 diode guard ring 1 st punch through 2 nd punch through diode guard ring Ileak [A] 1.0E-04 1.0E-05 1.

18 3D diode layout: Guard ring 10x10 holes matrix p-stop Bulk p-stop Ileak = 0.68 ± V p-spray Ileak = 0.59 ± V Ileak [A] 1.0E E E E E E E-10 diode guard ring 1 st punch through 2 nd punch through diode guard ring Ileak [A] 1.0E E E E E E E-10 diode guard ring 1.0E E E V bias [V] 1.0E V bias [V]

19 3D diode CV measurements p-stop Back C d Capacitance measurement versus back on a 300µm thick wafer with ~150µm deep columns, 100µm picth Phase 1 Phase 2 region between columns is not fully depleted large capacitance M. Boscardin V bias [V] IWORID-08 1/C C -2 2 d [pf-2] [pf -2 ] Cdiode C d [pf] full dep. between columns ~ 7V region between col. is fully depleted depletion proceeds only towards the back like a planar diode full depletion ~40V depletion width of ~150µm f=100khz V bias [V] 1/C

20 Strip detectors electrical characterization Electrical Chacaterization Leakage current: < 1pA/column Single-strip backplane capacitance: <5pF Inter-column capacitance range ff/column 1.0E-05 Ileak [A] 1.0E E E-08 p-stop Number of columns per detector: E E-10 p-spray Bias line Guard ring V bias [V] Average leakage Leakage current < 1pA/column

21 Strip detectors IV measurements 30 Detectors count Current 40V of 70 different devices >50 I bias line [na] Good process yield First production has proved the feasibility of 3D-stc detectors

22 on going activity University of Glasgow (UK): CCE d5 measurements d4 with α, β, γ on 3D diodes and short strips SCIPP (USA): CCE measurements on large strips INFN Florence (Italy): CCE meas with β,on 3D diodes; University of Freiburg (D); measurements on short strips Diode Current [A] 1.E-03 1.E-05 1.E-07 1.E-09 3D diode (80µm picth) irradiated at Liubliana at 5 different neutron fluences (from 5E13 to 5E15) after irradiation before irradiation Ljubljana: TCT and neutron irradiation 1.E Reverse Bias [V]

23 CCE measurements (preliminary) Thanks to Carlo Tosi, Mara Bruzzi, Antonio De Sio INFN d5 and University of Florence 100% low voltages CCE d Reverse Bias [V] Cz 300um Fz 500mm The fast reaching (before full depletion) of a 100% efficiency suggests that carriers generated in the undepleted region are effectively collected t c CCE@0V t c /t w (for t c ~ 150µm) t w due to the peculiar geometry of 3D detectors, a region as deep as the column is always sensitive a b

24 Next Run New Process n-type Si DRIE ~ 250mm no hole filling double columns double side New Layout = Pixel MEDIPIX1 ATLAS ALICE

25 3D Conclusion First production has proved the feasibility of 3D-stc detectors 3D-stc detector: Advantage: simple fabrication process, extremely interesting device to tune the technology for the production of standard 3D detectors Disadvantage: in those applications not requiring charge information in short time Very long full charge collection times, can be used Next Step: new process & new layout ( pixel detector ).

26 3D technology 3D active edge 3D readout technology planar detector + dopant diffused in D-RIE etched edge then doped (C. Kenney 1997). Back plane physically extends at the edge. large area devices large area imaging systems one pixel of imaging matrix Active volume enclosed by an electrode: active edge trench filled with doped polisilicon or metal n + p + p + p + p + Imaging pixel matrices with 3D readout; S. Eränen VTT finland see at:

27 SiPM Outline Introduction The Geiger-mode APD The Silicon PhotoMultiplier Development of ITC-irst ITC-irst activity First results of the electrical characterization of the SiPMs produced at ITC-irst.

28 Impact Ionization V E diode structure depletion width p+ n n- electric field in the reversed bias diode Current (A) 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 1E-16 Simulated diode reverse current V BD IMPACT IONIZATION ON IMPACT IONIZATION OFF V APD Reverse Bias Voltage (V) V < V APD => photodiode 1 collected pair/generated pair V APD < V <V BD => APD <M> collected pairs/generated pair V > V BD => Geiger-mode APD inf. collected pairs/generated pair

29 Geiger-mode APD Diode biased at V D > V BD p+ n n- V D t < t 0 t = t 0 t 0 < t < t 1 t > t 1 i=0 (if no free carriers in the depletion region) carrier initiates the avalanche avalanche spreading self-sustaining current i t 0 t 1 i=i MAX t In order to be able to detect another photon, quenching mechanism needed: V BIAS V D Two solutions: large resistance: passive quenching analog circuit: active quenching [extended literature from politecnico di Milano (Cova et al.)] v D v BD i t 0 t 1 t 2 t t

30 SiPM concept GM-APD gives no information on light intensity SiPM first proposed by Golovin and Sadygov in the mid 90 A single GM-APD is segmented in tiny microdiodes connected in parallel, each with the quenching resistance. Q = Q 1 + Q 2 = 2*Q 1 metal substrate Each element is independent and gives the same signal when fired by a photon output signal is proportional to the number of triggered cells that for PDE=1 is the number of photons

31 Dark count Noise = false counts triggered by non photogenerated carriers Sources of free of carriers: 1. SRH generation in the depleted region 2. tunneling in high-field region 3. diffusion from the highly-doped regions Dark count rate depends on: - number of generation centres - temperature - overvoltage

32 Afterpulsing AFTERPULSING: carriers are trapped during the avalanche and then released triggering an avalanche If the carrier is released after the recovery time => increase dark count rate If it is released within the recovery time => no/smaller pulse Afterpulse depends on: - number of traps - number of carriers transiting during an avalanche => Ideally the recovery time should be long enough so that the traps release the carrier within this time.

33 Optical cross-talk During an avalanche discharge photons are emitted because of spontaneous direct carrier relaxation in the conduct. band cell1 cell2 Those photons can trigger the avalanche in an adjacent cell: optical cross-talk. Solutions: - operate at low over-voltage => low gain => few photons emitted - optical isolation structure: cell1 cell2

34 Photo-detection Efficiency PDE = QE * Pt * Ae 1) Internal quantum efficiency Adsorbed light nm 400nm 420nm 450nm 500nm 600nm Depth (um) Dead area is given by the structures at the edges of the microcell (metal layers, trenches, resistor ) Electrons should trigger the avalanche because of the higher ionization rate 2) Transmission efficiency of the coating In any case, the higher the overvoltage is the higher Pt is.

35 Characteristics of first prototypes 1. Substrate: p-type epitaxial 2. Very shallow junction to improve quantum efficiency at short wavelengths 3. Quenching resistance made of doped polysilicon Doping conc. (10^) [1/cm^3] Doping profiles and Electric Field n + p Doping Field depth (um) 7E+05 6E+05 5E+05 4E+05 3E+05 2E+05 1E+05 0E+00 E field (V/cm) 4. Anti-reflective coating optimized for λ~450nm ARC transmittance 5. No structure for optical isolation 6. Geometry NOT optimized for maximum PDE Transmittance Wavelength (nm)

36 First prototypes The wafer includes many structure differing in geometrical details 1mm The basic SiPM geometry is composed by 25x25 cells 1mm Cell size: 40x40µm 2

37 Electrical characterization 1.E-03 1.E-04 IV characteristics of 10 devices T=22 o C 1.E-05 Current [A] 1.E-06 1.E-07 1.E-08 1.E-09 1.E Vbias [V] Messages from the IV curve: position of the devices Breakdown voltage 31V. Uniform all over the wafer surface. post-breakdown current very uniform (measured on 90 devices) only 20% of the devices show anomalous behavior.

38 Signal characteristics SiPM read-out by means of a wide-band voltage amplifier on a scope Dark signal Voltage (V) single cell signal V BIAS =35.5V -1.0E E E E E-07 Time (s) 0.05 double signal (optical cross-talk) T=22 o C 0 Rise time ~1ns (limited by read-out system) Recovery time ~70ns Voltage (V) Vbias=34V Vbias=35.5V Vbias=32.5V Time (ns)

39 Single electron spectrum Single electron spectrum in dark condition Integration time = 10ns. DARK V 33.5V 1000 Counts double peak E-10-6E-10-4E-10-2E-10 0E+00 QDC For V BIAS =35.5V double peak counts = 1/20 single peak counts

40 Gain Gain 2.0E E E E E E E E E E E+00 T=22 o C Gain vs Bias voltage Bias Voltage (V) Q=C microcell *(V bias -V breakdown ) => C = 80-90fF DARK Linear dependence, as expected.

41 Dark count 4.0E+06 Dark count vs Bias voltage 3.5E+06 Dark Count rate (Hz) 3.0E E E E E E E Voltage (V) Dark count increases linearly with voltage. => PDE should follow the same trend.

42 Response to light Counts 2_Si_PD 33.1V T=22 o C 1pe 2pe 3pe hist Entries Mean RMS V=1.5V Pulse charge spectrum from low-intensity light flashes (red LED) QDC Channels Each peak corresponds to a different number of fired cells 2Si_PD_33_5V Counts pe T=22 o C hist Entries Mean RMS V=2V pe Very good uniformity response from the micro-cells QDC Channels

43 Energy resolution Very first measurement on one single device VERY PRELIMINARY from Pisa (A. Del Guerra) 1mmx1mmx10mm LSO crystal coupled to a SiPM Data taken in coincidence with a 10mm diam, 5mm thick YAP crystal coupled to a PMT. 22 Na source. 2.5V overvoltage 37% energy resolution 1) Optimizing the set-up and the working conditions this value can be improved 2) Area efficiency has to be optimized yet!

44 SiPM Conclusion Extremely encouraging results from the first production of SiPMs at ITC-irst. Fully functional devices with: - Gain ~ 10 6 (linear with V BIAS ) - Dark count ~ MHz - Recovery time ~ 70ns - Good uniformity of the micro-pixels response - PDE measurement in progress, encouraging first results Second production run just completed. - Implemented trenches for optical cross-talk isolation. - As for the first run, IV measurements indicate a high production yield (80%) Next steps: SiPMs with lower dark count

45 Acknowledgements: Thank to all the people involved in the ITC-irst & INFN project DASIPM and TREDI

46 VACUUM TECHNOLOGY SOLID-STATE TECHNOLOGY PMT MCP-PMT HPD PN, PIN APD GM-APD Photon detection efficiency Blue 20 % 20 % 20 % 60 % 50 % 30% Green-yellow 40 % 40 % 40 % % Red < 6 % < 6 % < 6 % % % 50% 80 % 40% Timing / 10 ph.e 100 ps 10 ps 100 ps tens ns few ns tens of ps Gain x Operation voltage 1 kv 3 kv 20 kv V V < 100 V Operation in the magnetic field < 10-3 T Axial magnetic Axial No field 2 T magnetic sensitivity field 4 T No sensitivity No sensitivity Threshold sensitivity (S/N>>1) 1 ph.e 1 ph.e 1 ph.e 100 ph.e 10 ph.e 1 ph.e Shape characteristics sensible bulky compact sensible, bulky robust, compact, mechanically rugged

47 GAIN The area of the current pulse represents the gain GAIN = Area/q = I MAX x τ / q = C x (V BIAS -V BD )/q The capacitance should be large in order to have a high gain. On the other hand, a large capacitance leads to longer recovery times. GAIN C 2 >C 1 C 1 V BIAS -V BD

48 SiPM dark count dark count rate (Hz) 1.E+07 1.E+06 1.E+05 1.E+04 1.E V 1.E V 33.0 V 33.5 V 34.5 V 34.0 V threshold (mv) Room temperature (~ 23 C) 1 p.e. dark count rate: ~ 3 MHz 3 p.e. dark count rate: ~ 1 khz trenches for the optical isolation between micro-cells were not implemented in the first run 4.0E+06 Dark count rate: linear variable with V bias increases with the temperature Dark Count rate (Hz 3.0E E E E M. Boscardin Voltage (V) IWORID-08

49 Turn-on probability P 01 = turn-on probability = probability that a carrier traversing the high-field region triggers the avalanche. it affects the detection efficiency! It is linked to the ionization rates. 1E+02 1) electrons higher ioniz. rate Ionization Rates (1/um) 1E+01 1E+00 1E-01 1E-02 electrons holes n+ p+ p n e h h e p- n- first solution is better 1E-03 1E+05 2E+05 3E+05 4E+05 5E+05 6E+05 7E+05 E field (V/cm) 2) ioniz. rates increase with field increased probability for higher over-biasing

Strip detectors CV measurements Capacitance measurement between one strip and the two first

100µm 80µm 80µm Det1 230 columns per strip Det4 Cint [pf] 7 6 5 4 3 2 1 0 Det4 Det8 Det1 Det3

measurement results Typical single-strip backplane capacitance (after lateral full depletion) <5pF

50 Strip detectors CV measurements Capacitance measurement between one strip and the two first neighboring p-stop; DC coupling; strip pitch=80µm 8 f=100khz Det3 196 columns per strip Det8 93µm 100µm 80µm 80µm Det1 230 columns per strip Det4 Cint [pf] Det4 Det8 Det1 Det3 Typical inter-column capacitance range ff/column Vback [V] Other capacitance measurement results Typical single-strip backplane capacitance (after lateral full depletion) <5pF (~200 columns) 184 columns per strip 230 columns per strip Typical coupling capacitance for AC detectors ~ 60pF

51 3D diode CCE measurements (preliminary) Carlo Tosi, Mara Bruzzi, Antonio De Sio INFN and University of Florence Original system: β - source Shaping time: 2.4µs ENC= ( C/pF)e - Max inverse current= 1500pA Sr 9 0 p + n n + Integrator circuit Amptek a225 Shaping circuit DAQ card Actual System: Max inverse current=10µa Noise=2000e - SCINTILLATOR + PMT 120 Trigger LINE Cz 300µm not irradiated p-type diode Counts 60 Calibration on Cz, 300µm, p-type planar diode Channels

irst: process development, characterization and first irradiation studies

3D D detectors at ITC-irst irst: process development, characterization and first irradiation studies S. Ronchin a, M. Boscardin a, L. Bosisio b, V. Cindro c, G.-F. Dalla Betta d, C. Piemonte a, A. Pozza