Miniature 5V Input, 1W Isolated UNREGULATED DC/DC CONVERTERS

Transcription

1 DCP DCP DCP Series Miniature V Input, W Isolated UNREGULATED DC/DC CONVERTERS FEATURES STANDARD JEDEC PLASTIC PACKAGE MEETS EN CLASS B LOW PROFILE:." (3.mm) SYNCHRONIZABLE OUTPUT SHORT CIRCUIT PROTECTION THERMAL SHUTDOWN STARTS INTO ANY CAPACITIVE LOAD FLOATING OUTPUTS EFFICIENCY: Up to % (at Full Load) rms ISOLATION 4kHz SWITCHING MILLION HOURS MTTF V, ±V, V, ±V, V, ±PUTS AVAILABLE IN TAPE AND REEL DESCRIPTION The DCP family is a series of high efficiency, V input isolated DC/DC converters. In addition to W nominal galvanically isolated output power capability, the range of DC/DCs are also fully synchronizable. The devices feature thermal shutdown, and overload protection is implemented via watchdog circuitry. Advanced power-on reset techniques give superior reset performance and the devices will start into any capacitive load up to full power output. The DCP family is implemented in standardmolded IC packaging, giving outlines suitable for high volume assembly. APPLICATIONS POINT OF USE POWER CONVERSION DIGITAL INTERFACE POWER GROUND LOOP ELIMINATION SYNC OUT DATA ACQUISITION INDUSTRIAL CONTROL AND INSTRUMENTATION TEST EQUIPMENT SYNC IN khz Oscillator Reset Watch-dog/ start-up Power Stage PSU Thermal Shutdown I BIAS Power Controller IC ternational Airport Industrial Park Mailing Address: PO Box 4, Tucson, AZ 34 Street Address: 3 S. Tucson Blvd., Tucson, AZ Tel: () 4- Twx: 9-9- Internet: Cable: BBRCORP Telex: -49 FAX: () 9- Immediate Product Info: () Burr-Brown Corporation PDS-33G Printed in U.S.A. May, 999

2 SPECIFICATIONS At T A = + C, = +V, unless otherwise specified. DCP SERIES PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT Power + 4% W % Full Load.9 W Voltage (V NOM ) DCP % Full Load () 4.. V DCPD % Full Load ±4. ± ±. V DCP % Full Load..4 V DCPD % Full Load ±. ± ±.4 V DCP % Full Load 4.. V DCPD % Full Load ±4. ± ±. V Voltage vs Temperature ±. %/ C Short-Circuit Duration ± % Indefinite Ripple C L = O/P Capacitor = µf mvp-p INPUT Nominal Voltage ( ) V Voltage Range % Supply Current % Full Load ma Reflected Ripple Current C IN = I/P Capacitor = µf marms % Full Load ISOLATION Voltage () s Flash Test kvrms Continuous Voltage (3) kvrms Insulation Resistance > GΩ Input/Output Capacitance. pf LOAD REGULATION DCP % to % Load 3 % % to % Load % % to % Load % DCPD % to % Load 3 % % to % Load 9 % % to % Load % DCP % to % Load 3 % % to % Load % % to % Load % % to % Load % DCPD % to % Load 3 % % to % Load % % to % Load % % to % Load % DCP % to % Load 4 % % to % Load % % to % Load % % to % Load % DCPD % to % Load 4 % % to % Load % % to % Load % % to % Load % SWITCHING/SYNCHRONIZATION Oscillator Frequency (F OSC ) Switching Frequency = F OSC / khz Sync Input Low. V Sync Input Current YNC = +V 4 µa Reset Time 3. µs SYNC OUT Frequency 4 khz GENERAL No Load Current DCPP % Full Load 3 ma DCPDP % Full Load 4 ma DCPP % Full Load 3 ma DCPDP % Full Load 33 ma DCPP % Full Load 34 ma DCPDP % Full Load 34 ma DCP

3 SPECIFICATIONS (CONT) At T A = + C, = +V, unless otherwise specified. DCP SERIES PARAMETER CONDITIONS MIN TYP MAX UNITS GENERAL (Cont) Efficiency DCP % Full Load % % Full Load 4 % DCPD % Full Load % % Full Load 4 % DCP % Full Load % % Full Load 3 % DCPD % Full Load % % Full Load 3 % DCP % Full Load 3 % % Full Load 4 % DCPD % Full Load % % Full Load 3 % MTTF (3) T A = + C, hrs T A = + C 3,, hrs T A = + C,, hrs Weight 4-Pin PDIP. g THERMAL SHUTDOWN Internal Controller IC Temperature 4 C Shutdown Current 3 ma TEMPERATURE RANGE Operating 4 + C NOTES: () % load current = W/V NOM typical. () Rated working voltage = 3rms (IEC9 Convention). (3) Life test data. EMC SPECIFICATIONS Specifications and Related Documents The DCP was tested to and complied with the limits of the following EMC specifications: pren (99) Conducted RF emission, telecomm lines. EN (99) Limits and methods of measurement of radio interference characteristics of information technology equipment. ENV4 (993) Electromagnetic compatibility. Basic immunity standard. Radiated RF immunity. ENV4 (993) Electromagnetic compatibility. Basic immunity standard. Conducted RF immunity. EN-4- (99) Electromagnetic compatibility, Part 4. Testing and measurement techniques, Section. Electrostatic discharge. EN-4-4 (99) Electromagnetic compatibility, Part 4. Testing and measurement techniques, Section 4. Electrical fast transient bursts. EN-4- (994) Electromagnetic compatibility, Part 4. Testing and measurement techniques, Section. Power frequency magnetic field immunity. List of Tests The following is a list of tests which were required for compliance with the above specifications: Conducted Emission Test khz to 3MHz, power and output lines, Class B limits applying. DC/DC loads of %, %, and % applying. Radiated Emission Test 3MHz to MHz, Class B limits applying. DC/DC loads of %, %, and % applying. Radiated Immunity Test, Electric Field MHz to MHz, /m, khz % AM. Radiated Immunity Test, Electric Field 9MHz, /m, Hz % PM. Electrostatic Discharge Test 4kV, HCP/VCP indirect discharge only. Electrical Fast Transient Tests kv power lines, kv signal lines. Conducted RF Immunity Tests khz to MHz, power and output lines, rms, khz % AM. Radiated Immunity Test, Magnetic Field Hz, 3A/m 3 DCP

4 PIN CONFIGURATION (Single) PIN CONFIGURATION (Dual) Top View DIP Top View DIP 4 SYNC IN 4 SYNC IN DCP DCP NC SYNC OUT SYNC OUT PIN DEFINITIONS (Single) PIN # PIN NAME DESCRIPTION Voltage Input. Input Side Common. Output Side Common. +Voltage Out. NC Not Connected. SYNC OUT Unregulated 4kHz Output from Transformer. 4 SYNC IN Synchronization Pin. PIN DEFINITIONS (Dual) PIN # PIN NAME DESCRIPTION Voltage Input. Input Side Common. Output Side Common. +Voltage Out. Voltage Out. SYNC OUT Unregulated 4kHz Output from Transformer. 4 SYNC IN Synchronization Pin. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. DCP 4

5 ABSOLUTE MAXIMUM RATINGS Input Voltage... V Storage Temperature... C to + C Lead Temperature (soldering, s)... 3 C ORDERING INFORMATION Basic Model Number: W Product Voltage Input: V In Voltage Output: V Out Dual Output: Package Code: P = 4-Pin Plastic DIP P-U = 4-Pin Plastic DIP Gull Wing DCP (D ) ( ) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER () RANGE MARKING NUMBER () MEDIA Single DCP 4-Pin PDIP - 4 C to + C DCPP DCPP Rails DCP 4-Pin PDIP Gull Wing - 4 C to + C DCPP-U DCPP-U Rails " " " " " DCPP-U/ Tape and Reel DCP 4-Pin PDIP - 4 C to + C DCPP DCPP Rails DCP 4-Pin PDIP Gull Wing - 4 C to + C DCPP-U DCPP-U Rails " " " " " DCPP-U/ Tape and Reel DCP 4-Pin PDIP - 4 C to + C DCPP DCPP Rails DCP 4-Pin PDIP Gull Wing - 4 C to + C DCPP-U DCPP-U Rails " " " " " DCPP-U/ Tape and Reel Dual DCPD 4-Pin PDIP - 4 C to + C DCPDP DCPDP Rails DCPD 4-Pin PDIP Gull Wing - 4 C to + C DCPDP-U DCPDP-U Rails " " " " " DCPDP-U/ Tape and Reel DCPD 4-Pin PDIP - 4 C to + C DCPDP DCPDP Rails DCPD 4-Pin PDIP Gull Wing - 4 C to + C DCPDP-U DCPDP-U Rails " " " " " DCPDP-U/ Tape and Reel DCPD 4-Pin PDIP - 4 C to + C DCPDP DCPDP Rails DCPD 4-Pin PDIP Gull Wing - 4 C to + C DCPDP-U DCPDP-U Rails " " " " " DCPDP-U/ Tape and Reel NOTES: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. () Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., / indicates devices per reel). Ordering pieces of DCPP-U/ will get a single -piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. DCP

6 TYPICAL PERFORMANCE CURVES (Common and DCP Specific) At T A = + C, nominal (V NOM ) = +V and = +V, unless otherwise noted. DCP EFFICIENCY vs LOAD. DCP OUTPUT VOLTAGE vs LOAD..4 Efficiency (%) 4 4 Output Voltage (V) Full Load (%) 4 Full Load (%) Peak-to-Peak Ripple Voltage (mv) 4 4 PEAK-TO-PEAK RIPPLE VOLTAGE vs LOAD C L = nf C L = µf C L = µf Load (%) rms Ripple Current (ma) 4 3 REFLECTED rms RIPPLE CURRENT vs LOAD C IN = nf C IN = µf Load (%). DCP OUTPUT vs INPUT VOLTAGE (% Load). SWITCHING FREQUENCY vs SUPPLY VOLTAGE Output Voltage (V) Input (V) Input Supply Voltage (V) Frequency (%) DCP

7 TYPICAL PERFORMANCE CURVES (Common and DCP Specific, cont) At T A = + C, nominal (V NOM ) = +V and = +V, unless otherwise noted. Output Power (W) DCP OUTPUT POWER vs TEMPERATURE Temperature ( C) Frequency (%) SWITCHING FREQUENCY vs TEMPERATURE Temperature ( C) 9 RADIATED EMISSIONS (% Load) 9 RADIATED EMISSIONS (% Load) Emission Level, Peak (dbµv/m) 3 B (3m) Limit Emission Level, Peak (dbµv/m) 3 B (3m) Limit 3 Frequency (MHz) 3 Frequency (MHz) CONDUCTED EMISSIONS (% Load) CONDUCTED EMISSIONS (% Load) Emission Level, Peak (dbµa) 3 B QP Limit B AV Limit Emission Level, Peak (dbµa) 3 B QP Limit B AV Limit. 3 Frequency (MHz). 3 Frequency (MHz) DCP

8 TYPICAL PERFORMANCE CURVES (DCPD Specific) At T A = + C, nominal (V NOM ) = ±V and = +V, unless otherwise noted.. DCPD OUTPUT vs INPUT VOLTAGE (% Load). DCPD OUTPUT VOLTAGE vs LOAD.4. Output Voltage (V) Output Voltage (V) Input Voltage (V) Load (%) DCPD LOAD BALANCE ( Load = %) DCPD LOAD BALANCE ( Load = %) Load (% of FL) 4 Load (% of FL) DCPD POWER vs TEMPERATURE DCPD EFFICIENCY vs LOAD Power Out (W) Efficiency (%) Temperature ( C) Load (%) DCP

9 TYPICAL PERFORMANCE CURVES (DCP Specific) At T A = + C, nominal (V NOM ) = +V and = +V, unless otherwise noted. Output Voltage (V) DCP OUTPUT vs INPUT VOLTAGE (% Load) Input Voltage (V) (V) DCP OUTPUT VOLTAGE vs LOAD Load (%FL) Output Power (W) DCP OUTPUT POWER vs TEMPERATURE Temperature ( C) Efficiency/% DCP EFFICIENCY vs LOAD % of Full Load 9 DCP

10 TYPICAL PERFORMANCE CURVES (DCPD Specific) At T A = + C, nominal (V NOM ) = ±V and = +V, unless otherwise noted. 3. DCPD OUTPUT vs INPUT VOLTAGE (% Load) 4. DCPD OUTPUT VOLTAGE vs LOAD Magnitude (V) Magnitude (V) Input Voltage (V) Load (% FL) DCPD LOAD BALANCE ( Load = %) DCPD LOAD BALANCE ( Load = %) 9 Load (% of FL) Load (% of FL) Output Power (W) DCPD OUTPUT POWER vs TEMPERATURE Temperature ( C) Efficiency (%) DCPD EFFICIENCY vs LOAD % of Full Load DCP

11 TYPICAL PERFORMANCE CURVES (DCP Specific) At T A = + C, nominal (V NOM ) = +V and = +V, unless otherwise noted.. DCP OUTPUT vs INPUT VOLTAGE (% Load) 9 DCP OUTPUT VOLTAGE vs LOAD Output Voltage (V) (V) Input Voltage (V) Load (% FL) DCP OUTPUT POWER vs TEMPERATURE DCP EFFICIENCY vs LOAD.9. Output Power (W) Efficiency (%) Temperature ( C) % of Full Load DCP

12 TYPICAL PERFORMANCE CURVES (DCPD Specific) At T A = + C, nominal (V NOM ) = ±V and = +V, unless otherwise noted. DCPD OUTPUT vs INPUT VOLTAGE (% Load) 9 DCPD OUTPUT VOLTAGE vs LOAD Magnitude (V) 4 3 Magnitude (V) Input Voltage (V) Load (% FL) DCPD LOAD BALANCE ( Load = %) DCPD LOAD BALANCE ( Load = %) 9 Load (% of FL) Load (% of FL) Output Power (W) DCPD OUTPUT POWER vs TEMPERATURE Temperature ( C) Efficiency (%) DCPD EFFICIENCY vs LOAD % of Full Load DCP

13 FUNCTIONAL DESCRIPTION OVERVIEW The DCP offers W of unregulated output power from a V input source with a typical efficiency of up to %. This is achieved through highly integrated packaging technology and the implementation of a custom power stage and control IC. POWER STAGE This uses a push-pull, center-tapped topology switching at 4kHz (divide by from khz oscillator). OSCILLATOR AND WATCHDOG The on-board khz oscillator provides the switching frequency via a divide by circuit and allows synchronization via the SYNC IN pins. To synchronize any number of DCP family of devices, simply tie the SYNC IN pins together (see the Synchronization section). The watchdog circuitry protects the DC/DC against a stopped oscillator and checks the oscillator frequency which will shut down the output stage if it drops below a certain threshold i.e., it will be tri-stated after approximately µs. THERMAL SHUTDOWN The DCP is also protected by thermal shutdown. If the on-chip temperature reaches a predetermined value, the DC/ DC will shutdown. This effectively gives indefinite short circuit protection for the DC/DC. SYNCHRONIZATION Any number of DCP devices can be synchronized by connecting the SYNC IN pins on the devices together (see Figure ). All the DCP devices will then selfsynchronize. This same synchronization method will apply to other V IN versions of the DCP family, allowing synchronization of various and V IN DC/DCs. Care must taken as synchronized DCPs will turn on simultaneously very quickly and draw 3mA each until each output capacitor is fully charged. This may exact a heavy demand on the input power supply. The SYNC OUT pin gives an unrectified 4kHz signal from the transformer. This can be used to set the timing of external circuitry on the output side. In noise sensitive applications any pick-up from the SYNC OUT pin can be minimized by putting a guard ring round the pin (see Figure ). +V +V DIVIDE BY RESET C 4nF per DCP Out +Out C 3 4nF SYNC IN DCP Out+ 4 Isolated DC/DC converter performance normally suffers after power reset. This is because a change in the steady state transformer flux creates an offset after power-up. The DCP family does not suffer from this problem. This is achieved through a patented () technique employed on the divide by reset circuitry resulting in no change in output phase after power interruption. CONSTRUCTION Out +Out C 4nF SYNC IN DCP Out+ 4 The DCP s basic construction is the same as standard ICs. There is no substrate within the molded package. The DCP is constructed using an IC, rectifier diodes, and a wound magnetic toroid on a leadframe. As there is no solder within the package, the DCP does not require any special PCB assembly processing. This results in an isolated DC/DC with inherently high reliability. ADDITIONAL FUNCTIONS Out 3 +Out 3 C 4 4nF FIGURE. Standard Interface. SYNC IN DCP Out+ 4 DISABLE/ENABLE The DCP can be disabled or enabled by driving the SYNC IN pin with an open drain CMOS gate. If the SYNC IN pin is pulled LOW, the DCP will disable. The disable time depends on the output loading but the internal shutdown takes up to µs. Making the gate open drain will re-enable the DCP. However, there is a trade-off in using this function; the DCP quiescent current may increase and the on-chip oscillator may run slower. This degradation in performance is dependent on the external CMOS gate capacitance. Therefore, the smaller the capacitance, the lower the 3 DCP

14 performance decrease. Driving the SYNC IN pin with a CPU type tri-state output, which has a low output capacitance, offers the lowest reduction in performance. DECOUPLING Ripple Reduction The high switching frequency of 4kHz allows simple filtering. To reduce ripple, it is recommended that.4µf capacitors are used on and (see Figure ). Both outputs on dual output DCP devices should be decoupled to pin. In applications where power is supplied over long lines and output loading is high, it may be necessary to use a.µf capacitor on the input to insure startup. There is no restriction on the size of the output capacitor used to reduce ripple. The DCP will start into any capacitive load. Low ESR capacitors will give the best reduction. EXTERNAL SYNCHRONIZATION The DCP can be synchronized externally if required using a simple external interface. Figure 3 shows a universal interface using a 4 quad switch. The CTL and SYNC ON pins are used to select external synchronization or selfsynchronization. This interface can also be used to stop (disable) the DCP. CTL SYNC ON FUNCTION External Sync Self-Sync Device Stop W R Ω W R 33Ω C.4µF +V C.4µF V Out DCP FIGURE. DCP Fully Loaded. +V V CC SYNC 4 DCP +V +V Out +Out C 4nF Out Out+ R 33kΩ I/O A U C 4nF (One Per DC/DC) V CC SYNC 4 I/O B CONT CTL DCP FREQ IN Out +Out C 3 4nF Out Out+ I/O A I/OB I/O A U3 CONT U4 V CC SYNC 4 I/O B I/O A I/O B CONT U CONT R 33kΩ SYNC ON DCP 4 R 3 33kΩ Out 3 +Out 3 C 4 4nF Out Out+ FIGURE 3. Universal Interface. DCP 4

15 Connecting the DCP in Series Multiple DCP isolated W DC/DC converters can be connected in series to provide non-standard voltage rails. This is possible by utilizing the floating outputs provided by the DCP s galvanic isolation. Connect the positive from one DCP to the negative () of another (see Figure 4). If the SYNC IN pins are tied together, the self-synchronization feature of the DCP will prevent beat frequencies on the voltage rails. The SYNC feature of the DCP allows easy series connection without external filtering which is necessary in competing solutions. The outputs on dual output DCP versions can also be connected in series to provide times the magnitude of (see Figure ). For example, a dual V DCPD could be connected to provide a 4V rail. Connecting the DCP in Parallel If the output power from one DCP is not sufficient, it is possible to parallel the outputs of multiple DCPs (see Figure ). Again, the SYNC feature allows easy synchronization to prevent power-rail beat frequencies at no additional filtering cost. THERMAL MANAGEMENT LAYOUT To maximize the thermal performance of the DCP, taking more care in the PCB layout can provide the most efficient thermal dissipation paths from the DC/DC. The input controller IC and the rectifier diodes inside the DCP are bonded directly onto the internal leadframe. The leadframe, being almost % copper, provides an excellent path for dissipated heat and does so significantly more efficiently than FR4 PCBs or ceramic substrates found in alternate packaging technology DC/DCs. UPPLY SYNC IN DCP + SYNC IN DCP COM FIGURE 4. Connecting the DCP in Series. UPPLY DCP COM FIGURE. Connecting Dual Outputs in Series. UPPLY SYNC IN DCP x Power Out SYNC IN DCP COM FIGURE. Connecting Multiple DCPs in Parallel. DCP

16 Most of the dissipated heat comes from input side common (pin ). To a lesser extent, the pin (pin ) also dissipates heat from the package. In the layout shown in Figure, the large copper areas next to pins and will provide excellent heat dissipation paths. The tracking in Figure, shown in dotted lines, will provide shielding for the SYNC IN (pin 4) and SYNC OUT (pin ) pins if necessary. As described earlier in the Disable/Enable section of this data sheet, any additional capacitance to the pf internal capacitor at the SYNC IN pin will affect performance. If there is the possibility of significant leakage capacitance at the SYNC IN pin, it can be shielded as shown. As described earlier in the Synchronization section of this data sheet, the SYNC OUT pin can be shielded as shown to minimize noise pick-up in sensitive applications. dependent on the V IN of the DCP. With a V IN of.v, the LP9 LDO can deliver up to ma. The LP9 LDO has a very low dropout voltage of typically less than mv, which allows us to deliver 4.V guaranteed from a unregulated DC/DC. It also offers low output flagging and shutdown capability and is supplied in either MSOP- or SO- packages ensuring additional board area is minimal and low profile is maintained. +V IN V IN SIP DC/DC DCPxx FIGURE. PCB Layout for DCP and Competitive SIP DC/DC. Bottom View FIGURE. Thermal Management Layout. LAYOUT FOR DCP AND SIP PRODUCTS Figure shows a layout to allow the use of a DCP and a competitive SIP isolated DC/DC converter. POST REGULATION OF THE DCPP USING THE LP9 LDO REGULATOR In digital applications where the load range is wide or evolving, or the input supply voltage is not well regulated and V±% or V±V% cannot be guaranteed, it is often necessary to have a regulated V output from the DCP. It is possible to post regulate the DCP and still guarantee a minimum of 4.V. This still gives the benefits of isolation in reducing the power supply noise to V digital circuitry. By using an ultra-low dropout regulator (e.g., National Semiconductor s LP9IM-.) in series with the output of a DCP, it is possible to supply up to % load current (depending on V IN ). Figure 9 shows the typical load current for the post-regulated V IN / DCP. It is possible with a V IN of V to supply 3mA. Because of the : line regulation of the DCP, a % change in the input will result in a % change in the output. Therefore, the amount of current that the LDO can deliver is strongly V REG (V) V IN = V 4. V IN =.V V IN = 4.V 3. I OUT (ma) FIGURE 9. DCPP AND LP9 Regulator. DCP AND LP9 APPLICATION CIRCUIT Figure shows the LP9 in series with the DCP output. The.µF capacitor on the input of the LP9 and the 4.µF capacitor on the output are the minimum recommended for good ripple reduction. Pin on the LP9 flags an error by going LOW if the output drops % below nominal. DCP

17 OTHER LDO REGULATORS The SGS-Thomson L494 LDO can also be used to post regulate the DCP and can deliver a regulated minimum 4.V up to 3mA. The DCP can also be post regulated with the Micrel MIC which offers up to ma output drive with a typical dropout voltage of mv at ma. The MIC is available in a micro-sized SOT3- package which gives the minimum additional board area for post regulation. PREDICTING OUTPUT VOLTAGE VERSUS LOAD The Load Regulation specifications are calculated as follows: CONDITION CALCULATION % to % Load ( at % load at % load)/ at % load % to % Load ( at % load at % load)/ at % load % to % Load ( at % load at % load)/ at % load % to % Load ( at % load at % load)/ at % load. To predict the output voltage at % load take the measured or specified voltage at % load and multiply by ( + Load Reg % to %). For example a DCPP typical at % load will be V x ( %) = 4.V.. To predict the output voltage at % load take the measured or specified voltage at % load and multiply by ( + Load Reg % to %). For example a DCPP typical at % load will be V x ( + %) =.V. 3. To predict the output voltage at % load on higher versions take the measured or specified voltage at % load and multiply by ( + Load Reg % to %). For example a DCPP typical at % load will be V x ( + %) = 3.4V. To then estimate the voltage at % load take the previously calculated at % load and multiply by ( + Load Reg % to %). In this case the typical at % load will be 3.4V x ( + %) = 4.3V. To obtain predictions for loads other than those specified assume the versus load characteristic is linear between the load points and calculate accordingly. The % to % load specification guarantees the maximum voltage excursion for any load between % to % with respect to at % load. The above does not take into consideration line regulation and assumes a nominal input voltage. The : line regulation of the DCP family means that a percentage change in the input will give a corresponding percentage change in the output. V IN 4 Output.4µF DCP.µF 3 LP9 33kΩ Error + 4.µF Load Com FIGURE. Post Regulation of DCPP..4 (.). (.44).9 (.).4 (.). (.4) 4-Pin All Leads on.4mm Pitch Dimensions in mm (inches) FIGURE. PCB Pad Size and Placement for U Package. DCP