Abbreviations used: O - output, I - input, P - power.
|
|
|
- Richard Bennett
- 6 years ago
- Views:
Transcription
1 MONOSTABLE MULTIVIBRATOR 1.0 General description. This circuit is designed to work as monostable multivibrator. It is very useful as pulse stretcher circuit. It provides wide range of output pulse duration s which are programmable. It does not require any tuning or external components and provides 10% overall accurate pulse duration. Very easy to use and predictable to design. PDIP, SOIC 1 VDD GND 8 2 D0 SLOPE 7 3 D1 OUT 6 4 D2 TRIGGER 5 HTC550 Features Single chip solutions for most pulse starching applications. No external components needed. Easy selection of pulse duration. Flexible selection of trigger slope. Up to ten percent precise output pulse duration in voltage and temperature range. Predictability and design ease. Pin out description. Abbreviations used: O - output, I - input, P - power. Pin number Name I / O Description Notes 1 VDD P Power +2.5V to +5.5V 2 D0 I Period selector D0 Tie it to GND or VDD (see table) 3 D1 I Period selector D1 Tie it to GND or VDD (see table) 4 D2 I Period selector D2 Tie it to GND or VDD (see table) 5 TRIGGER I Trigger input 6 OUT O Pulse output 7 SLOPE I Trigger slope VDD rising edge, GND- falling. 8 GND P Ground Connects to digital ground. Pulse width verses D[0:2] Abbreviations used: 0 connection to GND, 1 connection to VDD. D2 D1 D0 PULSE WIDTH Rearming time Hunting time max(min) µS 12µS 19µS (14µS) µS 12µS 19µS (14µS) µS 12µS 19µS (14µS) mS 12µS 19µS (14µS) mS 12µS 19µS (14µS) mS 12µS 19µS (14µS) S 12µS 19µS (14µS) 12/26/99 1
2 S 12µS 19µS (14µS) Please note that those values are for reference only. Actual values vary up to 10 percent depending upon VDD voltage and operational temperature. Trigger edge versus SLOPE Abbreviations used: 0 connection to GND, 1 connection to VDD. SLOPE TRIGGER edge. 0 Falling edge 1 Rising edge. 2.0 Functional description. HTC550 has four operational states: 1. Power up State. Internal reset takes about 18mS once power is applied to the part. During those 18mS output is tri-stated. In order to keep output low during internal reset resistor can be put from output to ground. After internal reset HTC550 enters Power Up State. At this state Slope pin is sampled and output is set low. After those steps HTC550 enters Hunt State. 2. Hunt for Trigger State. In this state HTC550 is hunting for trigger. Output is not changed during this state. Once part gets trigger it samples D[0:2] pins and goes to Pulse generation State. 3. Pulse Generation. In this State output pulse is generated per D[0:2] pins. Output goes high for specified duration then goes low and goes to Rearm State. Any triggers are ignored during this State. 4. Rearm State. During this state SLOPE pin is sampled and trigger is rearmed per this value. After finishing it goes into Hunt State. 3.0 Typical connection diagram. TRIGGER IN VDD VDD SLOPE AND DURATION TRIGGER VDD SLOPE OUT D0 D1 D2 GND HTC n PULSE OUT 10K 10K 10K 10K 212/26/99 2
3 4.0 Electrical characteristics. Voltage on VDD pin in respect to GND +2.5 to +5.5V Current consumption without load 3 ma 1 TRIGGER rise time min 10nS 1 TRIGGER fall time min 10nS 1 TRIGGER high period min 1.04µS 1 TRIGGER low period min 1.04µS 1 TRIGGER input leakage ±5µA 1 TRIGGER input high voltage 0.8VDD TRIGGER input low voltage 0.2VDD OUT output low voltage (5mA load) 0.4V 1 OUT output low voltage (25mA load) 0.75V 1 OUT output high voltage (5mA source) VDD-0.7V 1 OUT output source current max 25mA 1 OUT output sink current max 25mA 1 NOTES: 1. Those values are characterized but not tested. 5.0 Ordering information. H T C X X OPTIONAL: Temperature range: C = 0 o C to +70 o C, I = - 40 o C to + 85 o C. PACKAGE: S 208 mil SOIC D 300 mil PDIP. PART NUMBER. 312/26/99 3
4 6.0 Mechanical information. 8-Lead Plastic Dual In-line (P) 300 mil (PDIP) Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p Top to Seating Plane A Molded Package Thickness A Base to Seating Plane A Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width B Lower Lead Width B Overall Row Spacing eb Mold Draft Angle Top α Mold Draft Angle Bottom β *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash protrusions. Mold flash or protrusions shell not exceed.010 (0.254mm)per side. JEDEC Equivalent:MS /26/99 4
5 8-Lead Plastic Small Outline (SM) Medium, 208 mil (SOIC) Units INCHES * MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch P Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Overall Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash protrusions. Mold flash or protrusions shell not exceed.010 (0.254mm)per side. 512/26/99 5
6 HTC makes no warranty, express, statutory implied or by description, regarding information set forth herein or regarding the freedom of described devices from patent infringement. HTC makes no warranty or merchantability or fitness for any purposes. HTC reserves right to discontinue production and change specifications and prices at any time and without notice. HTC's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by HTC for such applications. High Tech Chips, Inc /26/99 6
General Description HIGH TECH CHIPS, INC.
1 2 3 4 5 6 7 8 9 L HIGH TECH General Description HTC2500 is a simple clock IC that was built using our micro RTOS. Features: Operation from low cost low power 32768Hz crystal Supports backup power supply
TC4421/TC A High-Speed MOSFET Drivers. General Description. Features. Applications. Package Types (1)
9A High-Speed MOSFET Drivers Features High Peak Output Current: 9A Wide Input Supply Voltage Operating Range: - 4.5V to 18V High Continuous Output Current: 2A Max Fast Rise and Fall Times: - 3 ns with
DM96S02 Dual Retriggerable Resettable Monostable Multivibrator
January 1992 Revised June 1999 DM96S02 Dual Retriggerable Resettable Monostable Multivibrator General Description The DM96S02 is a dual retriggerable and resettable monostable multivibrator. This one-shot
SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
MCP6021/1R/2/3/4. Rail-to-Rail Input/Output, 10 MHz Op Amps. Features. Description. Typical Applications. Package Types.
Rail-to-Rail Input/Output, 10 MHz Op Amps Features Rail-to-Rail Input/Output Wide Bandwidth: 10 MHz (typ.) Low Noise: 8.7 nv/ Hz, at 10 khz (typ.) Low Offset Voltage: - Industrial Temperature: ±500 µv
NE556, SA556, SE556, SE556C DUAL PRECISION TIMERS
Two Precision Timing Circuits per Package Astable or Monostable Operation TTL-Compatible Output Can Sink or Source Up to 50 ma Active Pullup or Pulldown Designed to be Interchangeable With Signetics SE556,
MCP A, Low Voltage, Low Quiescent Current LDO Regulator. Description. Features. Applications. Package Types
1A, Low Voltage, Low Quiescent Current LDO Regulator Features 1A Output Current Capability Input Operating Voltage Range: 2.3V to.0v Adjustable Output Voltage Range: 0.8V to 5.0V Standard Fixed Output
DatasheetArchive.com. Request For Quotation
DatasheetArchive.com Request For Quotation Order the parts you need from our real-time inventory database. Simply complete a request for quotation form with your part information and a sales representative
CD4047BC Low Power Monostable/Astable Multivibrator
Low Power Monostable/Astable Multivibrator General Description The CD4047B is capable of operating in either the monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and
X9C102/103/104/503. Terminal Voltages ±5V, 100 Taps. Digitally Controlled Potentiometer (XDCP )
APPLICATION NOTE A V A I L A B L E AN99 AN115 AN120 AN124 AN133 AN134 AN135 Terminal Voltages ±5V, 100 Taps Digitally Controlled Potentiometer (XDCP ) FEATURES Solid-state potentiometer 3-wire serial interface
CD4538BC Dual Precision Monostable
CD4538BC Dual Precision Monostable General Description The CD4538BC is a dual, precision monostable multivibrator with independent trigger and reset controls. The device is retriggerable and resettable,
DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control
August 1986 Revised February 1999 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The circuit is a synchronous, reversible, up/ down counter. Synchronous operation is provided by
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
CD4538 Dual Precision Monostable
CD4538 Dual Precision Monostable General Description The CD4538BC is a dual, precision monostable multivibrator with independent trigger and reset controls. The device is retriggerable and resettable,
Dual precision monostable multivibrator
Rev. 05 4 March 2009 Product data sheet 1. General description The is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has an active LOW trigger/retrigger input (na), an active
Digitally Controlled Potentiometer (XDCP ) X9C102/103/104/503
Digitally Controlled Potentiometer (XDCP ) X9C102/103/104/503 FEATURES Solid-state potentiometer 3-wire serial interface 100 wiper tap points Wiper position stored in nonvolatile memory and recalled on
TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
Four -Bit Voltage Output DACs 3-V Single-Supply Operation Serial Interface High-Impedance Reference Inputs Programmable for or 2 Times Output Range Simultaneous Update Facility Internal Power-On Reset
96LS02 DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator
May 1992 96LS02 DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator General Description The 96LS02 is a dual retriggerable and resettable monostable multivibrator The one-shot provides exceptionally
TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
Four -Bit Voltage Output DACs 5-V Single-Supply Operation Serial Interface High-Impedance Reference Inputs Programmable or 2 Times Output Range Simultaneous-Update Facility Internal Power-On Reset Low
TCM1030, TCM1050 DUAL TRANSIENT-VOLTAGE SUPPRESSORS
Meet or Exceed Bell Standard LSSGR Requirements Externally-Controlled Negative Firing Voltage... 90 V Max Accurately Controlled, Wide Negative Firing Voltage Range... V to V Positive Surge Current (see
DUAL FULL-BRIDGE PWM MOTOR DRIVER
96 Data Sheet 939.0L PWM OUT A OUT A E SENSE OUT B I 0 I PHASE V REF RC 3 4 5 6 8 9 0 UDN96B (DIP) θ PWM V BB PWM θ V CC 4 3 0 9 8 6 5 4 3 LOAD SUPPLY E SENSE OUT B I PHASE V REF RC LOGIC SUPPLY Dwg. PP-005
ICS558A-02 LVHSTL TO CMOS CLOCK DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS558A-02 Description The ICS558A-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs
SN75150 DUAL LINE DRIVER
Meets or Exceeds the Requirement of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Max Transition Time
SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS
Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
8Mb (1M x 8) One-time Programmable, Read-only Memory
Features Fast read access time 90ns Low-power CMOS operation 100µA max standby 40mA max active at 5MHz JEDEC standard packages 32-lead PLCC 32-lead PDIP 5V 10% supply High-reliability CMOS technology 2,000V
NE555,SA555,SE555 PRECISION TIMERS
Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source Up To 200 ma Description/ordering information These devices are precision
TLC555, TLC555Y LinCMOS TIMERS
ery Low Power Consumption mw Typ at DD = 5 Capable of Operation in Astable Mode CMOS Output Capable of Swinging Rail to Rail High Output-Current Capability Sink 00 ma Typ Source 0 ma Typ Output Fully Compatible
UDN2987x-6. DABIC-5 8-Channel Source Driver with Overcurrent Protection
Package A, 20-pin DIP Package LW, 20-pin SOIC-W Approximate Scale 1:1 Providing overcurrent protection for each of its eight sourcing outputs, the UDN2987A-6 and UDN2987LW-6 drivers are used as an interface
SP720. Electronic Protection Array for ESD and Over-Voltage Protection. Features. [ /Title (SP720 ) /Subject. (Electronic.
SP70 Data Sheet January 99 File Number 79.0 [ /Title (SP70 ) /Subject (Electronic Protection Array for ESD and Over Voltage Protection) /Autho r () /Keywords (TVS, Transient Suppression, Protection, ESD,
MC3456 DUAL TIMING CIRCUIT
Order this document by /D The dual timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. Additional terminals are provided for triggering or resetting
DM74LS14 Hex Inverter with Schmitt Trigger Inputs
Hex Inverter with Schmitt Trigger Inputs General Description This device contains six independent gates each of which performs the logic INVERT function. Each input has hysteresis which increases the noise
IX2113BTR. 600V High and Low Side Gate Driver INTEGRATED CIRCUITS DIVISION. Description. Driver Characteristics. Features. Ordering Information
V High and Low Side Gate Driver Driver Characteristics Parameter Rating Units V OFFSET V I O +/- (Source/Sink) / A V OUT - V t on /t off / ns Delay Matching (Max) ns Features Floating Channel for Bootstrap
256K (32K x 8) Paged Parallel EEPROM AT28C256
Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
MCP ma Synchronous BUCK Regulator. Features. Description. Applications. Package Type
M MCP101 500 ma Synchronous BUCK Regulator Features Input Range of 2.V to 5.5V 3 Operating Modes: PWM, PFM and LDO Integrated BUCK and Synchronous Switches Ceramic or Electrolytic Input/Output Filtering
DM74LS132 Quad 2-Input NAND Gate with Schmitt Trigger Input
August 1986 Revised March 2000 DM74LS132 Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function.
SP723 Lead-Free/Green
TVS Diode Arrays The SP73 is an array of SCR/Diode bipolar structures for ESD and over-voltage protection of sensitive input circuits. The SP73 has protection SCR/Diode device structures per input. There
MM74C925 MM74C926 MM74C927 MM74C928 4-Digit Counters with Multiplexed 7-Segment Output Drivers
October 1987 Revised January 1999 MM74C925 MM74C926 MM74C927 MM74C928 4-Digit Counters with Multiplexed 7-Segment Output Drivers General Description The MM74C925, MM74C926, MM74C927 and MM74C928 CMOS counters
CD4541BC Programmable Timer
CD4541BC Programmable Timer General Description The CD4541BC Programmable Timer is designed with a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors,
DM74ALS174 DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Hex/Quad D-Type Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and
ISO-9001 AS9120certi cation ClassQ Military
Datasheet RochesterElectronics ManufacturedComponents Rochester branded components are manufactured using eitherdie/wafers purchasedfrom theoriginalsuppliers orrochesterwafers recreated from the originalip.
74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs
74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs General Description The DM74LS221 is a dual monostable multivibrator with Schmitt-trigger input. Each device has three inputs
RC A Adjustable/Fixed Low Dropout Linear Regulator. Description. Features. Applications. Typical Applications.
www.fairchildsemi.com A Adjustable/Fixed Low Dropout Linear Regulator Features Low dropout voltage Load regulation:.5% typical Trimmed current limit On-chip thermal limiting Standard SOT-223, TO-263, and
ISL6536A. Four Channel Supervisory IC. Features. Applications. Typical Application Schematic. Ordering Information. Data Sheet May 2004 FN9136.
ISL6536A Data Sheet May 2004 FN9136.1 Four Channel Supervisory IC The ISL6536A is a four channel supervisory IC designed to monitor voltages >, = 0.7V. This IC bias range is from 2.7V to 5V but can supervise
MM74C925 MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers
MM74C925 MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers General Description The MM74C925 and MM74C926 CMOS counters consist of a 4-digit counter, an internal output latch, NPN output
MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
September 1983 Revised January 2004 MM74HC221A Dual Non-Retriggerable Monostable Multivibrator General Description The MM74HC221A high speed monostable multivibrators (one shots) utilize advanced silicon-gate
SN74LS122, SN74LS123. Retriggerable Monostable Multivibrators LOW POWER SCHOTTKY
Retriggerable Monostable Multivibrators These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance
4-Megabit (512K x 8) OTP EPROM AT27C040
Features Fast Read Access Time 70 ns Low Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PDIP 32-lead PLCC 32-lead TSOP 5V ± 10% Supply High Reliability
TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS067C NOVEMBER 1983 REVISED SEPTEMBER 1996
Microprocessor Peripheral or Standalone Operation 8-Bit Resolution A/D Converter Differential Reference Input Voltages Conversion Time...7 µs Max Total Access and Conversion Cycles Per Second TLC548...up
DM74LS83A 4-Bit Binary Adder with Fast Carry
4-Bit Binary Adder with Fast Carry General Description These full adders perform the addition of two 4-bit binary numbers. The sum ( ) outputs are provided for each bit and the resultant carry (C4) is
256K (32K x 8) OTP EPROM AT27C256R
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 20 ma Max Active at 5 MHz JEDEC Standard Packages 28-lead PDIP 32-lead PLCC 28-lead TSOP and SOIC 5V ± 10% Supply High Reliability
UDN2987x-6 DABIC-5 8-Channel Source Driver with Overcurrent Protection
Features and Benefits 4.75 to 35 V driver supply voltage Output enable-disable (OE/R) 350 ma output source current Overcurrent protected Internal ground clamp diodes Output Breakdown Voltage 35 V minimum
HIP V, 300mA Three Phase High Side Driver. Features. Applications. Ordering Information. Pinout. July 2004
HIP0 Data Sheet July 00 FN. 0V, 00mA Three Phase High Side Driver The HIP0 is a three phase high side N-channel MOSFET driver, specifically targeted for PWM motor control. Two HIP0 may be used together
CD54HC221, CD74HC221, CD74HCT221. High-Speed CMOS Logic Dual Monostable Multivibrator with Reset. Features. Description
Data sheet acquired from Harris Semiconductor SCHS166F November 1997 - Revised October 2003 CD54HC221, CD74HC221, CD74HCT221 High-Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description
ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA
BUFFER Description The ICS552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for glitch-free switching between two clock sources. It is part
4-Megabit (256K x 16) OTP EPROM AT27C4096
Features Fast Read Access Time 55 ns Low Power CMOS Operation 100 µa Maximum Standby 40 ma Maximum Active at 5 MHz JEDEC Standard Packages 40-lead PDIP 44-lead PLCC 40-lead VSOP Direct Upgrade from 512-Kbit,
DM74ALS520 DM74ALS521 8-Bit Comparator
8-Bit Comparator General Description These comparators perform an equal to comparison of two 8-bit words with provision for expansion or external enabling. The matching of the two 8-bit input plus a logic
1-Megabit (64K x 16) OTP EPROM AT27C1024
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 40-lead PDIP 44-lead PLCC 40-lead VSOP Direct Upgrade from 512K (AT27C516)
DatasheetArchive.com. Request For Quotation
DatasheetArchive.com Request For Quotation Order the parts you need from our real-time inventory database. Simply complete a request for quotation form with your part information and a sales representative
Features. EXTERNAL PULLABLE CRYSTAL (external loop filter) FREQUENCY MULTIPLYING PLL 2
DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL MK2049-34A Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 khz
ICS LOW PHASE NOISE CLOCK MULTIPLIER. Features. Description. Block Diagram DATASHEET
DATASHEET ICS601-01 Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase
DM74LS126A Quad 3-STATE Buffer
DM74LS126A Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled,
IX2127NTR. High-Voltage Power MOSFET & IGBT Driver INTEGRATED CIRCUITS DIVISION. Description. Driver Characteristics. Features.
High-Voltage Power MOSFET & IGBT Driver Driver Characteristics Parameter Rating Units V OFFSET 6 V I O +/- (Source/Sink) 25/5 ma V th 25 mv t ON / t OFF (Typical) 1 ns Features Floating Channel Designed
Fast read access time 70ns Low-power CMOS operation 100μA max standby 30mA max active at 5MHz. JEDEC standard packages 32-lead PDIP 32-lead PLCC
Atmel AT7C040 4Mb (51K x 8) OTP, EPROM DATASHEET Features Fast read access time 70ns Low-power CMOS operation 100μA max standby 30mA max active at 5MHz JEDEC standard packages 3-lead PDIP 3-lead PLCC 5V
74AC04 74ACT04 Hex Inverter
74AC04 74ACT04 Hex Inverter General Description The AC/ACT04 contains six inverters. Ordering Code: Features I CC reduced by 50% on 74AC only Outputs source/sink 24 ma ACT04 has TTL-compatible inputs November
DATA SHEET. HEF4047B MSI Monostable/astable multivibrator. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
Load Switch with Level-Shift
Load Switch with Level-Shift PRODUCT SUMMARY V IN (V DS2 ) (V) R DS(on) (Ω) I D (A).5 to 2 DESCRIPTION.54 at V IN = 4.5 V 3.9.77 at V IN = 2.5 V 3.2.6 at V IN =.8 V 2.8.65 at V IN =.5 V 2.2 The includes
DM74ALS169B Synchronous Four-Bit Up/Down Counters
Synchronous Four-Bit Up/Down Counters General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74ALS169B
Remote Control Encoder IC
DESCRIPTION is a remote control encoder paired with PT2294 utilizing CMOS Technology. It encodes data and address pins into a serial coded waveform suitable for RF modulation. has a maximum of 12-bit of
ICS542 CLOCK DIVIDER. Features. Description. Block Diagram DATASHEET. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
DATASHEET ICS542 Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide
RC4136 General Performance Quad 741 Operational Amplifier
RC General Performance Quad 7 Operational Amplifier www.fairchildsemi.com Features Unity gain bandwidth MHz Short circuit protection No frequency compensation required No latch-up Large common mode and
74AC273, 74ACT273 Octal D-Type Flip-Flop
74AC273, 74ACT273 Octal D-Type Flip-Flop Features Ideal buffer for microprocessor or memory Eight edge-triggered D-type flip-flops Buffered common clock Buffered, asynchronous master reset See 377 for
RV4145A. Low Power Ground Fault Interrupter. Features. Description. Block Diagram.
Low Power Ground Fault Interrupter www.fairchildsemi.com Features No potentiomenter required Direct interface to SCR Supply voltage derived from AC line 26V shunt Adjustable sensitivity Grounded neutral
Logic Configuration Part Number Package Type Packing Method Quantity. IX4426N 8-Pin SOIC Tube 100. IX4426NTR 8-Pin SOIC Tape & Reel 2000
IX4426-IX4427-IX4428 1.5-mpere Dual Low-Side Ultrafast MOSFET Drivers Features 1.5 Peak Output Current Wide Operating Voltage Range: 4.5V to 35V -4 C to +125 C Operating Temperature Range Latch-up Protected
Microprocessor Supervisory Circuit ADM1232
Microprocessor Supervisory Circuit FEATURES Pin-compatible with MAX1232 and Dallas DS1232 Adjustable precision voltage monitor with 4.5 V and 4.75 V options Adjustable strobe monitor with 150 ms, 600 ms,
MM74HC132 Quad 2-Input NAND Schmitt Trigger
Quad 2-Input NAND Schmitt Trigger General Description The utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability
ICS HDTV AUDIO/VIDEO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET
DATASHEET ICS662-03 Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. LM555 Timer General Description The LM555 is a highly stable device for
DM74AS169A Synchronous 4-Bit Binary Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74AS169
MK2703 PLL AUDIO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET MK2703 Description The MK2703 is a low-cost, low-jitter, high-performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using IDT
LMC555 CMOS Timer. Features. Block and Connection Diagrams. Pulse Width Modulator. October 2003
LMC555 CMOS Timer General Description The LMC555 is a CMOS version of the industry standard 555 series general purpose timers. In addition to the standard package (SOIC, MSOP, and MDIP) the LMC555 is also
MCP4921/ Bit DAC with SPI Interface. Features. Description. Applications. Package Types. Block Diagram MCP4921 MCP4922
1-Bit DAC with SPI Interface Features 1-Bit Resolution ±. LSB DNL (typ) ± LSB INL (typ) Single or Dual Channel Rail-to-Rail Output SPI Interface with MHz Clock Support Simultaneous Latching of the Dual
ICS512 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS512 Description The ICS512 is the most cost effective way to generate a high-quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. The name
IDT9170B CLOCK SYNCHRONIZER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET IDT9170B Description The IDT9170B generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5 V VDD). Using IDT s proprietary phase-locked loop
PCI-EXPRESS CLOCK SOURCE. Features
DATASHEET ICS557-01 Description The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.
Discontinued Product
Dual Full-Bridge PWM Motor Driver Discontinued Product This device is no longer in production. The device should not be purchased for new design applications. Samples are no longer available. Date of status
DM Segment Decoder/Driver/Latch with Constant Current Sink Outputs
DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs General Description The DM74 is a 7-segment decoder driver incorporating input latches and output circuits to directly drive common
ICS571 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET Description The is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced
64K x 1 Static RAM CY7C187. Features. Functional Description. Logic Block Diagram. Pin Configurations. Selection Guide DIP. SOJ Top View.
64K x 1 Static RAM Features High speed 15 ns CMOS for optimum speed/power Low active power 495 mw Low standby power 110 mw TTL compatible inputs and outputs Automatic power-down when deselected Available
A5821. BiMOS II 8-Bit Serial Input Latched Driver. Discontinued Product
A5821 BiMOS II 8-Bit Serial Input Latched Driver Discontinued Product These parts are no longer in production The device should not be purchased for new design applications. Samples are no longer available.
Load Switch with Level-Shift
SiX Load Switch with Level-Shift PRODUCT SUMMARY V DS (V) R DS(on) ( ) I D (A).5 at V IN =.5 V ±.3.8 to 8.89 at V IN =.5 V ±.3.5 at V IN =.8 V ±.3 SiX, 3 S D Q FEATURES Halogen-free According to IEC 9--
8Mb (1M x 8) One-time Programmable, Read-only Memory
Features Fast read access time 90ns Low-power CMOS operation 100µA max standby 40mA max active at 5MHz JEDEC standard packages 32-lead PLCC 32-lead PDIP 5V 10% supply High-reliability CMOS technology 2,000V
ICS2304NZ-1 LOW SKEW PCI/PCI-X BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS2304NZ-1 Description The ICS2304NZ-1 is a high-performance, low skew, low jitter PCI/PCI-X clock driver. It is designed to distribute high-speed signals in PCI/PCI-X applications operating
ICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET ICS660 Description The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses
MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK2705 Description The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal.
Dual Processor Supervisors with Watchdog ADM13305
Dual Processor Supervisors with Watchdog ADM335 FEATURES Dual supervisory circuits Supply voltage range of 2.7 V to 5.5 V Pretrimmed threshold options:.8 V, 2.5 V, 3.3 V, and 5 V Adjustable.6 V voltage
DISCONTINUED PRODUCT FOR REFERENCE ONLY COMPLEMENTARY OUTPUT POWER HALL LATCH 5275 COMPLEMENTARY OUTPUT POWERHALL LATCH FEATURES
5275 POWER HALL LATCH Data Sheet 27632B X V CC 1 SUPPLY ABSOLUTE MAXIMUM RATINGS at T A = +25 C Supply Voltage, V CC............... 14 V Magnetic Flux Density, B...... Unlimited Type UGN5275K latching
CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS
Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 495 mw (Max, L version) Low standby power 0.275 mw (Max, L version) 2V data retention ( L version only) Easy memory expansion
DISCONTINUED PRODUCT FOR REFERENCE ONLY
23 Data Sheet 23.5A LOAD SUPPLY A PHASEA OUTA OUT 2A V EA 2 3 4 5 6 7 UDN23B VBB V DD 5 3 2 0 SUPPLY B 4 PHASE B OUT B OUT 2B V EB Dwg. No. A-2,455 ABSOLUTE MAXIMUM RATINGS at T J +50 C Load Supply Voltage,
MM74HCU04 Hex Inverter
MM74HCU04 Hex Inverter General Description The MM74HCU04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard