Low Power Scalable Successive Approximation ADC at 45nm

Transcription

1 Low Power Scalable Successive Approximation ADC at 45nm [1] Kiran Kumar Kuna, [2] Koushik Mekala, [3] Md. Naseer Baba [4] Ameet Chavan Sreenidhi Institute of Science and Technology Yamnampet, Ghatkesar, Hyderabad, Telangana, India Abstract: With extensive digitization, Analog to Digital Converters (ADC) have become the cornerstone circuits in all modern electronics. Higher resolution, Low p ower consumption and Faster conversions are the primary pref erred features. For a most application the ADC circuit design is inflexible and aimed to meet certain specification. But f or electronics that offer application flexibility a reconfigurable/programmable ADC is desired. The proposed work pres ents a low power Analog to Digital converter that offers scal able resolution - 6 bit, 8 bit, 10 bit and 12 bit. The scalable ADC is designed at 45nm technology using Cadence GPDK model files. Index Terms ADC, Successive Approximation, Low Power,Analog VLSI I. INTRODUCTION An Analog-to-Digital Converter (AD C) is a device that converts an analog quantity (usually a voltage or a current) into digital representation. The ADC s are at thefront-end of any digital circuit. It interfaces the Analo g and the digital world. digital words depends on the resolution and the type of converter used. Since there is a tradeof f between many parameters of ADC so depending on th e application andinput signal bandwidth correspond ing converter is used to yield better results with good perfor mance and accuracy. II. SUCCESSIVE APPROXIMA TION BASED ADC Fig Block Diagram of ADC Setup A block diagram of Analog to digital c onverter is shown in Fig The setup takes analog input, the existing physical quantity in the nature, and co nverts it into an equivalent digital word. All these digital w ords are processed by the digital signal processors and giv e the appropriate results. They are the link between the analog world of transducers and the digital world of sign al processing and data handling. Analog to digital converter plays a vi tal role in sensor based applications. In order to process any existing quantity in the nature it is mandatory to convert t he quantity from analog form to digital representation so that it can be processed by the signal processors and provide appropriate results. The accuracy in representing the given quantity in The architecture of the successiv e approximation register ADC is shown in the below figure 2.1. The basic converter consists of four components i.e. a sample and hold circuit, comparator, digital to analog c onverter (DAC) and a successive approximation register (ADC controller). It performs the binary search algorithm in order to approximatethe input voltage, this b inary search is performed by the successive approximation re gister The SAR ADC is widely used in many communication systems, such as ultra-wideband and wireless sensor networks which require l ow-to-mediumresolutionconverters, with low power consumption. The basic architecture of the SAR ADC is simple. SAR ADC is implemented by using the binary search algorithm. SAR ADC consists of mainly 4 blocks namely sample and hold circuit, comparator circuit, successive approximation register and DAC. Each of these 4 blocks can be built using different circuits. In the above figure 2.1 A rchitecture of SAR ADC shown initially the N-bitregister(SAR) is set to midscale which implies that the MSB is set t o 1 and rest all the bits are set to 0. All Rights Reserved 2015 IJERECE 11

2 Accuracy increases by increasing sensitivity of the comparator. It consumes less power since circuit is not complex. It is reliable Capable of high speed Conversion time is clock rate times the number of bits. III. SAMPLE AND HOLD CIRCUIT The currently used sample and hold circuit is as shown in figure 3.1 below Fig Successive Approxim ation based ADC Therefore the DAC output is found to be Vref/2, where Vref is the supply voltage provided to the ADC. The analog input voltage is sampled signal a t its output in which the signal is hold for various periods of time. Now a comparison is performed between the first sample of the sampled signal(vin) and he DAC output(vdac = Vref/2) to determine the difference between the 2 values. If Vin > Vdac, comparator output is high or logic 1 is generated at its output. Then the nth bit of the register is unchanged(set to 1 only) and the (n-1)th bit is set to 1 as the DAC vaue is less when compared to the analog input sample value. But if the sample value is less than Vdac, comparator output is low or logic 0. In this case the nth bit is reset to 0 and the (n-1)th bit is set to 1. This tends to change the DAC output and then another comparison is followed between the first sample and the modified DAC output. This process continues till the LSB is reached and gets terminated. The conversion is finally complete for one sample value and an n-bit digital word is generated in the register Fig. 2.2 Basic Successive Approximation Register ADC The SAR based ADC offers following advantages Good ratio of speed to power. Compact design compared to other types which makes inexpensive. Only one comparator is required. Lack of latency makes it ideal for single shot and multiplexed data acquisition applications. Fig. 3.1: Sample and Hold circuit The sample and hold circuit that is being used consists of an inverter, transmission gate and a capacitor as shown in the figure. The clock signal is applied to the input of inverter with peak to peak voltage of 1.2v and the sinusoidal signal is applied to the transmission gate respectively. The operation of this circuit is as follows. During the positive cycle of clock, the transmission gate is short circuited and the current flows through the circuit and reaches the output. Sampling of input takes place, output follows input and the capacitor (5pF) gets charged. During the negative half cycle of the clock, the transmission gate is open circuited and the charged capacitor is now in hold position as there is no path for discharging. Here the output is observed as a constant value as the capacitor holds the charge. IV. DIGITAL TO ANALOG CONVERTER (DAC) A digital-to-analog converter (DAC or D-to-A) is a device for converting a digital (usually binary) code to an analog signal (current, voltage or charges). Digital-to- Analog Converters are the interface between the abstract digital world and the analog real life. Simple switches, a network of resistors, current sources or capacitors may implement this conversion. A DAC inputs a binary number and outputs an analog voltage or current signal. The below fig 4.1 shows block diagram of digital to analog convertor where the inputs are binary words and corresponding analog value is generated. Several DACs are available but due to some limitations of other convertors capacitive distributed DAC is chosen for successive approximation register ADC. In fast and high accurate ADC converters, the successive approximation method is All Rights Reserved 2015 IJERECE 12

3 commonly used. Accuracy and linearity in this system are determined by the DAC, while the conversion speed depends on the comparator response time and the settling time of the DAC. Fig. 4.1: Block Diagram DAC Setup In a successive approximation system the analog signal is approximated by the step by step built up analog outputvoltage of the DACIn the given below figure 4.2 capacitive dist ributed DAC is shown which consists of array of binary weighted capacitors with a reference voltage Vref and electronic switches. resolution are two important factors whic h are required for high speed applications. The comparator compares the voltages t hat appear at their inputs and outputs a voltage representing the sign of the net difference between them. The comparator is a circuit that compares an analog signal with another analog signal or reference and outputs a binary signa l based on the comparison. If the +, VP, the input of the comparator is at a greater potential than the -, VN, input, t he output of the comparator is a logic 1 and vice versa. The comparator compares an an alog signal with another analog signal ( reference) and outp uts a binary signal based on the comparison. Figure 5.1 shows the schematic symbol of the comparator and 5.2 shows its ideal transfer characteristics. VP is the input voltage applied to the positive input terminal of comparator and Vn is the reference voltage applied to the negative terminal of compa rator. Now if Vp, the input of the comparator is at a greater potential than the Vn, the reference voltage, then the output of the comparator is a logic 1, where as if the Vp is at a potential less than the Vn, the output of the comparator is at logic 0. A clocked comparator generally consists of two stages. In that first stage is to interface the input sig nals. The second (regenerative) stage consists of two cross coupled inverters, where each input is connected to the output of the other. In a CMOS based latch, the regenerative stage and its following stages consume low static power since the power ground path is switched off either by a NMOS or PMOS transistor. A. DYNAMIC LATCHED C OMPARATOR Fig. 4.2: Capacitive Distributed D AC For the capacitive distributed DAC ind ividual bits from the controller are given to the common bus terminal of the capacitors and when the MSB bit is 1 the corresponding capacitor connected to the Vref and all t he capacitors for which the input bit is zero are connected to the ground. So here all the parallel capacitors are add u p and produces a voltage of Vref/2. Similarly depending on the bits the capacitor either connects to Vref or ground, which produces corresponding analog output voltage on the basis of weighted capacitors. V. COMPARATOR Comparators are the basic building elements for designing modern analog and mixed signal systems. Speed and The dynamic latched co mparator is composed of two stages as shown in Fig The first stage is the interface stage which consists of all the transistors except two cross coupled inverters. T he second stage is the regenerative stage that is comprised of the two cross coupled inverters, where each input is connected to the output of the other. It operates in two phases.1) Interface phase and 2) Regeneration phase. It consists of single nmos tail transistor connected to ground. When clock i s low tail transistor is off and depending on Vp and Vn outpu t reaches to VDD or gnd. When clock is high tail transistor is on and both the outputs discharges to ground. There is reduction of both pow er and delay in dynamic latched comparator circuit over the double tail latched andpre-amplifier based clocked comparators. Double tail latched comparator has less power consumption but low speed because of more transistor count and preamplifier based clocked comparator has high speed because All Rights Reserved 2015 IJERECE 13

4 of less transistor count but power consumption is more because it uses an amplification stage, it consumes static power during the amplification period However, sinc e the pre-amplifier based clocked comparator is to work at high frequency, the energy consumption of the preamplifier b ased clocked comparator becomes comparable to the double tail latched comparator. pins (clk, go, cmp) and four output pins(result[8bit], valid, sample, value[8 bit]). Hence the performance o f the pre-amplifier based clocked comparator is limited by th e static power dissipation in the evaluation or regeneration phase. Due to fast speed, low power consumption, high input impedance and full- swing output, dynamic latched comparators are very attractive for many applications su ch as high-speed analog- todigital converters (ADCs), memory. sense amplifiers (SAs) and data receivers. They use positive feedback mechanism with one pair of back-to-back cross coupled inverters (latch) Fig Block Diagram of ADC Controller in order to convert a small input-voltage difference to a fullscale digital level in a short time. Thus dynamic latched The binary search starts with the most significant bit (MSB) comparator is suitable for both high speed and low power and works towards the least significant bit (LSB). For an 8 dissipation because of decrease in transistor count which bit resolution 8 comparisons are needed taking atleast 8 overcomes the proble m of double tail latch andpreamplifier based clocked comparators. The working of the controller follows the following clock cycles. sequence: On the initial positive edge of the controller clock it makes the sample output to high value so that input signal is sampled at the sample and hold circuit. On the next clock cycle the controller makes go input to high value (which indicates start of conversion) depending on the valid bit. At the moment go becomes high sample value is made low so that the value is kept in hold for comparison. The conversion starts when go becomes high. Generally for an N-bit resolution N conversions are performed which takes atleast N clock cycles. The conversion starts by making MSB bit of the value signal as 1 and remaining bits as zero. For each conversion the corresponding analog value is generated by the DAC circuit which is given as an input to the comparator, the comparator compares the DAC output with the value that is Fig. 5.1: Dynamic Latch Comparator held at the sample and hold circuit. Depending on the value of the comparator the controller either set or reset the VI. ADC CONTROLLER corresponding bit in the value to catch the input signal that is held. ADC controller is the core part of the Analog to digital convertor which controls the operation of the individual The decision of the controller is as follows initially the MSB Here the controller is designed by bit is set and remaining bits are reset. After the conversion if components. using the comparator value is high then for the second conversion successive approximationregister.asuccessive the controller retains the MSB bit and makes the next bit approximation register works by using a digital to analog convertor 1, this process continues as long as the comparator is high. (DAC) and a comparator to perform binary search in order to find If the the comparator value is low then the controller makes that input voltage. It performs the binary search algorithm in order to bit find to 0 and next bit to 1. In this manner it approximates the input voltage which is faster than conventional controllers with that the input signal. Finally at the end of conversion when uses counters to find the input voltage. the LSB bit is 1 the valid bit is made high which indicates the end of conversion(eof) that drives the go In the below figure 6.1 block diagram of the controller with signal to high so that the controllers takes the next sample. necessary input and output pins are shown. It consists of three input At the end of 8 conversions the 8 bit digital word for the All Rights Reserved 2015 IJERECE 14

5 corresponding analog sample is stored in the result. In this manner depending on the resolution the number of samples are decided and corresponding digital words for all the samples are generated by the controller. VII. SIMULATION RESULTS [2]Vinotha V, Menakadevi B, Design of Low- Voltage, Power Proposed Dynamic Clocked Comparator, International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 3, Issue 1, January [3]ALGN Aditya, G.Rakesh Chowdary, J. Meenakshi, T.Praveen Blessington, M.S.Vamsi Krishna Implementation of Low Power Successive Approximation ADC, International Conference on Signal Processing, Image Processing and Pattern Recognition [ICSIPRI] May 2013 [4]Yong Kui Yang, Xin Liu, Jun Zhou, Jia Hao Cheong, Minkyu Je, Wang Ling Goh, "A 0.5V 16nW ENOB SAR ADC forultra-low Power Sensor Applications", IEEE International Microwave Workshop Series on RF and Wireless Technologies for Biomedical and Healthcare Applications (IMWS-Bio), Dec [5]RVNR Suneel Krishna, Aleti Shankar, Design of Low Power SAR- ADC in 0.18μm Mixed-Mode CMOS Process, International Journal of Research in Computer and Communication Technology, Vol 2, Issue 8, August CONCLUSION A successive approximation scalable ADC is designed which consumes low power and the design is scalable providing variable resolution depending on the precision required for the application under execution. All the building blocks of the ADC are implemented at transistor level abstraction except for the scalable ADC controller which is implemented in Verilog HDL and ported into the analog environment. The scalable ADC is implemented using 45nm GPDK MOSFET models of Cadence ECAD tool. The simulated power is 1.565nW for one complete analog input cycle (msec). The proposed scalable ADC design finds applications in Data Acquisition Systems, Sensor based applications, Program Logic Controllers, and Video & Audio processing Systems. [6]Surya Kant k, Bhavana P. Shrivastava, Lowvoltage Power-efficientDynamic Latched Comparator, International Journal of Emerging Technology and Advanced Engineering, ISSN , ISO 9001:2008 Certified Journal, Volume 4, Issue 8, August 2014 [7]Singh, R.R.; Genov, R.; Kotamraju, R.T.; Mazhari, B., "Multi-stepbinary-weighted capacitive digital-toanalog converter architecture," incircuits and Systems, MWSCAS st Midwest Symposium on, vol., no., pp , Aug REFERENCES [1]N.Naga sudha, V. Narasimha Nayak, Dr. Fazal Noor Basha, S. RahiHussain, High Speed and Low Power Dynamic Latched Comparator for Air Craft Application, International Journal of Engineering Research and Applications (IJERA) ISSN: Vol. 2, Issue 3, May-Jun 2012, pp All Rights Reserved 2015 IJERECE 15