MCP79410/MCP79411/MCP79412

Transcription

1 MP79410/MP79411/MP79412 I 2 Real-ime lock/alendar with EEPROM, SRM, Unique ID and Battery Switchover Device Selection able Part Number Features: EEPROM (bits) SRM (Bytes) Unique ID MP Blank MP EUI-48 MP EUI-64 Real-ime lock/alendar (R), Battery Backed: - Hours, Minutes, Seconds, Day of Week, Day, Month and Year - Dual alarm with single output On-hip Digital rimming/alibration: - Range -127 to +127 ppm - Resolution 1 ppm Programmable Open-Drain Output ontrol: - LOU with 4 selectable frequencies - larm output 64 Bytes SRM, Battery Backed 1 bits EEPROM (128x8): - 8 bytes/page - Block/sector write protection - Protect none, 1/4, 1/2 or all of array Separate 64-Bit Unique ID: - User or factory programmable - Protected area - EUI-48 or EUI-64 M address - ustom ID programming utomatic V Switchover to VB Backup Supply Power-Fail ime-stamp for Battery Switchover Low-Power MOS echnology: - Dynamic urrent: 400 max read - Dynamic urrent: 3m max EEPROM write - Battery Backup urrent: 1.8V 100 khz and 400 khz ompatibility ESD Protection >4,000V More than 1 Million Erase/Write ycles Packages include 8-Lead SOI, SSOP, 2x3 DFN, MSOP Pb-Free and RoHS ompliant emperature Ranges: - Industrial (I): -40 to +85. Description: he MP7941X series of low-power Real-ime locks (R) uses digital timing compensation for an accurate clock/calendar, a programmable output control for versatility, a power sense circuit that automatically switches to the backup supply, and nonvolatile memory for data storage. Using a low-cost khz crystal, it tracks time using several internal registers. For communication, the MP7941X uses the I 2 bus. he clock/calendar automatically adjusts for months with fewer than 31 days, including corrections for leap years. he clock operates in either the 24-hour or 12-hour format with an M/PM indicator and settable alarm(s) to the second, minute, hour, day of the week, date or month. Using the programmable LOU, frequencies of , and khz and 1 Hz can be generated from the external crystal. long with the on-board Serial EEPROM and batterybacked SRM memory, a 64-bit protected space is available for a unique ID or M address to be programmed at the factory or by the end user. he device is fully accessible through the serial interface while V is between 1.8V and 5.5V, but can operate down to 1.3V for timekeeping and SRM retention only. he R series of devices are available in the standard 8-lead SOI, SSOP, MSOP and 2x3 DFN packages. Package ypes X1 X2 V B VSS X1 X2 V B VSS MSOP SOI, SSOP V MFP SL SD X1 1 X2 2 VB 3 VSS 4 V MFP SL SD DFN 8 V 7 MFP 6 SL 5 SD 2011 Microchip echnology Inc. Preliminary DS22266B-page 1

2 FIGURE 1-1: YPIL OPERING IRUI X1 R V X2 Oscillator ime-stamp/ larms SRM MFP VB VB Switch I 2 SL VSS EEPROM ID SD DS22266B-page 2 Preliminary 2011 Microchip echnology Inc.

3 1.0 ELERIL HRERISIS bsolute Maximum Ratings ( ) V...6.5V ll inputs and outputs w.r.t. VSS V to V +1.0V Storage temperature to +150 mbient temperature with power applied to +125 ESD protection on all pins 4 kv NOIE: Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. BLE 1-1: D HRERISIS D HRERISIS Electrical haracteristics: Industrial (I): V = +1.8V to 5.5V = -40 to +85 Param. No. Sym. haracteristic Min. yp. Max. Units onditions SL, SD pins D1 VIH High-level input voltage 0.7 V V D2 VIL Low-level input voltage 0.3 V V V = 2.5V to 5.5V 0.2 V D3 VHYS Hysteresis of Schmitt 0.05 V (Note 1) rigger inputs V (SD, SL pins) D4 VOL Low-level output voltage (MFP, SD) 0.40 V IOL = 3.0 V = 4.5V IOL = 2.1 V = 2.5V D5 ILI Input leakage current ±1 VIN = VSS or V D6 ILO Output leakage current ±1 VOU = VSS or V D7 IN, OU Pin capacitance (SD, SL and MFP) 10 pf V = 5.0V (Note 1) = 25, f = 400 khz D8 I Read Operating current 400 V = 5.5V, SL = 400 khz I Write EEPROM 3 m V = 5.5V D9 I Read Operating current 300 V = 5.5V, SL = 400 khz I Write SRM 400 V = 5.5V, SL = 400 khz D10 IS Standby current (Note 2) 5 V = 5.5V, SL = SD = V D11 IB VB Standby urrent 700 n VB = 25 (Note 2) D12 VRIP VB hange Over V 1.5V typical at MB = 25 D13 VF V Fall ime (Note 1) 300 s From VRIP (max) to VRIP (min) D14 VR V Rise ime (Note 1) 0 s From VRIP (min) to VRIP (max) D15 VB VB Voltage Range (Note 1) V Note 1: his parameter is periodically sampled and not 100% tested. 2: Standby with oscillator running 2011 Microchip echnology Inc. Preliminary DS22266B-page 3

4 BLE 1-2: HRERISIS HRERISIS Param. No. 1 FL lock frequency 2 HIGH lock high time LOW lock low time Electrical haracteristics: Industrial (I): V = +1.8V to 5.5V = -40 to +85 Symbol haracteristic Min. Max. Units onditions 4 R SD and SL rise time (Note 1) 5 F SD and SL fall time (Note 1) 6 HD:S Start condition hold time SU:S Start condition setup time HD:D Data input hold time 0 ns 9 SU:D Data input setup time SU:SO Stop condition setup time Output valid from clock 12 BUF Bus free time: ime the bus must be free before a new transmission can start 13 SP Input filter spike suppression (SD and SL pins) 14 W Write cycle time (byte or page) khz 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V ns 1.8V V < 2.5V 2.5V V 5.5V 50 ns (Note 1 and Note 2) 5 ms 15 Endurance 1M cycles 25, V = 5.5V Page mode (Note 3) Note 1: Not 100% tested. 2: he combined SP and VHYS specifications are due to new Schmitt rigger inputs, which provide improved noise spike suppression. his eliminates the need for a I specification for standard operation. 3: his parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the otal Endurance Model which can be obtained from Microchip s web site at DS22266B-page 4 Preliminary 2011 Microchip echnology Inc.

5 FIGURE 1-2: BUS IMING D 5 2 D4 4 SL SD In SD Out Microchip echnology Inc. Preliminary DS22266B-page 5

6 2.0 PIN DESRIPIONS he descriptions of the pins are listed in able 2-1. FIGURE 2-1: DEVIE PINOUS SOI/DFN/MSOP/SSOP X1 1 8 Vcc X2 2 7 MFP VB 3 6 SL Vss 4 5 SD 2.1 Serial Data (SD) his is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SD bus requires a pull-up resistor to V (typically 10 k for 100 khz, 2 k for 400 khz). For normal data transfer SD is allowed to change only during SL low. hanges during SL high are reserved for indicating the Start and Stop conditions. 2.2 Serial lock (SL) his input is used to synchronize the data transfer from and to the device. BLE 2-1: PIN DESRIPIONS Pin Name Pin Function Vss Ground SD Bidirectional Serial Data SL Serial lock X1 Xtal Input, External Oscillator Input X2 Xtal Output VB Battery Backup Input (3V yp) MFP Multi Function Pin Vcc +1.8V to +5.5V Power Supply DS22266B-page 6 Preliminary 2011 Microchip echnology Inc.

7 3.0 I 2 BUS HRERISIS 3.1 I 2 Interface he MP7941X supports a bidirectional 2-wire bus and data transmission protocol. device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. he bus has to be controlled by a master device which generates the Start and Stop conditions, while the MP7941X works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated BUS HRERISIS he following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. hanges in the data line while the clock line is high will be interpreted as a Start or Stop condition. ccordingly, the following bus conditions have been defined (Figure 3-1) Bus not Busy () Both data and clock lines remain high Start Data ransfer (B) high-to-low transition of the SD line while the clock (SL) is high determines a Start condition. ll commands must be preceded by a Start condition Stop Data ransfer () low-to-high transition of the SD line while the clock (SL) is high determines a Stop condition. ll operations must end with a Stop condition Data Valid (D) he state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. he data on the line must be changed during the low period of the clock signal. here is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. he number of the data bytes transferred between the Start and Stop conditions is determined by the master device cknowledge Each receiving device, when addressed, is obliged to generate an cknowledge signal after the reception of each byte. he master device must generate an extra clock pulse which is associated with this cknowledge bit. Note: he MP7941X does not generate any EEPROM cknowledge bits if an internal programming cycle is in progress. he user may still access the SRM and R registers during an EEPROM write. device that acknowledges must pull down the SD line during the cknowledge clock pulse in such a way that the SD line is stable-low during the high period of the cknowledge-related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NO generating an cknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (MP7941X) will leave the data line high to enable the master to generate the Stop condition. FIGURE 3-1: D RNSFER SEQUENE ON HE SERIL BUS SL () (B) (D) (D) () () SD Start ondition ddress or cknowledge Valid Data llowed to hange Stop ondition 2011 Microchip echnology Inc. Preliminary DS22266B-page 7

8 FIGURE 3-2: NOWLEDGE IMING cknowledge Bit SL SD Data from transmitter Data from transmitter ransmitter must release the SD line at this point allowing the Receiver to pull the SD line low to acknowledge the previous eight bits of data. Receiver must release the SD line at this point so the ransmitter can continue sending data DEVIE DDRESSING ND OPERION control byte is the first byte received following the Start condition from the master device (Figure 3-2). he control byte consists of a control code; for the MP7941X this is set as for read and write operations for the EEPROM. he control byte for accessing the SRM and R registers are set to he R registers and the SRM share the same address space. he last bit of the control byte defines the operation to be performed. When set to a 1 a read operation is selected, and when set to a 0 a write operation is selected. he next byte received defines the address of the data byte (Figure 3-3). he upper address bits are transferred first, followed by the Least Significant bits (LSb). Following the Start condition, the MP7941X monitors the SD bus, checking the device type identifier being transmitted. Upon receiving an or code, the slave device outputs an cknowledge signal on the SD line. Depending on the state of the R/W bit, the MP7941X will select a read or write operation. FIGURE 3-3: DDRESS SEQUENE BI SSIGNMENS EEPROM ONROL BYE DDRESS BYE R/W X 0 ONROL ODE X = Don t are { 7 is Don t are for normal EEPROM operations, but is used to access unique ID location and SUS register.) SRM R ONROL BYE DDRESS BYE R/W X 0 ONROL ODE X = Don t are DS22266B-page 8 Preliminary 2011 Microchip echnology Inc.

9 3.1.3 NOWLEDGE POLLING Since the device will not acknowledge an EEPROM command during an EEPROM write cycle, this can be used to determine when the cycle is complete. his feature can be used to maximize bus throughput. Once the Stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. polling can be initiated immediately. his involves the master sending a Start condition, followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no will be returned. If no is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the, and the master can then proceed with the next read or write command. See Figure 3-4 for the flow diagram. FIGURE 3-4: NOWLEDGE POLLING FLOW Send EE Write ommand Send Stop ondition to Initiate EE Write ycle Send Start Send ontrol Byte with R/W = 0 Did Device cknowledge ( = 0)? NO YES Next Operation 2011 Microchip echnology Inc. Preliminary DS22266B-page 9

10 4.0 R FUNIONLIY he MP7941x family is a highly integrated R. Onboard time and date counters are driven from a lowpower oscillator to maintain the time and date. n integrated V switch enables the device to maintain the time and date and also the contents of the SRM during a V power failure. 4.1 R MEMORY MP he R registers are contained in addresses 0x00h-0x1fh. 64 bytes of user-accessable SRM are located in the address range 0x20-0x5f. he SRM memory is a separate block from the R control and onfiguration registers. ll SRM locations are battery-backed-up during a V power fail. Unused locations are not accessible, MP7941X will no after the address byte if the address is out of range. he shaded areas are not implemented and read as 0. No error checking is provided when loading time and date registers. ddresses 0x00h-0x06h are the R ime and Date registers. hese are read/write registers. are must be taken when writing to these registers with the oscillator running. Incorrect data can appear in the ime and Date registers if a write is attempted during the time frame where these internal registers are being incremented. he user can minimize the likelihood of data corruption by ensuring that any writes to the ime and Date registers occur before the contents of the second register reach a value of 0x59H. ddresses 0x07h-0x09h are the device onfiguration, alibration and ID Unlock registers. ddresses 0x0h-0x10h are the larm 0 registers. hese are used to set up the larm 0, the Interrupt polarity and the larm 0 ompare. ddresses 0x11h-0x17h are the same as 0x0Bh- 0x11h but are used for larm 1. ddresses 0x18h-0x1Fh are used for the timestamp feature. he Memory Map is shown in able 4-1. DS22266B-page 10 Preliminary 2011 Microchip echnology Inc.

11 BLE 4-1: R MEMORY MP ddress Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Range Reset State 00h S 10 Seconds Seconds Seconds h 01h 10 Minutes Minutes Minutes h 02h 10 Hour 10 Hour Hour Hours M/PM 00h 12/24 M/PM h OSON VB VBEN Day Day h 04h 10 Date Date Date h 05h LP 10 Month Month Month h 06h 10 Year Year Year h 07h OU SQWE LM1 LM0 EXOS RS2 RS1 RS0 ontrol Reg. 80h 08h LIBRION alibration 00h 09h UNIQUE UNLO ID SEQUENE Unlock ID 00h 0h 10 Seconds Seconds Seconds h 0Bh 10 Minutes Minutes Minutes h 0h 10 Hour 10 Hours Hour Hours M/PM 00h 12/24 M/PM Dh LM0POL LM02 LM01 LM00 LM0IF Day Day h 0Eh 10 Date Date Date h 0Fh 10 Month Month Month h 10h Reserved Do not use Reserved 01h 11h 10 Seconds Seconds Seconds h 12h 10 Minutes Minutes Minutes h 13h 10 Hour 10 Hours Hour Hours M/PM 00h 12/24 M/PM h LM1POL LM12 LM11 LM10 LM1IF Day Day h 15h 10 Date Date Date h 16h 10 Month Month Month h 17h Reserved - Do not use Reserved 01h 18h 10 Minutes Minutes 00h 19h 10 Hour 10 Hours Hour 00h 12/24 M/PM 1h 10 Date Date 00h 1Bh Day 10 Month Month 00h 1h 10 Minutes Minutes 00h 1Dh 10 Hour 10 Hours Hour 00h 12/24 M/PM 1Eh 10 Date Date 00h 1Fh Day 10 Month Month 00h 2011 Microchip echnology Inc. Preliminary DS22266B-page 11

12 4.1.1 R REGISER DDRESSES 0x00h ontains the BD seconds and 10 seconds. he range is 00 to 59. Bit 7 in this register is used to start or stop the on-board crystal oscillator. Setting this bit to a 1 starts the oscillator and clearing this bit to a 0 stops the on-board oscillator. 0x01h ontains the BD minutes and 10 minutes. he range is 00 to 59. 0x02h ontains the BD hour in bits 3:0. Bits 5:4 contain either the 10 hour in BD for 24-hour format or the M/PM indicator and the 10-hour bit for 12-hour format. Bit 6 determines the hour format. Setting this bit to 0 enables 24-hour format, setting this bit to 1 enables 12-hour format. 0x03h ontains the BD day. he range is 1-7. dditional bits are also used for configuration and status. Bit 3 is the VBEN bit. If this bit is set, the internal circuitry is connected to the VB pin when V fails. If this bit is 0 then the VB pin is disconnected and the only current drain on the external battery is the VB pin leakage. Bit 4 is the VB bit. his bit is set by hardware when the V fails and the VB is used to power the Oscillator and the R registers. his bit is cleared by software. learing this bit will also clear all the time-stamp registers. Bit 5 is the OSON bit. his is set and cleared by hardware. If this bit is set, the oscillator is running, if cleared, the oscillator is not running. his bit does not indicate that the oscillator is running at the correct frequency. he R will wait 32 oscillator cycles before the bit is set. he R will wait roughly 32 clock cycles to clear this bit. 0x04h ontains the BD date and 10 date. he range is x05h ontains the BD month. Bit 4 contains the 10 month. Bit 5 is the Leap Year bit, which is set during a leap year and is read-only. 0x06h ontains the BD year and 10 year. he Range is x07h Is the ontrol register. Bit 7 is the OU bit. his sets the logic level on the MFP when not using this as a square wave output. Bit 6 is the SQWE bit. Setting this bit enables the divided output from the crystal oscillator. Bits 5:4 determine which alarms are active No larms are active - 01 larm 0 is active - 10 larm 1 is active - 11 Both larms are active Bit 3 is the EXOS enable bit. Setting this bit will allow an external khz signal to drive the R registers eliminating the need for an external crystal. Bit 2:0 sets the internal divider for the khz oscillator to be driven to the MFP. he duty cycle is 50%. he output is responsive to the alibration register. he following frequencies are available: Hz khz khz khz - 1xx enables the al output function. al output appears on MFP if SQWE is set (64 Hz Nominal). Note: he R counters will continue to increment during the calibration. 0x08h is the alibration register. his is an 8-bit register that is used to add or subtract clocks from the R counter every minute. he MSB is the sign bit and indicates if the count should be added or subtracted. he remaining 7 bits, with each bit adding or subtracting 2 clocks, give the user the ability to add or subtract up to 254 clocks per minute. 0x09h is the unlock sequence address. o unlock write access to the unique ID area in the EEPROM, a sequence must be written to this address in separate commands. he process is fully detailed in Section Unlock Sequence. 0x0h-0x0fh and 0x11-0x16h are the larm 0 and larm 1 registers. he bits are the same as the R bits with the following differences: Locations 0x10h and 0x17h are reserved and should not be used to allow for future device compatibility. 0x0Dh/0x14h has additional bits for alarm configuration. LMxPOL: his bit specifies the level that the MFP will drive when the alarm is triggered. LM2POL is a copy of LM1POL. he default state of the MFP when used for alarms is the inverse of LM1POL. LMxIF: his is the larm Interrupt Fag. his bit is set in hardware if the alarm was triggered. he bit is cleared in software. DS22266B-page 12 Preliminary 2011 Microchip echnology Inc.

13 LMx2:0: hese onfiguration bits determine the alarm match. he logic will trigger the alarm based on one of the following match conditions: 000 Seconds match 001 Minutes match 010 Hours match (takes into account 12/24 hour) 011 Matches the current day, interrupt at a.m. Example: 12 midnight on 100 Date 101 RESERVED 110 RESERVED 111 Seconds, Minutes, Hour, Day, Date, Month he 12/24-hour bits 0xh.6 and 0x13h.6 are copies of the bit in 0x02h.6. he bits are read-only. 0x18h-0x1Bh are used for the timesaver function. hese registers are loaded at the time when V fails and the R operates on the VB. he VB bit is also set at this time. hese registers are cleared when the VB bit is cleared in software. 0x1h-0x1Fh are used for the timesaver function. hese registers are loaded at the time when V is restored and the R switches to VDD. hese registers are cleared when the VB bit is cleared in software. Note: It is strongly recommended that the timesaver function only be used when the oscillator is running. his will ensure accurate functionality. 4.2 FEURES SUS REGISER he SUS register is in the nonvolatile EEPROM array. o access the SUS register, the address of 0xFFh is written to and read from. polling may be used to determine if the write is complete. he bits in this register are defined as: Bit 3:2 are the EEPROM array block protection bits. hese bits are in the nonvolatile EEPROM array. his allows protection of the following areas: - 00 None of the array is protected he upper 1/4 of the array 0x60h-0x7fh is protected he upper 1/2 of the array 0x40h-0x7fh is protected ll of the array 0x00-0x7fh is protected. he unused bits are reserved at this time and read as 0. With the current address read operation, the address is not incremented. onsequently, the subsequent reads are done from the same location. If multiple bytes are loaded to the SUS register, only the last byte is written UNLO SEQUENE he unique ID location is user accessible by using the unlock ID sequence. he unique ID location is 64-bits (8 bytes) and is stored in EEPROM locations 0xF0 to 0xF7. his location can be read at any time, however, a write is inhibited until unlocked. o unlock the write access to this location the following sequence must be completed: single write of 0x55h to address 0x09. Stop single write of 0xh to address 0x09. Stop his will allow the unique EEPROM locations to be written. fter the byte or page write to these locations, the write sequence is initiated by the Stop condition. t this time, the ID locations are locked and no further writes are possible to this location unless a complete unlock sequence is repeated Microchip echnology Inc. Preliminary DS22266B-page 13

14 4.2.3 LIBRION he MP7941X utilizes digital calibration to correct for inaccuracies of the input clock source (either external or crystal). alibration is enabled by setting the value of the alibration register at address 08H. alibration is achieved by adding or subtracting a number of input clock cycles per minute in order to achieve ppm level adjustments in the internal timing function of the MP7941X. he MSB of the alibration register is the sign bit, with a 1 indicating subtraction and a 0 indicating addition. he remaining seven bits in the register indicate the number of input clock cycles (multiplied by two) that are subtracted or added per minute to the internal timing function. he internal timing function can be monitored using the MFP open-drain output pin by setting bit [6] (SQWE) and bits [2:0] (RS2, RS1, RS0) of the control register at address 07H. Note that the MFP output waveform is disabled when the MP7941X is running in VB mode. With the SQWE bit set to 1, there are two methods that can be used to observe the internal timing function of the MP7941X:. RS2 BI SE O 0 With the RS2 bit set to 0, the RS1 and RS0 bits enable the following internal timing signals to be output on the MFP pin: RS2 RS1 RS0 Output Signal Hz khz khz khz he frequencies listed in the table presume an input clock source of exactly khz. In terms of the equivalent number of input clock cycles, the table becomes: RS2 RS1 RS0 Output Signal With regards to the calibration function, the alibration register setting has no impact upon the MFP output clock signal when bits RS1 and RS0 are set to 11. he setting of the alibration register to a non-zero value (i.e., values other than 00H or 80H) enables the calibration function which can be observed on the MFP output pin. he calibration function can be expressed in terms of the number of input clock cycles added/subtracted from the internal timing function. With bits RS1 and RS0 set to 00, the calibration function can be expressed as: output = ( /- (2 * LREG)) input where: output = clock period of MFP output signal input = clock period of input signal LREG = decimal value of alibration register setting and the sign is determined by the MSB of alibration register. Since the calibration is done once per minute (i.e., when the internal minute counter is incremented), only one cycle in sixty of the MFP output waveform is affected by the calibration setting. lso note that the duty cycle of the MFP output waveform will not necessarily be at 50% when the calibration setting is applied. With bits RS1 and RS0 set to 01 or 10, the calibration function can not be expressed in terms of the input clock period. In the case where the MSB of the alibration register is set to 0, the waveform appearing at the MFP output pin will be delayed, once per minute, by twice the number of input clock cycles defined in the alibration register. he MFP waveform will appear as: FIGURE 4-1: RS1 ND RS0 WIH ND WIHOU LIBRION Delay DS22266B-page 14 Preliminary 2011 Microchip echnology Inc.

15 In the case where the MSB of the alibration register is set to 1, the MFP output waveforms that appear when bits RS1 and RS0 are set to 01 or 10 are not as responsive to the setting of the alibration register. For example, when outputting the khz waveform (RS1, RS0 set to 01 ), the output waveform is generated using only eight input clock cycles. onsequently, attempting to subtract more than eight input clock cycles from this output does not have a meaningful effect on the resulting waveform. ny effect on the output will appear as a modification in both the frequency and duty cycle of the waveform appearing on the MFP output pin. B.RS2 BI SE O 1 With the RS2 bit set to 1, the following internal timing signal is output on the MFP pin: RS2 RS1 RS0 Output Signal 1 x x 64.0 Hz he frequency listed in the table presumes an input clock source of exactly khz. In terms of the equivalent number of input clock cycles, the table becomes: RS2 RS1 RS0 Output Signal 1 x x 512 Unlike the method previously described, the calibration setting is continuously applied and affects every cycle of the output waveform. his results in the modulation of the frequency of the output waveform based upon the setting of the alibration register. Using this setting, the calibration function can be expressed as: output = (2 * (256 +/- (2 * LREG))) input where: output = clock period of MFP output signal input = clock period of input signal LREG = decimal value of the alibration register setting, and the sign is determined by the MSB of the alibration register. Since the calibration is done every cycle, the frequency of the output MFP waveform is constant MFP Pin 7 is a multi-function pin and supports the following functions: Use of the OU bit in the ontrol register for single bit I/O larm Outputs vailable in VB mode FOU mode driven from a FOS divider Not available in VB mode he internal control logic for the MFP is connected to the switched internal supply bus, this allows operation in VB mode. he larm Output is the only mode that operates in VB mode, other modes are suspended VB If the VB feature is not being used, the VB pin should be connected to GND. low-value series resistor is recommended between the external battery and the VB pin. he VB point is defined as 1.5V typical. When VDD falls below 1.5V the system will continue to operate the R and SRM using the VB supply. he following conditions apply: BLE 4-2: Supply ondition Read/Write ccess Powered By V < VRIP, V < VB No VB V > VRIP, V < VB Yes V V > VRIP, V > VB Yes V RYSL SPES he MP7941X has been designed to operate with a standard 32 khz crystal. Devices with a specified load capacitance of either 12pF or 6pF can be used. he end user should fully validate the chosen crystal across all the expected design parameters of the system to ensure correct operation. he following crystals have been tested and shown to work with the MP7941X: M200S 12pF surface mount crystals from itizen ES pF surface mount crystals from ES IN FS206 12pF leaded crystals from itizen his is not a definitive list and all crystals should be tested in the target application across all temperature, voltage and other significant environmental conditions Microchip echnology Inc. Preliminary DS22266B-page 15

16 4.2.7 POWER-FIL IME-SMP he MP7941X family of R devices feature a power-fail time-stamp feature. his feature will save the time at which V crosses the VRIP voltage. o use this feature, a VB supply must be present and the oscillator must also be running. here are two separate sets of registers that are used to record this information: he first set located at 0x18h through 0x1Bh are loaded at the time when V fails and the R operates on the VB. he VB (register 0x03h bit 4) bit is also set at this time. he second set of registers, located at 0x1h through 0x1Fh, are loaded at the time when V is restored and the R switches to V. he power-fail time-stamp registers are cleared when the VB bit is cleared in software. DS22266B-page 16 Preliminary 2011 Microchip echnology Inc.

17 5.0 ON BORD MEMORY he MP7941X has both on-board EEPROM memory and Battery-Backed SRM. he SRM is arranged as 64 x 8 bytes and is retained when the V supply is removed, provided the VB supply is present and enabled. he EEPROM is organized as 128 x 8 bytes. he EEPROM is nonvolatile memory and does not require the VB supply for retention. 5.1 SRM FIGURE 5-1: SRM/R BYE WRIE BUS IVIY MSER SD LINE S R ONROL BYE DDRESS BYE D S x P S O P BUS IVIY FIGURE 5-2: BUS IVIY MSER SD LINE BUS IVIY SRM/R MULIPLE BYE WRIE S R ONROL BYE DDRESS BYE D BYE 0 D BYE N S x P S O P he 64 bytes of user SRM are at location 0x20h and can be accessed during an R update. Upon POR the SRM will be in an undefined state. Writing to the SRM and R is accomplished in a similar way to writing to the EEPROM (as described later in this document) with the following considerations: here is no page. he entire 64 bytes of SRM or 32 bytes of R register can be written in one command. he SRM allows an unlimited number of read/ write cycles with no cell wear out. he R and SRM are not accessible when the device is running on the external VB. he R and SRM are separate blocks. he SRM array may be accessed during an R update. Read and write access is limited to either the R register block or the SRM array. he ddress Pointer will rollover to the start of the addressed block. Data written to the R and SRM are on a per byte basis. Note: Entering an address past 5F for an SRM operation will result in the MP7941X not acknowledging the address Microchip echnology Inc. Preliminary DS22266B-page 17

18 5.2 EEPROM EEPROM BYE WRIE Following the Start condition from the master, the control code and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. his indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an cknowledge bit during the ninth clock cycle. herefore, the next byte transmitted by the master is the word address and will be written into the ddress Pointer of the MP7941X. fter receiving another cknowledge signal from the MP7941X, the master device transmits the data word to be written into the addressed memory location. he MP7941X acknowledges again and the master generates a Stop condition. his initiates the internal write cycle, and, during this time, the MP7941X does not generate cknowledge signals for EEPROM write commands. If an attempt is made to write to an address and the protection is set then the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. fter a byte write command, the internal address counter will point to the address location following the one that was just written. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being transmitted. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size ) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Note: ddressing undefined EEPROM locations will result in the MP7941X not acknowledging the address EEPROM PGE WRIE he write control byte, word address, and the first data byte are transmitted to the MP7941X in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 7 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. fter receipt of each word, the three lower ddress Pointer bits are internally incremented by one. If the master should transmit more than 8 bytes prior to generating the Stop condition, the address counter will roll over and the data received previously will be overwritten. s with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 5-4). DS22266B-page 18 Preliminary 2011 Microchip echnology Inc.

19 FIGURE 5-3: EE BYE WRIE BUS IVIY MSER SD LINE S R ONROL BYE DDRESS BYE D S x P S O P BUS IVIY x = don t care for 1 devices FIGURE 5-4: BUS IVIY MSER SD LINE BUS IVIY EE PGE WRIE S R ONROL BYE DDRESS BYE D BYE 0 D BYE 7 S x P x = don t care for 1 devices S O P BLO PROEION he EEPROM does not support a hardware write protection pin, however, software block protection is available to the use and is configured using the SUS register RED OPERION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. here are three basic types of read operations: current address read, random read, and sequential read. he SRM array can be read in the same way as the EEPROM using the control byte for the SRM with a valid address urrent ddress Read he MP7941X contains an address counter that maintains the address of the last word accessed, internally incremented by one. herefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the MP7941X issues an cknowledge and transmits the 8-bit data word. he master will not acknowledge the transfer but does generate a Stop condition and the MP7941X discontinues transmission (Figure 5-1). FIGURE 5-1: BUS IVIY MSER SD LINE BUS IVIY S R Random Read URREN DDRESS RED (EEPROM SHOWN) ONROL BYE S D BYE Random read operations allow the master to access any memory location in a random manner. o perform this type of read operation, first the word address must be set. his is done by sending the word address to the MP7941X as part of a write operation (R/W bit set to 0 ). fter the word address is sent, the master generates a Start condition following the cknowledge. his terminates the write operation, but not before the internal ddress Pointer is set. hen, the master issues the control byte again but with the R/W bit set to a one. he MP7941X will then issue an cknowledge and transmit the 8-bit data word. he master will not acknowledge the transfer but it does generate a Stop condition which causes the MP7941X to discontinue transmission (Figure 5-2). fter a random read command, the internal address counter will point to the address location following the one that was just read. N O S O P P 2011 Microchip echnology Inc. Preliminary DS22266B-page 19

20 Sequential Read Sequential reads are initiated in the same way as a random read except that after the MP7941X transmits the first data byte, the master issues an cknowledge as opposed to the Stop condition used in a random read. his cknowledge directs the MP7941X to transmit the next sequentially addressed 8-bit word (Figure 5-3). Following the final byte transmitted to the master, the master will NO generate an cknowledge but will generate a Stop condition. o provide sequential reads, the MP7941X contains an internal ddress Pointer which is incremented by one at the completion of each operation. his ddress Pointer allows the entire memory contents to be serially read during one operation. he internal ddress Pointer will automatically roll over to the start of the Block. FIGURE 5-2: RNDOM RED (EEPROM SHOWN) BUS IVIY MSER SD LINE BUS IVIY S R ONROL BYE DDRESS BYE S R ONROL BYE D BYE S S P N O S O P FIGURE 5-3: BUS IVIY MSER SD LINE BUS IVIY SEQUENIL RED (EEPROM SHOWN) ONROL BYE D n D n + 1 D n + 2 D n + X N O S O P P 5.3 Unique ID he MP7941X features an additional 64-bit unique ID area. his is separate and in addition to the 1 of onboard EEPROM. he unique ID is located at addresses 0xF0 through 0xF7. Reading the unique ID requires the user to simply address these bytes. he unique ID area is protected to prevent unintended writes to these locations. he unlock sequence is detailed in Unlock Sequence. he unique ID can be factory programmed on some devices to provide a unique IEEE EUI-48 or EUI-64 value. In addition, customer-provided codes can also be programmed. DS22266B-page 20 Preliminary 2011 Microchip echnology Inc.

21 6.0 PGING INFORMION 6.1 Package Marking Information 8-Lead SOI (3.90 mm) Example: XXXXX XXYYWW NNN 79410I SN e F 8-Lead SSOP Example: XXXX YWW NNN 7941 I527 13F 8-Lead MSOP Example: XXXXX YWWNNN 79401I 52713F 8-Lead 2x3 DFN Example: XXX YWW NN st Line Marking odes Part Number SSOP MSOP DFN MP P MP Q MP R Note: = emperature grade NN = lphanumeric traceability code Legend: XX...X ustomer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week 01 ) NNN e3 lphanumeric traceability code Pb-free JEDE designator for Matte in (Sn) * his package is Pb-free. he Pb-free JEDE designator ( e3) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information Microchip echnology Inc. Preliminary DS22266B-page 21

22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at DS22266B-page 22 Preliminary 2011 Microchip echnology Inc.

23 Note: For the most current package drawings, please see the Microchip Packaging Specification located at Microchip echnology Inc. Preliminary DS22266B-page 23

24 DS22266B-page 24 Preliminary 2011 Microchip echnology Inc.

25 D N E E1 NOE 1 b 1 2 e 2 c φ 1 L1 L 2011 Microchip echnology Inc. Preliminary DS22266B-page 25

26 Note: For the most current package drawings, please see the Microchip Packaging Specification located at DS22266B-page 26 Preliminary 2011 Microchip echnology Inc.

27 D N E1 E NOE e b 2 c φ 1 L1 L 2011 Microchip echnology Inc. Preliminary DS22266B-page 27

28 Note: For the most current package drawings, please see the Microchip Packaging Specification located at DS22266B-page 28 Preliminary 2011 Microchip echnology Inc.

29 Note: For the most current package drawings, please see the Microchip Packaging Specification located at Microchip echnology Inc. Preliminary DS22266B-page 29

30 Note: For the most current package drawings, please see the Microchip Packaging Specification located at DS22266B-page 30 Preliminary 2011 Microchip echnology Inc.

31 2011 Microchip echnology Inc. Preliminary DS22266B-page 31

32 PPENDIX : REVISION HISORY Revision (10/2010) Original release of this document. Revision B (03/2011) Minor typographical edits; dded ppendix B: Device Errata PPENDIX B: DEVIE ERR Devices with silicon revision prior to 4 (date code prior to 11/10) have an errata where the M/PM bit (Bit 5 in register 02h) may be flipped if the oscillator is stopped. his is coincident with the OSON bit getting cleared. his can occur due to the following conditions: he oscillator is stopped on the application. he oscillator is stopped by clearing the S bit (Bit 7 in register 00h). he external MOS source is stopped in EXOS mode. he work-around is to determine when the OSON bit is cleared and check in software for M/PM bit corruption. Devices with silicon revision 4 or later (date code after 11/09) do not have this issue. DS22266B-page 32 Preliminary 2011 Microchip echnology Inc.

33 HE MIROHIP WEB SIE Microchip provides online support via our WWW site at his web site is used as a means to make files and information easily available to customers. ccessible by using your favorite Internet browser, the web site contains the following information: Product Support Data sheets and errata, application notes and sample programs, design resources, user s guides and hardware support documents, latest software releases and archived software General echnical Support Frequently sked Questions (FQ), technical support requests, online discussion groups, Microchip consultant program member listing Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives USOMER SUPPOR Users of Microchip products can receive assistance through several channels: Distributor or Representative Local Sales Office Field pplication Engineer (FE) echnical Support Development Systems Information Line ustomers should contact their distributor, representative or field application engineer (FE) for support. Local sales offices are also available to help customers. listing of sales offices and locations is included in the back of this document. echnical support is available through the web site at: USOMER HNGE NOIFIION SERVIE Microchip s customer notification service helps keep customers current on Microchip products. Subscribers will receive notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. o register, access the Microchip web site at Under Support, click on ustomer hange Notification and follow the registration instructions Microchip echnology Inc. Preliminary DS22266B-page 33

34 REDER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FX your comments to the echnical Publications Manager at (480) Please list the following information, and use this outline to provide us with your comments about this document. O: RE: echnical Publications Manager Reader Response otal Pages Sent From: Name ompany ddress ity / State / ZIP / ountry elephone: ( ) - pplication (optional): Would you like a reply? Y N FX: ( ) - Device: MP7941X Literature Number: DS22266B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS22266B-page 34 Preliminary 2011 Microchip echnology Inc.

35 PRODU IDENIFIION SYSEM o order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering combination is listed below. PR NO. X /XX Device emperature Range Package Device: MP79410 = 1.8V - 5.5V I 2 Serial R MP79410 = 1.8V - 5.5V I 2 Serial R MP79411 = 1.8V - 5.5V I 2 Serial R, EUI-48 M MP79411 = 1.8V - 5.5V I 2 Serial R, EUI-48 M (ape and Reel) MP79412 = 1.8V - 5.5V I 2 Serial R, EUI-64 M MP79412 = 1.8V - 5.5V I 2 Serial R, EUI-64 M (ape and Reel) emperature Range: I = -40 to +85 Package: SN = 8-Lead Plastic Small Outline (3.90 mm body) S = 8-Lead Plastic hin Shrink Small Outline (4.4 mm) MS = 8-Lead Plastic Micro Small Outline MNY (1) = 8-Lead Plastic Dual Flat, No Lead Examples: a) MP79410-I/SN: Industrial emperature, SOI package. b) MP79410-I/SN: Industrial emperature, SOI package, ape and Reel. c) MP79410-I/MNY: Industrial emperature, DFN package, ape and Reel. d) MP79411-I/SN: Industrial emperature, SOI package, EUI-48 M. e) MP79411-I/MS: Industrial emperature MSOP package, EUI-48 M. f) MP79412-I/SN: Industrial emperature, SOI package, EUI-64 M. g) MP79412-I/S: Industrial emperature, SSOP package, EUI-64 M. h) MP79412-I/S: Industrial emperature, SSOP package, ape and Reel, EUI-64 M. Note 1: Y indicates a Nickel Palladium Gold (NiPdu) finish Microchip echnology Inc. Preliminary DS22266B-page 35

36 NOES: DS22266B-page 36 Preliminary 2011 Microchip echnology Inc.

37 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. here are dishonest and possibly illegal methods used to breach the code protection feature. ll of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. ode protection does not mean that we are guaranteeing the product as unbreakable. ode protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. ttempts to break Microchip s code protection feature may be a violation of the Digital Millennium opyright ct. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that ct. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MIROHIP MES NO REPRESENIONS OR WRRNIES OF NY IND WHEHER EXPRESS OR IMPLIED, WRIEN OR ORL, SUORY OR OHERWISE, RELED O HE INFORMION, INLUDING BU NO LIMIED O IS ONDIION, QULIY, PERFORMNE, MERHNBILIY OR FINESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. rademarks he Microchip name and logo, the Microchip logo, dspi, EELOQ, EELOQ logo, MPLB, PI, PImicro, PISR, PI 32 logo, rfpi and UNI/O are registered trademarks of Microchip echnology Incorporated in the U.S.. and other countries. FilterLab, Hampshire, HI-EH, Linear ctive hermistor, MXDEV, MXLB, SEEVL and he Embedded ontrol Solutions ompany are registered trademarks of Microchip echnology Incorporated in the U.S.. nalog-for-the-digital ge, pplication Maestro, odeguard, dspidem, dspidem.net, dspiworks, dsspe, EN, EONOMONIOR, FanSense, HI-IDE, In-ircuit Serial Programming, ISP, Mindi, MiWi, MPSM, MPLB ertified logo, MPLIB, MPLIN, mouch, Omniscient ode Generation, PI, PI-18, PIDEM, PIDEM.net, PIkit, PItail, REL IE, rflb, Select Mode, otal Endurance, SHR, UniWinDriver, WiperLock and ZEN are trademarks of Microchip echnology Incorporated in the U.S.. and other countries. SQP is a service mark of Microchip echnology Incorporated in the U.S.. ll other trademarks mentioned herein are property of their respective companies. 2011, Microchip echnology Incorporated, Printed in the U.S.., ll Rights Reserved. Printed on recycled paper. ISBN: Microchip received ISO/S-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in handler and empe, rizona; Gresham, Oregon and design centers in alifornia and India. he ompany s quality system processes and procedures are for its PI MUs and dspi DSs, EELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9001:2000 certified Microchip echnology Inc. Preliminary DS22266B-page 37