STEVAL-TSP009V2. PoE 3.3 V - 6 A PD converter based on the PM8803 IEEE802.3at-compliant, synchronous flyback controller. Description.

Transcription

1 PoE. V - A PD converter based on the PM0 IEEE0.at-compliant, synchronous flyback controller Data brief Description The is a reference design for a PoE+, high-efficiency,. V - A flyback converter based on the PM0 PoE controller. The PM0 is a highly integrated device embedding an IEEE0.at-compliant powered device (PD) interface together with a PWM controller and support for auxiliary sources. The reference design is based on an isolated flyback topology CCM converter featuring synchronous rectification with gate driver transformer. Features IEEE 0.at compliant PD interface Works with power supplied from Ethernet LAN cables or from local auxiliary sources Line input voltage range: 0 VDC to 0 VDC Output voltage:. VDC ± % Output current: A Peak-to-peak output ripple: < mv Efficiency DC-DC full-load: > 90% Overall peak efficiency: > % Transient response ΔVOUTPK-PK to 0% load step: < 0 mv ΔV in load line case: < 0.% RoHs compliant April 0 DocID0 Rev / For further information contact your local STMicroelectronics sales office

2 R Schematic diagrams 0 AUX J J DATA & POWER INPUT TP R K TP R 0 D STTH0S SMC C D D R0 R C R C C.nF D D R C D D D9 D 0 9 ETH-0 T 9 0 R R R R C9.nF 0 R TP TP TP C nf 0% R 0 R 0 POE+F C 0.uF 0% D JA J DATA OUTPUT C nf 0% C nf 0% Auxiliary input frontal orauxi POE+F Schematic diagrams Figure : circuit schematic ( of ) GG00DI / DocID0 Rev

3 V AUX TP TP R9 TP9 J 0 C TBD L 0uH D STTH0S MSS-0ML SMC C R K C0 0pF C uf - 0% 0x0. C9 C.u 0 TP.u 0.u 0 R 00R 0 L 0.uH TP R 0 DO-ML J C.nF R R0 R K Inpu t Filter R 0R C C TP C C C C 9 0 Figure : circuit schematic ( of ) 0 D C 0uF V x0. uf 0 V uf 0 V uf 0 V uf 0 V uf 0 V uf 0 V C 0.u TP0 POE+F TP Out de t T Q STLNLLH PowerFLAT x Ou tput Filter COILCRAFT JA - AL R K R TP D 0R BATJ R 0R D BATJ C9 uf V SOD SOD C TP 0nF R0 0K-% % R K R 0K-% % D MMZVT SOD C0 uf V C uf V D COILCRAFT DA9-AL BATJ SOD R C 0.uF Q MMBT90LT SOT A R0 R R9 D BATJ SOD R 0K U U C R T TP Fairchild FODAS 0 R9 0R CTL TP 0.uF 9 FRS VB R9.K CS DT C uf V TP R9 0R R9 0R C9.nF R90 0R GAT DCCL R9 K-% % R R TP R VC CLS SiDY SO 0R9 % R D BATJ C0 00nF GAT C 00pF R9 SOD K A DET R0 R99 K.9K- % % Q 9 D9 BATJ SOD VDD C uf 0R 0 A Ex Pa d D0 VDD C 0p R0.K-% R9 K % R MMBT90LT SOT Q C9 0nF TP R k % C nf PM0 HTSSOP0-LARGE BATJ SOD C 0nF 0% 0V R0.9K-% % C9 uf V C9 0nF R0 R ohm - % 0.0 ohm - % 0 0 A R0 0K C0 nf U TILT SOT- R.K-% % R NM % Powercircuit C.n TP9 TP VC Feedback circuit Schematic diagrams DocID0 Rev / R A D TP det D0 Aux det JM U TP U TP0 Fairchild FODAS R9 R.K K Auxiliary present TP present VC Jumper-doppio Fairchild FODAS R K R.9K JM Jumper-doppio TP NOTE for Resistors Where not indicated the body is and tolerance % NOTE for Capacitors NOTE for Ju mpers JM and JM Move the short on both jumpers at the same time: - short between pin and when used AUX input Where not indicated the body is and the voltage is 0V NOTE The A is a dedicated plane of signal ground that will be connected to the power ground plane close to pin and 9 of PM0 - short between pin and when used AUX input.

4 Detailed description Detailed description The PM0 evaluation board,, has been designed to cover a broad range of Power over Ethernet (PoE) applications. The PM0 is a highly integrated device embedding an IEEE0.af/at-compliant powered device (PD) interface together with a PWM controller and support for auxiliary sources. Although the PM0 can be configured to work in several isolated topologies (self-driven or transformer gate-driven), the focus here is on a high-efficiency isolated flyback converter topology with synchronous rectification,. V output voltage with A output current capability. Auxiliary sources can be connected to the board on different input connectors. One input (AUX II) allows prevalence of the auxiliary sources with respect to the PoE, while the other input (AUX I) allows the use of a wall adapter with voltage lower than the internal PoE UVLO threshold, while still benefitting from the inherent inrush and DC current limit. The possible configurations supported by the PM0 evaluation board as options on the same PCB are: Input diode bridges; possible options, including active bridges Optional -pair detection circuit, to detect a high power PSE source Optional booster circuit, to increase the max input current over 00 ma Diode or synchronous rectification; package options for diode and package options for MOSFET Primary side snubber; options including active clamp Power transformer; size options for transformer gate-driven solutions and size options for self-driven applications / DocID0 Rev

5 Efficiency Efficiency Figure : Efficiency DocID0 Rev /

6 Revision history Revision history Table : Document revision history Date Version Changes -Apr-0 Initial release. / DocID0 Rev

7 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 0 STMicroelectronics All rights reserved DocID0 Rev /