Features. Description. Table 1: Device summary. Order code Marking Package Packing STL24N60DM2 24N60DM2 PowerFLAT 8x8 HV Tape and reel

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1 N-channel 600 V, Ω typ., 15 A MDmesh DM2 Power MOSFET in a PowerFLAT 8x8 HV package Datasheet - production data Features Order code TJmax RDS(on) max. ID 5 STL24N60DM2 650 V Ω 15 A PowerFLAT 8x8 HV Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Figure 1: Internal schematic diagram Applications Switching applications Table 1: Device summary Description This high voltage N-channel Power MOSFET is part of the MDmesh DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Order code Marking Package Packing STL24N60DM2 24N60DM2 PowerFLAT 8x8 HV Tape and reel July 2016 DocID Rev 3 1/15 This is information on a product in full production.

2 Contents STL24N60DM2 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information PowerFLAT8x8 HV package information PowerFLAT8x8 HV packaging information Revision history /15 DocID Rev 3

3 Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ±25 V ID (1) Drain current (continuous) at Tcase = 25 C 15 A Drain current (continuous) at Tcase = 100 C 9.5 IDM (1)(2) Drain current (pulsed) 60 A PTOT (1) Total dissipation at Tcase = 25 C 125 W dv/dt (3) Peak diode recovery voltage slope 40 dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns Tstg Tj Storage temperature range -55 to 150 C Operating junction temperature range Notes: (1) The value is limited by package (2) Pulse width limited by safe operating area. (3) ISD 15 A, di/dt 400 A/μs, VDS(peak) < V(BR)DSS, VDD=400 V (4) VDS 480 V. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 1 Rthj-pcb (1) Thermal resistance junction-pcb 45 C/W Notes: (1) When mounted on FR-4 board of inch², 2oz Cu. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 3 A EAS Single pulse avalanche energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) 160 mj DocID Rev 3 3/15

4 Electrical characteristics STL24N60DM2 2 Electrical characteristics (Tcase = 25 C unless otherwise specified) Table 5: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS IDSS IGSS Drain-source breakdown voltage Zero gate voltage drain current Gate-body leakage current VGS = 0 V, ID = 1 ma 600 V VGS = 0 V, VDS = 600 V 1.5 VGS = 0 V, VDS = 600 V, Tcase = 125 C 100 VDS = 0 V, VGS = ±25 V ±10 µa VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µa V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 9 A Ω µa Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance Coss Output capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Crss Reverse transfer capacitance Coss eq. (1) RG Equivalent output capacitance Intrinsic gate resistance VDS = 0 to 480 V, VGS = 0 V pf f = 1 MHz, ID= 0 A Ω Qg Total gate charge VDD = 480 V, ID = 18 A, VGS = 10 V Qgs Gate-source charge (see Figure 15: "Gate charge test Qgd Gate-drain charge circuit") Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. pf nc Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 300 V, ID = 9 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: tr Rise time "Switching times test circuit for td(off) Turn-off delay time resistive load" and Figure 19: ns tf Fall time "Switching time waveform") /15 DocID Rev 3

5 Table 8: Source-drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit ISD (1) Source-drain current - 15 A ISDM (2) Source-drain current (pulsed) - 60 A VSD (3) Forward on voltage VGS = 0 V, ISD = 18 A V trr Qrr IRRM trr Qrr IRRM Notes: Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current (1) The value is limited by package. (2) Pulse width limited by safe operating area (3) Pulsed: pulse duration = 300 μs, duty cycle 1.5% ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") ns nc A ns nc - 13 A DocID Rev 3 5/15

6 Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance STL24N60DM2 K δ= Single pulse 0.01 Z th = K*R thj-c δ= t p /Ƭ 10-2 t p Ƭ tp(s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance R Ω VGS=10 V ID(A) 6/15 DocID Rev 3

7 Figure 8: Capacitance variations Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature RDS(on) (norm) ID=9 A VGS=10 V TJ( C) Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy AM15669v1 Eoss(µJ) 8 Figure 13: Source- drain diode forward characteristics VDS(V) DocID Rev 3 7/15

8 Test circuits STL24N60DM2 3 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VGS VD RG RL + D.U.T µf 3.3 µf VDD PW GND1 (driver signal) GND2 (power) Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit G A D D.U.T. A FAST DIODE A L=100µH L 25Ω S B RG B G B D S D.U.T µf + µf VDD VD ID µf 3.3 µf VDD Vi D.U.T. GND1 GND2 Pw GND1 GND2 AM15858v1 Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/15 DocID Rev 3

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DocID Rev 3 9/15

10 Package information 4.1 PowerFLAT8x8 HV package information Figure 20: PowerFLAT 8x8 HV package outline STL24N60DM _Rev_3_ A 10/15 DocID Rev 3

11 Package information Table 9: PowerFLAT 8x8 HV mechanical data mm Dim. Min. Typ. Max. A A A b D E D E E e 2.00 L Figure 21: PowerFLAT 8x8 HV footprint All dimensions are in millimeters. DocID Rev 3 11/15

12 Package information 4.2 PowerFLAT8x8 HV packaging information Figure 22: PowerFLAT 8x8 HV tape STL24N60DM2 All dimensions are in millimeters. Figure 23: PowerFLAT 8x8 HV package orientation in carrier tape 12/15 DocID Rev 3

13 Figure 24: PowerFLAT 8x8 HV reel Package information All dimensions are in millimeters. DocID Rev 3 13/15

14 Revision history STL24N60DM2 5 Revision history Table 10: Document revision history Date Revision Changes 03-Mar First release. 21-Jan Modified: title, features, description and internal schematic in cover page Modified: Section 3: "Test circuits" Updated: Section 4: "Package information" Minor text changes 25-Jul Document status promoted from preliminary to production data. 14/15 DocID Rev 3

15 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DocID Rev 3 15/15

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