QUAD CHANNEL HIGH SIDE SOLID STATE RELAY

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1 P QUAD CHANNE HIGH SIDE SOID STATE REAY TYPE R DS(on) (*) I lim V CC 35mΩ 25A 36 V (*) Per each channel DC SHORT CIRCUIT CURRENT: 25A CMOS COMPATIBE INPUTS PROPORTIONA OAD CURRENT SENSE UNDERVOTAGE & OVERVOTAGE nshut-down OVERVOTAGE CAMP THERMA SHUT-DOWN CURRENT IMITATION VERY OW STAND-BY POWER DISSIPATION PROTECTION AGAINST: noss OF GROUND & OSS OF V CC REVERSE BATTERY PROTECTION (**) DESCRIPTION The is a quad HSD formed by assembling two VND6 chips in the same SO-28 ABSOUTE MAXIMUM RATING SO-28 (DOUBE ISAND) ORDER CODES PACKAGE TUBE T&R SO-28 3TR package. The VND6 is a monolithic device designed in STMicroelectronics VIPower M-3 Technology. The is intended for driving any type of multiple loads with one side connected to ground. This device has four independent channels and four analog sense outputs which deliver currents proportional to the outputs currents. Active current limitation combined with thermal shut-down and automatic restart protect the device against overload. Device automatically turns off in case of ground pin disconnection. Symbol Parameter Value Unit V CC Supply voltage (continuous) 4 V -V CC Reverse supply voltage (continuous) -.3 V I OUT Output current (continuous), for each channel 5 A I R Reverse output current (continuous), for each channel -5 A I IN Input current +/- ma V CSENSE Current sense maximum voltage -3 V +5 V I GND Ground current at T pins < 25 C (continuous) -2 ma V ESD Electrostatic Discharge (Human Body Model: R=.5KΩ; C=pF) - INPUT - CURRENT SENSE - OUTPUT - V CC V V V V E MAX Maximum Switching Energy (=.mh; R =Ω; V bat =3.5V; T jstart =5ºC; I =4A) 26 mj P tot Power dissipation (per island) at T lead =25 C 6.25 W T j Junction operating temperature Internally imited C T stg Storage temperature -55 to 5 C (**) See application schematic at page 9. Rev. July 24 /9

2 BOCK DIAGRAM V CC,2 OVERVOTAGE UNDERVOTAGE INPUT DRIVER DEMAG I IM OUTPUT INPUT 2 GND,2 OGIC DRIVER 2 I OUT K DEMAG 2 CURRENT SENSE OUTPUT 2 OVERTEMP. I IM2 OVERTEMP. 2 I OUT2 K CURRENT SENSE 2 OVERVOTAGE UNDERVOTAGE V CC 3,4 INPUT 3 DRIVER 3 DEMAG 3 I IM3 OUTPUT 3 INPUT 4 GND 3,4 OGIC DRIVER 4 I OUT3 K DEMAG 4 CURRENT SENSE 3 OUTPUT 4 OVERTEMP. 3 I IM4 OVERTEMP. 4 I OUT4 K CURRENT SENSE 4 2/9

3 CURRENT AND VOTAGE CONVENTIONS I S3,4 I S,2 VCC3,4 V CC3,4 V CC,2 VF (*) V CC,2 I IN V IN I SENSE V SENSE I IN2 V IN2 I SENSE2 V SENSE2 I IN3 V IN3 I SENSE3 V SENSE3 I IN4 V IN4 I SENSE4 V STAT4 INPUT CUR. SENSE INPUT2 CUR. SENSE2 INPUT3 CUR. SENSE3 INPUT4 CUR. SENSE4 GND 3,4 OUTPUT OUTPUT2 OUTPUT3 OUTPUT4 GND,2 I OUT V OUT I OUT2 V OUT2 I OUT3 V I OUT3 OUT4 V OUT4 I GND3,4 I GND,2 (*) V Fn = V CCn - V OUTn during reverse battery condition CONFIGURATION DIAGRAM (TOP VIEW) & SUGGESTED CONNECTIONS FOR UNUSED AND N.C. PINS V CC,2 28 V CC,2 GND,2 OUTPUT 2 INPUT2 OUTPUT 2 INPUT OUTPUT 2 CURRENT SENSE OUTPUT CURRENT SENSE 2 V CC,2 OUTPUT OUTPUT V CC 3,4 OUTPUT 4 GND 3,4 OUTPUT 4 INPUT4 OUTPUT 4 INPUT3 CURRENT SENSE 3 CURRENT SENSE 4 V CC 3,4 4 5 OUTPUT 3 OUTPUT 3 OUTPUT 3 V CC 3,4 Connection / Pin Current Sense N.C. Output Input Floating X X X To Ground Through KΩ resistor X Through KΩ resistor 3/9

4 THERMA DATA (Per island) Symbol Parameter Value Unit R thj-lead Thermal resistance Junction-lead 2 C/W R thj-amb Thermal resistance Junction-ambient (one chip ON) 6 () 45 (2) C/W R thj-amb Thermal Resistance Junction-ambient (two chips ON) 46 () 3 (2) C/W () When mounted on a standard single-sided FR-4 board with.5cm 2 of Cu (at least 35µm thick) connected to all V CC pins. Horizontal mounting and no artificial air flow. (2) When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all V CC pins. Horizontal mounting and no artificial air flow. EECTRICA CHARACTERISTICS (8V<V CC <36V; -4 C<T j <5 C; unless otherwise specified) (Per each channel) POWER Symbol Parameter Test Conditions Min Typ Max Unit V CC (**) Operating supply voltage V V USD (**) Undervoltage shut-down V V OV (**) Overvoltage shut-down 36 V R ON On state resistance I OUT,2,3,4=5A; T j =25 C I OUT,2,3,4=5A; T j =5 C I OUT,2,3,4=3A; V CC =6V mω mω mω V clamp Clamp Voltage I CC =2mA (see note ) V I S (**) Supply current Off State; V CC =3V; V IN =V OUT =V Off State; V CC =3V; V IN =V OUT =V; T j =25 C On State; V CC =3V; V IN =5V; I OUT =A; R SENSE =3.9KΩ µa µa ma I (off) Off state output current V IN =V OUT =V 5 µa I (off2) Off State Output Current V IN =V; V OUT =3.5V -75 µa I (off3) Off State Output Current V IN =V OUT =V; V CC =3V; T j =25 C 5 µa I (off4) Off State Output Current V IN =V OUT =V; V CC =3V; T j =25 C 3 µa SWITCHING (V CC =3V) Symbol Parameter Test Conditions Min Typ Max Unit t d(on) Turn-on delay time R =2.6Ω channels,2,3,4 (see fig. ) 4 µs t d(off) Turn-off delay time R =2.6Ω channels,2,3,4 (see fig. ) 4 µs (dv OUT /dt) on Turn-on voltage slope R =2.6Ω channels,2,3,4 (see fig. ) See relative V/µs diagram (dv OUT /dt) off Turn-off voltage slope R =2.6Ω channels,2,3,4 (see fig. ) See relative diagram V/µs (**) Per island VCC - OUTPUT DIODE Symbol Parameter Test Conditions Min Typ Max Unit V F Forward on Voltage -I OUT =2.3A; T j =5 C.6 V 4/9

5 EECTRICA CHARACTERISTICS (continued) CURRENT SENSE (9V< V CC < 6V) (See Figure 3) Symbol Parameter Test Conditions Min Typ Max Unit K I OUT /I SENSE V SENSE =.5V; other channels I OUT or I OUT2 =.5A; open; T j = -4 C...5 C dk /K Current Sense Ratio Drift I OUT or I OUT2 =.35A; V SENSE =.5V; other channels open; T j = -4 C...5 C - + % K 2 I OUT /I SENSE other channels open; T j =-4 C I OUT or I OUT2 =5A; V SENSE =4V; T j =25 C...5 C dk 2 /K 2 OGIC INPUT Current Sense Ratio Drift Note : V clamp and V OV are correlated. Typical difference is 5V. Note 2: current sense signal delay after positive input slope. I OUT or I OUT2 =2A; V SENSE =2.5V; other channels open; T j =-4 C...5 C K 3 I OUT /I SENSE other channels open; T j =-4 C I OUT or I OUT2 =5A; V SENSE =4V; T j =25 C...5 C dk 3 /K 3 V SENSE,2 V SENSEH R VSENSEH Current Sense Ratio Drift Max analog sense output voltage Analog sense output voltage in overtemperature condition Analog Sense Output Impedance in Overtemperature Condition I OUT or I OUT2 =5A; V SENSE =4V; other channels open; T j =-4 C...5 C V CC =5.5V; I OUT,2 =2.5A; R SENSE =kω V CC >8V, I OUT,2 =5A; R SENSE =kω V CC =3V; R SENSE =3.9kΩ V CC =3V; T j >T TSD ; All channels open % % 2 4 V V 5.5 V 4 Ω t DSENSE Current sense delay response to 9% I SENSE (see note 2) 5 µs Symbol Parameter Test Conditions Min Typ Max Unit V I ow level input voltage.25 V V IH High level input voltage 3.25 V V I(hyst) Input hysteresis voltage.5 V I I Input current V IN =.5V µa I IN Input current V IN =3.5V µa V IC Input clamp voltage I IN =ma V I IN = -ma -.7 V 5/9 2

6 EECTRICA CHARACTERISTICS (continued) PROTECTIONS (see note ) Symbol Parameter Test Conditions Min Typ Max Unit I lim DC Short circuit current V CC =3V A 5.5V<V CC <36V 7 A T TSD Thermal shut-down temperature C T R Thermal reset temperature 35 C T hyst Thermal hysteresis 7 5 C V demag Turn-off output voltage clamp I OUT =2A; =6mH V CC -4 V CC -48 V CC -55 V V ON Output voltage drop limitation I OUT =.5A; T j = -4 C...+5 C 5 mv Note : To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. TRUTH TABE (per channel) CONDITIONS INPUT OUTPUT SENSE Normal operation Overtemperature Undervoltage Overvoltage Short circuit to GND Short circuit to V CC Negative output voltage clamp H H H H H H H H H H Nominal V SENSEH (T j <T TSD ) (T j >T TSD ) V SENSEH < Nominal 6/9

7 EECTRICA TRANSIENT REQUIREMENTS ISO T/R Test evels Test evels Test evels Test evels Test evels 7637/ I II III IV Delays and Impedance Test Pulse -25V -5V -75V -V 2ms, Ω 2 +25V +5V +75V +V.2ms, Ω 3a -25V -5V -V -5V.µs, 5Ω 3b +25V +5V +75V +V.µs, 5Ω 4-4V -5V -6V -7V ms,.ω V +46.5V +66.5V +86.5V 4ms, 2Ω ISO T/R Test evels Result Test evels Result Test evels Result Test evels Result 7637/ I II III IV Test Pulse C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. Figure : Switching Characteristics (Resistive load R =2.6Ω) V OUT 8% 9% dv OUT /dt (on) t r % t f dv OUT /dt (off) t I SENSE 9% INPUT t d(on) t DSENSE t d(off) t t 7/9

8 Figure 2: Waveforms (per each chip) NORMA OPERATION INPUT n OAD CURRENT n SENSE n UNDERVOTAGE V CC V USDhyst INPUT n V USD OAD CURRENT n SENSE n OVERVOTAGE V CC INPUT n OAD CURRENT n SENSE n V OV V CC < V OV V CC > V OV INPUT n OAD CURRENT n OAD VOTAGE n SENSE n SHORT TO GROUND INPUT n OAD VOTAGE n OAD CURRENT n SHORT TO V CC SENSE n <Nominal <Nominal T j T TSD T R OVERTEMPERATURE INPUT n OAD CURRENT n SENSE n V SENSEH I SENSE = RSENSE 8/9

9 APPICATION SCHEMATIC +5V R prot INPUT V CC,2 V CC3,4 D ld R prot C. SENSE OUTPUT R prot INPUT2 µc R prot C. SENSE 2 OUTPUT2 R prot R prot R prot R prot INPUT3 C. SENSE 3 INPUT4 C. SENSE 4 GND,2 OUTPUT3 OUTPUT4 GND3,4 R SENSE,2,3,4 V GND R GND D GND Note: Channels 3 & 4 have the same internal circuit as channel & 2. GND PROTECTION NETWORK AGAINST REVERSE BATTERY Solution : Resistor in the ground line (R GND only). This can be used with any type of load. The following is an indication on how to dimension the R GND resistor. ) R GND 6mV / 2(I S(on)max ). 2) R GND ( V CC ) / (-I GND ) where -I GND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device s datasheet. Power Dissipation in R GND (when V CC <: during reverse battery situations) is: P D = (-V CC ) 2 /R GND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula () where I S(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the R GND will produce a shift (I S(on)max * R GND ) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R GND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (D GND ) in the ground line. A resistor (R GND =kω) should be inserted in parallel to D GND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j6mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 9/9

10 OAD DUMP PROTECTION D ld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds V CC max DC rating. The same applies if the device will be subject to transients on the V CC line that are greater than the ones shown in the ISO T/R 7637/ table. µc I/Os PROTECTION: If a ground protection network is used and negative transients are present on the V CC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot ) in line to prevent the µc I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µc and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µc I/Os. -V CCpeak /I latchup R prot (V OHµC -V IH -V GND ) / I IHmax Calculation example: For V CCpeak = - V and I latchup 2mA; V OHµC 4.5V 5kΩ R prot 65kΩ. Recommended R prot value is kω. Figure 3: I OUT /I SENSE versus I OUT I OUT /I SENSE max.tj= C min.tj= C max.tj=-4 C typical value min.tj=-4 C I OUT (A) /9

11 Off State Output Current High evel Input Current I(off) (ua) 5 Iih (ua) Off state Vcc=36V Vin=Vout=V Vin=3.25V Tc ( C) Input Clamp Voltage Tc ( C) Input High evel Vicl (V) 8 Vih (V) Iin=mA Tc ( C) Input ow evel Tc ( C) Input Hysteresis Voltage Vil (V) Tc ( C) Vhyst (V) Tc ( C) /9

12 Overvoltage Shutdown I IM Vs T case Vov (V) 5 Ilim (A) Vcc=3V Tc ( C) Turn-on Voltage Slope Tc ( C) Turn-off Voltage Slope dvout/dt(on) (V/ms) 75 dvout/dt(off) (V/ms) Vcc=3V Rl=2.6Ohm 4 35 Vcc=3V Rl=2.6Ohm Tc (ºC) Tc (ºC) On State Resistance Vs T case On State Resistance Vs V CC Ron (mohm) Ron (mohm) Iout=5A Vcc=8V & 36V 7 6 Iout=5A Tc= 5 C Tc= 25 C Tc= - 4 C Tc ( C) Vcc (V) 2/9

13 Maximum turn off current versus load inductance IMAX (A) A B C... (mh) A = Single Pulse at T Jstart =5ºC B= Repetitive pulse at T Jstart =ºC C= Repetitive Pulse at T Jstart =25ºC Conditions: V CC =3.5V Values are generated with R =Ω In case of repetitive pulses, T jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. V IN, I Demagnetization Demagnetization Demagnetization t 3/9

SO-28 DOUBE ISAND THERMA DATA SO-28 Double island PC Board ayout condition of R th and Z th measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu

Thermal calculation according to the PCB heatsink area Chip Chip 2 T jchip T jchip2 Note ON OFF R tha x P dchip + T amb R thc x P dchip + T amb OFF ON R thc x P

dchip ) + R thc x P dchip2 + T amb (R tha x P dchip2 ) + R thc x P dchip + T amb P dchip P dchip2 R tha = Thermal resistance Junction to Ambient with one chip ON

14 SO-28 DOUBE ISAND THERMA DATA SO-28 Double island PC Board ayout condition of R th and Z th measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas:.5cm 2, 3cm 2, 6cm 2 ). Thermal calculation according to the PCB heatsink area Chip Chip 2 T jchip T jchip2 Note ON OFF R tha x P dchip + T amb R thc x P dchip + T amb OFF ON R thc x P dchip2 + T amb R tha x P dchip2 + T amb ON ON R thb x (P dchip + P dchip2 ) + T amb R thb x (P dchip + P dchip2 ) + T amb P dchip =P dchip2 ON ON (R tha x P dchip ) + R thc x P dchip2 + T amb (R tha x P dchip2 ) + R thc x P dchip + T amb P dchip P dchip2 R tha = Thermal resistance Junction to Ambient with one chip ON R thb = Thermal resistance Junction to Ambient with both chips ON and P dchip =P dchip2 R thc = Mutual thermal resistance R thj-amb Vs. PCB copper area in open box free air condition RTHj_am b ( C/W) R tha R thb R thc PCB Cu heatsink area (cm ^2)/island 4/9

15 SO-28 Thermal Impedance Junction Ambient Single Pulse Zth( C/W),5 cm ^2/island 3 cm ^2/island 6 cm ^2/island One channel ON Two channels ON on same chip time(s) Thermal fitting model of a four channels HSD in SO-28 Pulse calculation formula Z THδ = R TH δ + Z THtp ( δ) Tj_ C C2 C3 C4 C5 C6 where δ = t p T Thermal Parameter Pd Tj_2 Pd2 Tj_3 Pd3 Tj_4 Pd4 R C3 R3 C7 R7 C5 R5 R2 C4 R4 C8 R8 C6 R6 R3 R7 C9 R9 R4 R8 C R R5 C R R6 C2 R2 Area/island (cm 2 ).5 6 R=R7=R3=R5 ( C/W).5 R2=R8=R4=R6 ( C/W).3 R3=R9 ( C/W) 3.4 R4=R ( C/W) R5=R ( C/W) 5 R6=R2 ( C/W) 3 3 C=C7=C3=C5 (W.s/ C). C2=C8=C4=C6 (W.s/ C) 5.E-3 C3=C9 (W.s/ C).E-2 C4=C (W.s/ C).2 C5=C (W.s/ C).5 T_amb C6=C2 (W.s/ C) 5 8 R7=R8 ( C/W) 5 5/9

16 SO-28 MECHANICA DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A a b b C.5.2 c 45 (typ.) D E e.27.5 e F S 8 (max.) 6/9 2

17 SO-28 TUBE SHIPMENT (no suffix) C B Base Q.ty 28 Bulk Q.ty 7 Tube length (±.5) 532 A 3.5 B 3.8 C (±.).6 A All dimensions are in mm. TAPE AND REE SHIPMENT (suffix 3TR ) REE DIMENSIONS Base Q.ty Bulk Q.ty A (max) 33 B (min).5 C (±.2) 3 F 2.2 G (+ 2 / -) 6.4 N (min) 6 T (max) 22.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 48 rev. A, Feb. 986 Tape width W 6 Tape Hole Spacing P (±.) 4 Component Spacing P 2 Hole Diameter D (±./-).5 Hole Diameter D (min).5 Hole Position F (±.5) 7.5 Compartment Depth K (max) 6.5 Hole Spacing P (±.) 2 All dimensions are in mm. End Start Top cover tape No components 5mm min Components Empty components pockets saled with cover tape. No components 5mm min User direction of feed 7/9

18 REVISION HISTORY Date Revision Description of Changes Jul Current and voltage convention update (page 3). - Configuration diagram (top view) & suggested connections for unused and n.c. pins insertion (page 3). - 6 cm 2 Cu condition insertion in Thermal Data table (page 4). - V CC - OUTPUT DIODE section update (page 4). - PROTECTIONS note insertion (page 6). - Revision History table insertion (page 8). - Disclaimers update (page 9). 8/9

19 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. All other names are the property of their respective owners 24 STMicroelectronics - Printed in ITAY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States 9/9

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VN800S-E VN800PT-E HIGH SIDE DRIVER. Table 1. General Features. Figure 1. Package

VN800S-E VN800PT-E HIGH SIDE DRIVER. Table 1. General Features. Figure 1. Package VN800S-E VN800PT-E IG SIDE DRIVER Table 1. General Features Figure 1. Package Type R DS(on) I OUT V CC VN800S-E VN800PT-E 135 mω 0.7 A 36 V CMOS COMPATIBE INPUT TERMA SUTDOWN CURRENT IMITATION SORTED OAD