VN5E050MJ-E. Single-channel high-side driver with analog current sense for automotive applications. Features. Application.

Transcription

1 VN5E5MJ-E Single-channel high-side driver with analog current sense for automotive applications Features Max supply voltage V CC 41 V Operating voltage range V CC 4.5 V to 28V Max on-state resistance R ON 5 mω Current limitation (typ) I LIMH 27 A Off-state supply current I S 2 µa (1) 1. Typical value with all loads connected. General Inrush current active management by power limitation Very low standby current 3. V CMOS compatible inputs Optimized electromagnetic emissions Very low electromagnetic susceptibility In compliance with the 22/95/EC european directive Very low current sense leakage Diagnostic functions Proportional load current sense High current sense precision for wide currents range Current sense disable Overload and short to ground (power limitation) indication Thermal shutdown indication Protections Undervoltage shutdown Overvoltage clamp Load current limitation Self limiting of fast thermal transients Protection against loss of ground and loss of V CC Overtemperature shutdown with auto restart (thermal shutdown) Reverse battery protected (see Figure 29) Electrostatic discharge protection Application All types of resistive, inductive and capacitive loads Suitable as LED driver Description PowerSSO-12 The VN5E5MJ-E is a single channel high-side driver manufactured in the ST proprietary VIPower M-5 technology and housed in the tiny PowerSSO-12 package. The VN5E5MJ-E is designed to drive 12 V automotive grounded loads delivering protection, diagnostics and easy 3 V and 5 V CMOS compatible interface with any microcontroller. The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp. A dedicated analog current sense pin is associated with every output channel in order to provide Enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation and overtemperature indication. The current sensing and diagnostic feedback of the whole device can be disabled by pulling the CS_DIS pin high to allow sharing of the external sense resistor with other similar devices. November 29 Doc ID Rev 1 1/35 1

2 Contents VN5E5MJ-E Contents 1 Block diagram and pin description Electrical specifications Absolute maximum ratings Thermal data Electrical characteristics Waveforms Electrical characteristics curves Application information GND protection network against reverse battery Solution 1: resistor in the ground line (RGND only) Solution 2: diode (D GND ) in the ground line Load dump protection MCU I/O protection Current sense and diagnostic Maximum demagnetization energy (VCC = 13.5V) Package and PCB thermal data PowerSSO-12 thermal data Package information ECOPACK Package mechanical data Packing information Order codes Revision history /35 Doc ID Rev 1

3 VN5E5MJ-E List of tables List of tables Table 1. Pin function Table 2. Suggested connections for unused and not connected pins Table 3. Absolute maximum ratings Table 4. Thermal data Table 5. Power section Table 6. Switching (V CC = 13V; T j = 25 C) Table 7. Logic inputs Table 8. Protections and diagnostics Table 9. Current sense (8V<VCC<18V) Table 1. Truth table Table 11. Electrical transient requirements (part 1) Table 12. Electrical transient requirements (part 2) Table 13. Electrical transient requirements (part 3) Table 14. Thermal parameter Table 15. PowerSSO-12 mechanical data Table 16. Device summary Table 17. Document revision history Doc ID Rev 1 3/35

4 List of figures VN5E5MJ-E List of figures Figure 1. Block diagram Figure 2. Configuration diagram (top view) Figure 3. Current and voltage conventions Figure 4. Current sense delay characteristics Figure 5. Switching characteristics Figure 6. Output voltage drop limitation Figure 7. Delay response time between rising edge of output current and rising edge of current sense (CS enabled) Figure 8. I OUT /I SENSE vs. I OUT Figure 9. Maximum current sense ratio drift vs. load current Figure 1. Normal operation Figure 11. Overload or Short to GND Figure 12. Intermittent Overload Figure 13. T J evolution in Overload or Short to GND Figure 14. Off-state output current Figure 15. High level input current Figure 16. Input clamp level Figure 17. Input low level Figure 18. Input high level Figure 19. Input hysteresis voltage Figure 2. On-state resistance vs. Tcase Figure 21. On-state resistance vs. VCC Figure 22. Undervoltage shutdown Figure 23. Turn-on voltage slope Figure 24. ILIMH Vs. Tcase Figure 25. Turn-off voltage slope Figure 26. CS_DIS high level voltage Figure 27. CS_DIS clamp voltage Figure 28. CS_DIS low level voltage Figure 29. Application schematic Figure 3. Current sense and diagnostic Figure 31. Maximum turn-off current versus inductance Figure 32. PowerSSO-12 PC board Figure 33. Rthj-amb Vs. PCB copper area in open box free air condition Figure 34. PowerSSO-12 thermal impedance junction ambient single pulse Figure 35. Thermal fitting model of a single channel HSD in PowerSSO Figure 36. PowerSSO-12 package dimensions Figure 37. PowerSSO-12 tube shipment (no suffix) Figure 38. PowerSSO-12 tape and reel shipment (suffix TR ) /35 Doc ID Rev 1

5 VN5E5MJ-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram V CC Signal Clamp Undervoltage Control & Diagnostic Power Clamp IN DRIVER V ON Limitation Over temp. Current Limitation CS_ DIS V SENSEH CS Current Sense LOGIC OVERLOAD PROTECTION (ACTIVE POWER LIMITATION) OUT GND Table 1. Name Pin function Function V CC OUT GND IN CS CS_DIS Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Analog current sense pin, delivers a current proportional to the load current. Active high CMOS compatible pin, to disable the current sense pin. Doc ID Rev 1 5/35

6 Block diagram and pin description VN5E5MJ-E Figure 2. Configuration diagram (top view) TAB = Vcc N.C N.C. GND 2 11 OUT IN 3 1 OUT CS 4 9 OUT CS_DIS 5 8 OUT N.C. 6 7 N.C. Table 2. Connection / pin Suggested connections for unused and not connected pins Current sense N.C. Output Input CS_DIS Floating Not allowed X X X X To ground Through 1 KΩ resistor X Through 22 KΩ resistor Through 1 KΩ resistor Through 1 KΩ resistor 6/35 Doc ID Rev 1

7 VN5E5MJ-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions I S V CC V F VCC V CSD I CSD CS_DIS OUT I OUT V OUT I IN V IN IN GND CS I SENSE VSENSE I GND Note: V F = V OUT - V CC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings Symbol Parameter Value Unit V CC DC supply voltage 41 V -V CC Reverse DC supply voltage.3 V - I GND DC reverse ground pin current 2 ma I OUT DC output current Internally limited A - I OUT Reverse DC output current 2 A I IN DC input current -1 to 1 ma I CSD DC current sense disable input current -1 to 1 ma -I CSENSE DC reverse CS pin current 2 ma V CSENSE E MAX Current sense maximum voltage Maximum switching energy (single pulse) (L= 3mH; R L =Ω; V bat =13.5V; T jstart =15ºC; I OUT = I liml (Typ.)) V CC - 41 to +V CC V 14 mj Doc ID Rev 1 7/35

8 Electrical specifications VN5E5MJ-E Table 3. Symbol Parameter Value Unit V ESD Absolute maximum ratings (continued) Electrostatic discharge (Human Body Model: R=1.5KΩ; C=1pF) INPUT CURRENT SENSE CS_DIS OUTPUT V CC V ESD Charge device model (CDM-AEC-Q1-11) 75 V T j Junction operating temperature -4 to 15 C T stg Storage temperature -55 to 15 C V V V V V 2.2 Thermal data Table 4. Thermal data Symbol Parameter Max. value Unit R thj-case Thermal resistance junction-case (with one channel ON) 2.7 C/W R thj-amb Thermal resistance junction-ambient See Figure 33 C/W 8/35 Doc ID Rev 1

9 VN5E5MJ-E Electrical specifications 2.3 Electrical characteristics Values specified in this section are for 8V <V CC < 28V; -4 C< T j <15 C, unless otherwise stated. Table 5. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit V CC Operating supply voltage V V USD Undervoltage shutdown V V USDhyst Undervoltage shutdown hysteresis.5 V R ON On-state resistance I OUT = 2A; T j = 25 C I OUT = 2A; T j = 15 C I OUT = 2A; V CC = 5V; T j = 25 C mω mω mω V clamp Clamp voltage I S = 2 ma V I S Supply current Off-state; V CC =13V; T j =25 C; V IN =V OUT =V SENSE =V CSD =V On-state; V CC =13V; V IN =5V; I OUT =A 2 (1) (1) 3 µa ma I L(off1) Off-state output current V IN =V OUT =V; V CC =13V; T j =25 C V IN =V OUT =V; V CC =13V; T j =125 C µa V F Output - V CC diode voltage -I OUT = 2A; T j = 15 C.7 V 1. PowerMOS leakage included. Table 6. Switching (V CC = 13V; T j = 25 C) Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time R L = 6.5Ω (see Figure 5.) µs t d(off) Turn-off delay time R L = 6.5Ω (see Figure 5.) µs (dv OUT /dt) on Turn-on voltage slope R L = 6.5Ω - See Figure 23 - V/µs (dv OUT /dt) off Turn-off voltage slope R L = 6.5Ω - See Figure 25 - V/µs W ON W OFF Switching energy losses during t on R L = 6.5Ω (see Figure 5.) mj Switching energy losses during t off R L = 6.5Ω (see Figure 5.) mj Doc ID Rev 1 9/35

10 Electrical specifications VN5E5MJ-E Table 7. Logic inputs Symbol Parameter Test conditions Min. Typ. Max. Unit V IL Input low level voltage.9 V I IL Low level input current V IN =.9V 1 µa V IH Input high level voltage 2.1 V I IH High level input current V IN =2.1V 1 µa V I(hyst) Input hysteresis voltage.25 V V ICL Input clamp voltage I IN =1mA I IN =-1mA V V V CSDL CS_DIS low level voltage.9 V I CSDL Low level CS_DIS current V CSD =.9V 1 µa V CSDH CS_DIS high level voltage 2.1 V I CSDH High level CS_DIS current V CSD =2.1V 1 µa V CSD(hyst) CS_DIS hysteresis voltage.25 V V CSCL CS_DIS clamp voltage I CSD =1mA I CSD =-1mA V V Table 8. Protections and diagnostics (1) Symbol Parameter Test conditions Min. Typ. Max. Unit I limh DC short circuit current V CC = 13V 5V < V CC < 28V Short circuit current I liml V during thermal cycling CC = 13V; T R <T j <T TSD 7 A T TSD Shutdown temperature C T R Reset temperature T RS + 1 T RS + 5 C T RS Thermal reset of status 135 C Thermal hysteresis T HYST 7 C (T TSD -T R ) V DEMAG V ON Turn-off output voltage clamp Output voltage drop limitation I OUT = 2A; V IN =; L= 6mH V CC -41 V CC -46 V CC -52 V I OUT =.1A; T j =-4 C to 15 C (see Figure 6) 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. A A 25 mv 1/35 Doc ID Rev 1

11 VN5E5MJ-E Electrical specifications Table 9. Current sense (8V<V CC <18V) Symbol Parameter Test conditions Min. Typ. Max. Unit K I OUT /I SENSE I OUT =.5A; V SENSE =.5V;V CSD =V; T j = -4 C to 15 C K 1 I OUT /I SENSE T j = -4 C to 15 C I OUT = 1A; V SENSE =4 V; V CSD =V T j =25 C to 15 C dk 1 /K 1 (1) Current sense ratio drift I OUT = 1A; V SENSE = 4 V; V CSD =V; T J = -4 C to 15 C -1 1 % K 2 I OUT /I SENSE T j = -4 C to 15 C I OUT = 2A; V SENSE = 4V; V CSD =V; T j =25 C to 15 C dk 2 /K 2 (1) Current sense ratio drift I OUT = 2A; V SENSE = 4V; V CSD =V; T J =-4 C to 15 C -7 7 % K 3 I OUT /I SENSE T j = -4 C to 15 C I OUT = 4A; V SENSE =4V; V CSD =V; T j = 25 C to 15 C dk 3 /K 3 (1) Current sense ratio drift I OUT = 4A; V SENSE = 4 V; V CSD =V; T J = -4 C to 15 C -4 4 % I SENSE Analog sense leakage current I OUT =A; V SENSE =V; V CSD =5V; V IN =V; T j =-4 C to 15 C V CSD =V; V IN =5V; T j =-4 C to 15 C 1 2 µa µa I OUT =2A; V SENSE =V; V CSD =5V; V IN =5V; T j =-4 C to 15 C 1 µa I OL Open load onstate current detection threshold V IN = 5V, 8V<V CC <18V I SENSE = 5 µa 4 2 ma V SENSE Max analog sense output voltage I OUT = 4A; V CSD = V 5 V V SENSEH I SENSEH Analog sense output voltage in V CC = 13V; R SENSE = 3.9 KΩ 8 V fault condition (2) Analog sense output current in V CC = 13V; V SENSE = 5V 9 ma fault condition (2) t DSENSE1H Delay response time from falling edge of CS_DIS pin V SENSE <4V,.5A<Iout<4A I SENSE = 9% of I SENSE max (see Figure 4.) 5 1 µs t DSENSE1L Delay response time from rising edge of CS_DIS pin V SENSE < 4V,.5A<Iout<4A I SENSE = 1% of I SENSE max (see Figure 4.) 5 2 µs Doc ID Rev 1 11/35

12 Electrical specifications VN5E5MJ-E Table 9. Current sense (8V<V CC <18V) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit t DSENSE2H Delay response time from rising edge of INPUT pin V SENSE < 4V,.5A<Iout<4A I SENSE = 9% of I SENSE max (see Figure 4.) 8 25 µs Δt DSENSE2H Delay response time between rising edge of output current and rising edge of current sense V SENSE <4V, I SENSE = 9% of I SENSEMAX, I OUT = 9% of I OUTMAX I OUTMAX = 2A (see Figure 7) 4 µs t DSENSE2L Delay response time from falling edge of INPUT pin V SENSE < 4V,.5A<Iout<4A I SENSE = 1% of I SENSE max (see Figure 4.) 1 25 µs 1. Parameter guaranteed by design; it is not tested. 2. Fault condition includes: power limitation and overtemperature. 12/35 Doc ID Rev 1

13 VN5E5MJ-E Electrical specifications Figure 4. Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT t DSENSE2H t DSENSE1L t DSENSE1H tdsense2l Figure 5. Switching characteristics V OUT t Won 8% t Woff 9% d VOUT /d t(on) d VOUT /d t(off) t r 1% t f t INPUT t d(on) t d(off) t Figure 6. Output voltage drop limitation Vcc-Vout Tj=15oC Tj=25oC Tj=-4oC Von Von/Ron(T) Iout Doc ID Rev 1 13/35

14 Electrical specifications VN5E5MJ-E Figure 7. Delay response time between rising edge of output current and rising edge of current sense (CS enabled) V IN Δt DSENSE2H t I OUT I OUTMAX 9% I OUTMAX t I SENSE I SENSEMAX 9% I SENSEMAX t 14/35 Doc ID Rev 1

15 VN5E5MJ-E Electrical specifications Figure 8. I OUT /I SENSE vs. I OUT I out / I sense max Tj = -4 C to 15 C max Tj = 25 C to 15 C 2 typical value min Tj = 25 C to 15 C = min Tj = -4 C to 15 C ,5 2 2,5 3 3,5 4 I OUT (A) Figure 9. Maximum current sense ratio drift vs. load current dk/k(%) I OUT (A) Note: Parameter guaranteed by design; it is not tested. Doc ID Rev 1 15/35

16 Electrical specifications VN5E5MJ-E Table 1. Truth table Conditions Input Output Sense (V CSD = V) (1) Normal operation L H L H Nominal Overtemperature L H L L V SENSEH Undervoltage L H L L Overload H H X (no power limitation) Cycling (power limitation) Nominal V SENSEH Short circuit to GND (power limitation) L H L L V SENSEH Negative output voltage clamp L L 1. If the V CSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. 16/35 Doc ID Rev 1

17 VN5E5MJ-E Electrical specifications Table 11. Electrical transient requirements (part 1) ISO : 24(E) Test pulse Test levels (1) Number of pulses or test times Burst cycle/pulse repetition time III IV Min. Max. Delays and Impedance 1-75V -1V 5 pulses.5s 5s 2 ms, 1Ω 2a +37V +5V 5 pulses.2s 5s 5µs, 2Ω 3a -1V -15V 1h 9ms 1ms.1µs, 5Ω 3b +75V +1V 1h 9ms 1ms.1µs, 5Ω 4-6V -7V 1 pulse 1ms,.1Ω 5b (2) +65V +87V 1 pulse 4ms, 2Ω 1. The above test levels must be considered referred to V CC = 13.5 V except for pulse 5b. 2. Valid in case of external load dump clamp: 4 V maximum referred to ground. Table 12. Electrical transient requirements (part 2) ISO : 24(E) Test pulse III Test level results (1) IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b (2) C C 1. The above test levels must be considered referred to V CC = 13.5 V except for pulse 5b 2. Valid in case of external load dump clamp: 4 V maximum referred to ground. Table 13. Electrical transient requirements (part 3) Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID Rev 1 17/35

18 Electrical specifications VN5E5MJ-E 2.4 Waveforms Figure 1. Normal operation Normal operation INPUT Nominal load Nominal load I OUT V SENSE V CS_DIS Figure 11. Overload or Short to GND Overload or Short to GND INPUT I LimH > Power Limitation I LimL > Thermal cycling I OUT V SENSE V CS_DIS 18/35 Doc ID Rev 1

19 VN5E5MJ-E Electrical specifications Figure 12. Intermittent Overload Intermittent Overload INPUT I LimH > Overload I LimL > Nominal load I OUT V SENSEH > V SENSE V CS_DIS Figure 13. T J evolution in Overload or Short to GND T J evolution in Overload or Short to GND INPUT Self-limitation of fast thermal transients T TSD T HYST T R T J_START T J I LimH > Power Limitation < I LimL I OUT Doc ID Rev 1 19/35

20 Electrical specifications VN5E5MJ-E 2.5 Electrical characteristics curves Figure 14. Off-state output current Figure 15. High level input current Iloff (na) Iih (µa) Off State Vcc=13V Vin=Vout=V 4,5 4 3,5 Vin=2.1V 4 3 2, ,5 1 1, Tc ( C) Tc ( C) Figure 16. Input clamp level Figure 17. Input low level Vicl (V) 7 6,8 6,6 6,4 6,2 6 5,8 5,6 5,4 5,2 lin=1ma Vil (V) 2 1,8 1,6 1,4 1,2 1,8,6,4, Tc ( C) Tc ( C) Figure 18. Input high level Figure 19. Input hysteresis voltage Vih (V) 4 3,5 3 2,5 2 1,5 1, Tc ( C) Vihyst (V) 1,9,8,7,6,5,4,3,2, Tc ( C) 2/35 Doc ID Rev 1

21 VN5E5MJ-E Electrical specifications Figure 2. On-state resistance vs. T case Figure 21. On-state resistance vs. V CC Ron (mohm) Ron (mohm) Iout= 2A Vcc=13V 8 Tc=15 C 2 Tc=125 C Tc=25 C 1 Tc=-4 C Tc ( C) Vcc (V) Figure 22. Undervoltage shutdown Figure 23. Turn-on voltage slope Vusd (V) (dvout/dt )On (V/ms) Vcc=13V RI=6.5 Ohm Tc ( C) Tc ( C) Figure 24. I LIMH Vs. T case Figure 25. Turn-off voltage slope Ilimh (A) 4 (dvout/dt )Off (V/ms) Vcc=13V 5 45 Vcc=13V RI= 6.5 Ohm Tc ( C) Tc ( C) Doc ID Rev 1 21/35

22 Electrical specifications VN5E5MJ-E Figure 26. CS_DIS high level voltage Figure 27. CS_DIS clamp voltage Vcsdh (V) 4 3,5 3 2,5 2 1,5 1,5 Vcsdcl(V) Iin = 1 ma Tc ( C) Tc ( C) Figure 28. CS_DIS low level voltage Vcsdl (V) 3 2,5 2 1,5 1, Tc ( C) 22/35 Doc ID Rev 1

23 VN5E5MJ-E Application information 3 Application information Figure 29. Application schematic +5V V CC R prot CS_DIS D ld ΜCU R prot IINPUT OUTPUT R prot CURRENT SENSE GND C ext R SENSE V GND R GND D GND 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery Solution 1: resistor in the ground line (R GND only) This can be used with any type of load. The following show how to dimension the R GND resistor: 1. R GND 6mV / (I S(on)max ) 2. R GND ( V CC ) / (-I GND ) where -I GND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in R GND (when V CC < during reverse battery situations) is: P D = (-V CC ) 2 /R GND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I S(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the R GND produces a shift (I S(on)max * R GND ) in the input thresholds and the status output Doc ID Rev 1 23/35

24 Application information VN5E5MJ-E values. This shift varies depending on how many devices are ON in the case of several high side drivers sharing the same R GND. If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below Solution 2: diode (D GND ) in the ground line Note that a resistor (R GND =1kΩ) should be inserted in parallel to D GND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (j6mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift not varies if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection D ld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the V CC max DC rating. The same applies if the device is subject to transients on the V CC line that are greater than the ones shown in the ISO : 24(E) table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the V CC line, the control pins is pulled negative. ST suggests to insert a resistor (R prot ) in line to prevent the MCU I/O pins from latching up. The value of these resistors is a compromise between the leakage current of MCU and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of MCU I/Os: -V CCpeak /I latchup R prot (V OHμC -V IH -V GND ) / I IHmax Calculation example: For V CCpeak = - 1V and I latchup 2mA; V OHµC 4.5V 5kΩ R prot 18kΩ Recommended values: R prot =1kΩ, C EXT =1nF. 24/35 Doc ID Rev 1

25 VN5E5MJ-E Application information 3.4 Current sense and diagnostic The current sense pin performs a double function (see Figure 3: Current sense and diagnostic): Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a know ratio K X. The current I SENSE can be easily converted to a voltage V SENSE by means of an external resistor R SENSE. Linearity between I OUT and V SENSE is ensured up to 5V minimum (see parameter V SENSE in Table 9: Current sense (8V<VCC<18V)). The current sense accuracy depends on the output current (refer to current sense electrical characteristics Table 9: Current sense (8V<VCC<18V)). Diagnostic flag in fault conditions, delivering a fixed voltage V SENSEH up to a maximum current I SENSEH in case of the following fault conditions (refer to Truth table): Power limitation activation Overtemperature A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices. Figure 3. Current sense and diagnostic V BAT V CC 41V Main MOSn I OUT /K X Overtemperature I SENSEH Pwr_Lim OUTn CS_DIS CURRENT SENSEn V SENSEH GND Load R PROT To uc ADC R SENSE V SENSE Doc ID Rev 1 25/35

26 Application information VN5E5MJ-E 3.5 Maximum demagnetization energy (V CC = 13.5V) Figure 31. Maximum turn-off current versus inductance 1 1 C A B I (A) 1,1 1 L (mh) 1 1 A: T jstart = 15 C single pulse B: T jstart = 1 C repetitive pulse C: T jstart = 125 C repetitive pulse V IN, I L Demagnetization Demagnetization Demagnetization t LΩ. In case of repetitive pulses, T jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 26/35 Doc ID Rev 1

27 VN5E5MJ-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 PowerSSO-12 thermal data Figure 32. PowerSSO-12 PC board Note: Layout condition of R th and Z th measurements (PCB: Double layer, Thermal Vias, FR4 area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 7 µm (front and back side), Copper areas: from minimum pad lay-out to 8 cm 2 ). Figure 33. R thj-amb Vs. PCB copper area in open box free air condition RTHj_amb( C/ W) PCB Cu heatsink area (cm^ 2) Doc ID Rev 1 27/35

28 Package and PCB thermal data VN5E5MJ-E Figure 34. PowerSSO-12 thermal impedance junction ambient single pulse ZTH ( C/ W) 1 Footprint 2 cm 2 8 cm 2 1 1,1,1,1, Time ( s) Equation 1: pulse calculation formula Z = R δ + Z ( 1 δ) THδ TH THtp where δ = t P /T Figure 35. Thermal fitting model of a single channel HSD in PowerSSO-12 (a) a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 28/35 Doc ID Rev 1

29 VN5E5MJ-E Package and PCB thermal data Table 14. Thermal parameter Area/island (cm 2 ) Footprint 2 8 R1 ( C/W).7 R2 ( C/W) 2.8 R3 ( C/W) 3 R4 ( C/W) R5 ( C/W) R6 ( C/W) C1 (W.s/ C).1 C2 (W.s/ C).25 C3 (W.s/ C).166 C4 (W.s/ C) C5 (W.s/ C) C6 (W.s/ C) Doc ID Rev 1 29/35

30 Package information VN5E5MJ-E 5 Package information 5.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 5.2 Package mechanical data Figure 36. PowerSSO-12 package dimensions 3/35 Doc ID Rev 1

31 VN5E5MJ-E Package information Table 15. PowerSSO-12 mechanical data Millimeters Symbol Min. Typ. Max. A A1..1 A B C D E e.8 H h.25.5 L k 8 X Y ddd.1 Doc ID Rev 1 31/35

32 Package information VN5E5MJ-E 5.3 Packing information Figure 37. PowerSSO-12 tube shipment (no suffix) A B C Base Q.ty 1 Bulk Q.ty 2 Tube length (±.5) 532 A 1.85 B 6.75 C (±.1).6 All dimensions are in mm. Figure 38. PowerSSO-12 tape and reel shipment (suffix TR ) REEL DIMENSIONS Base Q.ty 25 Bulk Q.ty 25 A (max) 33 B (min) 1.5 C (±.2) 13 F 2.2 G (+ 2 / -) 12.4 N (min) 6 T (max) 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb Tape width W 12 Tape Hole Spacing P (±.1) 4 Component Spacing P 8 Hole Diameter D (±.5) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (±.1) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (±.1) 2 All dimensions are in mm. End Start Top cover tape No components 5mm min Components Empty components pockets saled with cover tape. No components 5mm min User direction of feed 32/35 Doc ID Rev 1

33 VN5E5MJ-E Order codes 6 Order codes Table 16. Device summary Package Tube Order codes Tape and reel PowerSSO-12 VN5E5MJ-E VN5E5MJTR-E Doc ID Rev 1 33/35

34 Revision history VN5E5MJ-E 7 Revision history Table 17. Document revision history Date Revision Changes 3-Nov-29 1 Initial release. 34/35 Doc ID Rev 1

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