VND5160J-E. Double channel high side driver for automotive applications. Features. Application. Description. Electrostatic discharge protection

Transcription

1 VND516J-E Double channel high side driver for automotive applications Features Max supply voltage V CC 41V Operating voltage range V CC 4.5 to 36V Max on-state resistance R ON 16 m Current limitation (typ) I LIM 5A Off state supply current (typ) I S 2 µa (1) 1. Typical value with all loads connected. General Inrush current active management by power limitation Very low stand-by current 3.V CMOS compatible input Optimized electromagnetic emission Very low electromagnetic susceptibility In compliance with the 22/95/EC European directive Diagnostic functions Open drain status output On state open load detection Off state open load detection Thermal shutdown indication Protection Undervoltage shut-down Overvoltage clamp Output stuck to Vcc detection Load current limitation Self limiting of fast thermal transients Protection against loss of ground and loss of V CC Thermal shut down Reverse battery protection (see Figure 28) Table 1. Device summary Package Part number (Tube) Electrostatic discharge protection Application All types of resistive, inductive and capacitive loads Description PowerSSO-12 The VND516J-E is a monolithic device made using STMicroelectronics VIPower M-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). The device detects open load condition in both ON and OFF states, when STAT_DIS is left open or driven low. Output shorted to V CC is detected in the OFF state. When STAT_DIS is driven high, the STATUS pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long duration overload, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Order codes Part number (Tape & Reel) PowerSSO-12 VND516J-E VND516JTR-E September 213 Rev 6 1/

2 Contents VND516J-E Contents 1 Block diagram and pin description Electrical specifications Absolute maximum ratings Thermal data Electrical characteristics Electrical characteristics curves Application information GND protection network against reverse battery Solution 1 : resistor in the ground line (RGND only) Solution 2: a diode (DGND) in the ground line Load dump protection MCU I/Os protection Open load detection in Off state Maximum demagnetization energy (VCC = 13.5V) Package and PCB thermal data PowerSSO-12 thermal data Package information ECOPACK packages PowerSSO-12 package information Packing information Revision history /31

3 VND516J-E List of tables List of tables Table 1. Device summary Table 2. Pin functions Table 3. Suggested connections for unused and N.C. pins Table 4. Absolute maximum ratings Table 5. Thermal data Table 6. Power section Table 7. Switching (VCC = 13V; Tj = 25 C) Table 8. Status pin (V SD =) Table 9. Protection Table 1. Openload detection Table 11. Logic input Table 12. Truth table Table 13. Electrical transient requirements Table 14. Thermal parameters Table 15. PowerSSO-12 mechanical data Table 16. Document revision history /31

4 List of figures VND516J-E List of figures Figure 1. Block diagram Figure 2. Configuration diagram (top view) Figure 3. Current and voltage conventions Figure 4. Status timings Figure 5. Output voltage drop limitation Figure 6. Switching characteristics Figure 7. Waveforms Figure 8. Off state output current Figure 9. Input clamp voltage Figure 1. igh level input current Figure 11. Input high level Figure 12. Input low level Figure 13. Input hysteresis voltage Figure 14. Status low output voltage Figure 15. Status leakage current Figure 16. Status clamp voltage Figure 17. On state resistance vs T case Figure 18. On state resistance vs V CC Figure 19. Openload On state detection threshold Figure 2. Openload Off state voltage detection threshold Figure 21. Turn - On voltage slope Figure 22. Turn - Off voltage slope Figure 23. I LIM vs T case Figure 24. Undervoltage shutdown Figure 25. STAT_DIS clamp voltage Figure 26. igh level STAT_DIS voltage Figure 27. Low level STAT_DIS voltage Figure 28. Application schematic Figure 29. Open load detection in Off state Figure 3. Maximum turn Off current versus inductance (for each channel) Figure 31. PowerSSO-12 PC board Figure 32. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON) Figure 33. PowerSSO-12 Thermal impedance junction ambient single pulse (one channel ON).. 25 Figure 34. Thermal fitting model of a double channel SD in PowerSSO Figure 35. PowerSSO-12 package dimensions Figure 36. PowerSSO-12 tube shipment (no suffix) Figure 37. PowerSSO-12 tape and reel shipment (suffix TR ) /31

5 VND516J-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram V CC GND INPUT1 STATUS1 V CC CLAMP UNDERVOLTAGE CLAMP 1 CLAMP 2 OUTPUT1 STAT_DIS INPUT2 STATUS2 OVERTEMP. 1 LOGIC DRIVER 1 I LIM 1 PWR LIM 1 V DSLIM 1 OPENLOAD ON 1 DRIVER 2 I LIM 2 V DSLIM 2 OPENLOAD ON 2 OVERTEMP. 2 OPENLOAD OFF 1 OPENLOAD OFF 2 OUTPUT2 PWR LIM 2 Table 2. Pin functions Name Function V CC OUTPUTn GND INPUTn STATUSn STAT_DIS Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/ resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Open Drain digital diagnostic pin. Active high CMOS compatible pin, to disable the STATUS pin. 5/31

6 Block diagram and pin description VND516J-E Figure 2. Configuration diagram (top view) TAB = V cc GND STAT_DIS INPUT 1 STATUS 1 STATUS 2 INPUT V cc OUTPUT 1 OUTPUT 1 OUTPUT 2 OUTPUT 2 V cc Table 3. Suggested connections for unused and N.C. pins Connection / Pin STATUS N.C. OUTPUT INPUT STAT_DIS Floating X X X X X To ground N.R. (1) 1. Not recommended. X N.R. Through 1k resistor Through 1k resistor 6/31

7 VND516J-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions V CC V Fn I S V CC I SD STAT_DIS OUTPUTn I OUTn V SD I INn INPUTn STATUSn I STATn V OUTn V INn GND V STATn I GND Note: V Fn = V OUTn - V CCn during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the Absolute maximum ratings tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol Parameter Value Unit V CC DC supply voltage 41 V -V CC Reverse DC supply voltage.3 V -I GND DC reverse ground pin current 2 ma I OUT DC output current Internally limited A -I OUT Reverse DC output current 6 A I IN DC input current +1 / -1 ma I STAT DC status current +1 / -1 ma I STAT_DIS DC status disable current +1 / -1 ma E MAX Maximum switching energy (L=12m; R L = ; V bat =13.5V; T jstart =15 C; I OUT = I liml (Typ.) ) 33 mj 7/31

8 Electrical specifications VND516J-E Table 4. Absolute maximum ratings (continued) Symbol Parameter Value Unit V ESD Electrostatic discharge (uman Body Model: R=1.5K C=1pF) INPUT STATUS STAT_DIS OUTPUT V CC V ESD Charge device model (CDM-AEC-Q1-11) 75 V T j Junction operating temperature -4 to 15 C T stg Storage temperature -55 to 15 C V V V V V 2.2 Thermal data Table 5. Thermal data Symbol Parameter Max value Unit R thj-case Thermal resistance junction-case (max.) (with one channel ON) 8 C/W R thj-amb Thermal resistance junction-ambient See Figure 32 C/W 8/31

9 VND516J-E Electrical specifications 2.3 Electrical characteristics Values specified in this section are for 8V<V CC <36V; -4 C<T j <15 C, unless otherwise stated.. Table 6. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit V CC Operating supply voltage V V USD Undervoltage shutdown V V USDhyst Undervoltage Shut-down hysteresis.5 V R ON On state resistance (2) I OUT = 1A; T j = 15 C I OUT = 1A; T j = 25 C I OUT = 1A; V CC = 5V; T j = 25 C m m m V clamp Clamp voltage I S = 2mA V I S Supply current Off State; V CC =13V; V IN =V OUT = T j = 25 C; On State; V CC =13V; V IN =5V; I OUT =A 2 (1) 3 5 (1) 6 µa ma I L(off1) Off state output current (2) V IN =V OUT =V; V CC =13V; T j =25 C V IN =V OUT =V; V CC =13V; T j =125 C µa I L(off2) V IN =V; V OUT =4V -75 V F Output - V CC diode voltage (2) -I OUT =.6A; T j =15 C.7 V 1. PowerMOS leakage included. 2. For each channel. Table 7. Switching (V CC =13V; T j =25 C) Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-On delay time R L =13 (see Figure 6) 1 µs t d(off) Turn-Off delay time R L =13 (see Figure 6) 15 µs dv OUT /dt (on) Turn-On voltage slope R L =13 See Figure 21 V µs dv OUT /dt (off) Turn-Off voltage slope R L =13 See Figure 22 V µs W ON Switching energy losses during t won R L =13 (see Figure 6).7 mj W OFF Switching energy losses during t woff R L =13 (see Figure 6).4 mj 9/31

10 Electrical specifications VND516J-E Table 8. Status pin (V SD =) Symbol Parameter Test conditions Min. Typ. Max. Unit V STAT Status low output voltage I STAT = 1.6 ma, V SD =V.5 V I LSTAT Status leakage current Normal operation or V SD =5V, V STAT = 5V 1 µa C STAT Status pin input capacitance Normal operation or V SD=5V, V STAT = 5V 1 pf V SCL Status clamp voltage I STAT = 1mA I STAT = - 1mA V V Table 9. Protection (1) Symbol Parameter Test conditions Min. Typ. Max. Unit I lim DC short circuit current V CC = 13V 5V<V CC <36V Short circuit current during I liml V thermal cycling CC = 13V T R <T j <T TSD 2 A T TSD Shutdown temperature C T R Reset temperature T RS + 1 T RS + 5 C T RS Thermal reset of STATUS 135 C T YST Thermal hysteresis (T TSD -T R ) 7 C Status delay in overload t SDL T conditions j >T TSD 2 µs V DEMAG V ON Turn-Off output voltage clamp Output voltage drop limitation I OUT =1A; V IN =; L=2m V CC -41 V CC -46 V CC -52 V I OUT =.3A; T j = -4 C C (see Figure 5) 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. A A 25 mv 1/31

11 VND516J-E Electrical specifications Table 1. Openload detection Symbol Parameter Test conditions Min. Typ. Max. Unit I OL t DOL(on) t POL V OL t DSTKON Openload On state detection threshold Openload On state detection delay Delay between INPUT falling edge and STATUS rising edge in Openload condition Openload Off state voltage detection threshold Output short circuit to V cc detection delay at turn Off V IN = 5V, 8V<V CC <18V 1 I OUT = A, V CC =13V (see Figure 4) See Figure 19 4 ma 2 µs I OUT = A (see Figure 4) µs V IN = V, 8V<V CC <16V 2 See Figure 2 4 V See Figure 4 18 t POL µs Table 11. Logic input Symbol Parameter Test conditions Min. Typ. Max. Unit V IL Input low level voltage.9 V I IL Low level input current V IN =.9V 1 µa V I Input high level voltage 2.1 V I I igh level input current V IN = 2.1V 1 µa V I(hyst) Input hysteresis voltage.25 V V ICL Input clamp voltage I IN = 1mA I IN = -1mA V V V SDL STAT_DIS low level voltage.9 V I SDL Low level STAT_DIS current V CSD =.9V 1 µa V SD STAT_DIS high level voltage 2.1 V I SD igh level STAT_DIS current V CSD = 2.1V 1 µa V SD(hyst) STAT_DIS hysteresis voltage.25 V V SDCL STAT_DIS clamp voltage I SD = 1mA I SD = -1mA V V 11/31

12 Electrical specifications VND516J-E Figure 4. Status timings OPEN LOAD STATUS TIMING (without external pull-up) OPEN LOAD STATUS TIMING (with external pull-up) V IN I OUT < I OL V IN I OUT < I OL V OUT < V OL V OUT > V OL V STAT V STAT t DOL(on) t POL t DOL(on) OUTPUT STUCK TO Vcc OVER TEMP STATUS TIMING VIN I OUT > I OL V OUT > V OL V IN T j > T TSD V STAT V STAT t DOL(on) t DSTKON t SDL t SDL Figure 5. Output voltage drop limitation V cc -V out T j =15 o C T j =25 o C T j =-4 o C V on V on /R on(t) I out 12/31

13 VND516J-E Electrical specifications Table 12. Truth table Conditions INPUT n OUTPUT n STATUS n (V SD =V) (1) Normal operation L L Current limitation L L X Overtemperature L L L L Undervoltage L L L X X Output Voltage > V OL L L (2) Output Current < I OL L L (3) L 1. If the V SD is high, the STATUS pin is in a high impedance. 2. The STATUS pin is low with a delay equal to t DSTKON after INPUT falling edge. 3. The STATUS pin becomes high with a delay equal to t POL after INPUT falling edge. Figure 6. Switching characteristics V OUT t Won t Woff 8% 9% dv OUT /dt (on) tr 1% t f dv OUT /dt (off) t INPUT t d(on) t d(off) t 13/31

14 Electrical specifications VND516J-E Table 13. ISO : 24(E) test pulse Electrical transient requirements III Test levels (1) IV Number of pulses or test times Burst cycle/pulse repetition time Delays and impedance 1-75V -1V 5 pulses.5 s 5 s 2 ms, 1 2a +37V +5V 5 pulses.2 s 5 s 5 µs, 2 3a -1V -15V 1h 9 ms 1 ms.1 µs, 5 3b +75V +1V 1h 9 ms 1 ms.1 µs, 5 4-6V -7V 1 pulse 1 ms,.1 5b (2) +65V +87V 1 pulse 4 ms, 2 ISO : 24(E) test pulse III Test level results (1) IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b (2) C C 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 4V maximum referred to ground. Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 14/31

15 VND516J-E Electrical specifications Figure 7. Waveforms INPUT STAT_DIS LOAD CURRENT STATUS NORMAL OPERATION UNDERVOLTAGE V CC VUSD V USDhyst INPUT STAT_DIS LOAD CURRENT STATUS undefined OPEN LOAD with external pull-up INPUT STAT_DIS LOAD VOLTAGE STATUS V OL V OUT >V OL INPUT STAT_DIS LOAD VOLTAGE LOAD CURRENT STATUS OPEN LOAD without external pull-up I OUT <I OL t POL RESISTIVE SORT TO Vcc, NORMAL LOAD INPUT STAT_DIS LOAD VOLTAGE STATUS I OUT >I OL V OUT >V OL V OL t DSTKON OVERLOAD OPERATION T TR T TSD j T RS INPUT STAT_DIS LOAD CURRENT I LIM I LIML STATUS current limitation power limitation SORTED LOAD thermal cycling NORMAL LOAD 15/31

16 Electrical specifications VND516J-E 2.4 Electrical characteristics curves Figure 8. Off state output current Figure 9. Input clamp voltage Iloff1 (ua) Vicl (V) Off state Vcc=13V Vin=Vout=V Iin=1mA Figure 1. igh level input current Figure 11. Input high level Iih (ua) Vin=2.1V Vih (V) Figure 12. Input low level Figure 13. Input hysteresis voltage Vil (V) 4 Vihyst (V) /31

17 VND516J-E Electrical specifications Figure 14. Status low output voltage Figure 15. Status leakage current Vstat (V).9 Ilstat (ua) Istat=1.6mA Vstat=5V Figure 16. Status clamp voltage Figure 17. On state resistance vs T case Vscl (V) Ron (mohm) Istat=1mA Iout=1A Vcc=13V Figure 18. On state resistance vs V CC Figure 19. Openload On state detection threshold Ron (mohm) 3 Iol (ma) Tc=15 C Tc=125 C Vin=5V Tc=25 C Tc=-4 C Vcc (V) 17/31

18 Electrical specifications VND516J-E Figure 2. Openload Off state voltage detection threshold Figure 21. Turn - On voltage slope Vol (V) 5 dvout/dt(on) (V/ms) Vin=V Vcc=13V Ri=6.5Ohm Figure 22. Turn - Off voltage slope Figure 23. I LIM vs T case dvout/dt(off) (V/ms) 1 9 Ilimh (A) Vcc=13V 6 Vcc=13V Ri=13Ohm Figure 24. Undervoltage shutdown Figure 25. STAT_DIS clamp voltage Vusd (V) 14 Vsdcl (V) Isd=1mA /31

19 VND516J-E Electrical specifications Figure 26. igh level STAT_DIS voltage Figure 27. Low level STAT_DIS voltage Vsdh (V) 8 Vsdl (V) /31

20 Application information VND516J-E 3 Application information Figure 28. Application schematic +5V +5V V CC R prot STAT_DIS µc R prot INPUT D ld R prot STATUS OUTPUT GND V GND R GND D GND Note: Channels 2, has the same internal circuit as channel GND protection network against reverse battery Solution 1 : resistor in the ground line (R GND only) This can be used with any type of load. The following is an indication on how to dimension the R GND resistor. 1. R GND 6mV / (I S(on)max ). 2. R GND V CC ) / (-I GND ) where -I GND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in R GND (when V CC <: during reverse battery situations) is: P D = (-V CC ) 2 /R GND This resistor can be shared amongst several different SDs. Please note that the value of this resistor should be calculated with formula (1) where I S(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the R GND will produce a shift (I S(on)max * R GND ) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R GND. 2/31

21 VND516J-E Application information If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below) Solution 2: a diode (D GND ) in the ground line A resistor (R GND =1k should be inserted in parallel to D GND if the device drives an inductive load. This small signal diode can be safely shared amongst several different SDs. Also in this case, the presence of the ground network will produce a shift ( 6mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one SD shares the same diode/resistor network. 3.2 Load dump protection D ld is necessary (Voltage transient suppressor) if the load dump peak voltage exceeds the V CC max DC rating. The same applies if the device is subject to transients on the V CC line that are greater than the ones shown in the ISO : 24(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient are present on the V CC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot ) in line to prevent the µc I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the SD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -V CCpeak /I latchup R prot (V O C -V I -V GND ) / I Imax Calculation example: For V CCpeak = - 1V and I latchup 2mA; V O C 4.5V 5k R prot 18k. Recommended R prot values is 1k 3.4 Open load detection in Off state Off state open load detection requires an external pull-up resistor (R PU ) connected between OUTPUT pin and a positive supply voltage (V PU ) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid V OUT to be higher than V Olmin ; this results in the following condition V OUT =(V PU /(R L +R PU ))R L <V Olmin. 2. no misdetection when load is disconnected: in this case the V out has to be higher than V OLmax ; this results in the following condition R PU <(V PU V OLmax )/I L(off2). 21/31

22 Application information VND516J-E Because I s(off) may significantly increase if V out is pulled high (up to several ma), the pullup resistor R PU should be connected to a supply that is switched OFF when the module is in standby. The values of V OLmin, V OLmax and I L(off2) are available in the Electrical characteristics section. Figure 29. Open load detection in Off state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) STATUS + - R OUT VOL RL GROUND 22/31

23 VND516J-E Application information 3.5 Maximum demagnetization energy (V CC = 13.5V) Figure 3. Maximum turn Off current versus inductance (for each channel) 1 A B C 1 I (A),1,1 1 L (m) 1 1 A: T jstart = 15 C single pulse B: T jstart = 1 C repetitive pulse C: T jstart = 125 C repetitive pulse V IN, I L Demagnetization Demagnetization Demagnetization t Note: Values are generated with R L = In case of repetitive pulses, T jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 23/31

24 Package and PCB thermal data VND516J-E 4 Package and PCB thermal data 4.1 PowerSSO-12 thermal data Figure 31. PowerSSO-12 PC board Note: Layout condition of R th and Z th measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=7µm (front and back side), Copper areas: from minimum pad lay-out to 8cm 2 ). Figure 32. R thj-amb vs. PCB copper area in open box free air condition (one channel ON) RTj_amb( C/ W) PCB Cu heatsink area (cm^ 2) 24/31

25 VND516J-E Package and PCB thermal data Figure 33. PowerSSO-12 Thermal impedance junction ambient single pulse (one channel ON) ZT ( C/ W) 1 Footprint 2 cm 2 8 cm 2 1 1,1,1,1,1, Time ( s) Pulse calculation formula Z = R + Z 1 T T Ttp where = t P /T Figure 34. Thermal fitting model of a double channel SD in PowerSSO-12 (a) a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 25/31

26 Package and PCB thermal data VND516J-E Table 14. Thermal parameters Area/island (cm 2 ) Footprint 2 8 R1=R7 ( C/W) 1.2 R2=R8 ( C/W) 6 R3 ( C/W) 7 R4 ( C/W) R5 ( C/W) R6 ( C/W) C1=C7 (W.s/ C).8 C2=C8 (W.s/ C).16 C3 (W.s/ C).5 C4 (W.s/ C) C5 (W.s/ C) C6 (W.s/ C) /31

27 VND516J-E Package and packing information 5 Package and packing information 5.1 ECOPACK packages In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: PowerSSO-12 package information Figure 35. PowerSSO-12 package dimensions 27/31

28 Package and packing information VND516J-E Table 15. PowerSSO-12 mechanical data Millimeters Symbol Min. Typ. Max. A A1..1 A B C D E e h.25.5 L k 8 X Y ddd.1 28/31

29 VND516J-E Package and packing information 5.3 Packing information Figure 36. PowerSSO-12 tube shipment (no suffix) A B C Base Q.ty 1 Bulk Q.ty 2 Tube length (±.5) 532 A 1.85 B 6.75 C (±.1).6 All dimensions are in mm. Figure 37. PowerSSO-12 tape and reel shipment (suffix TR ) REEL DIMENSIONS Base Q.ty 25 Bulk Q.ty 25 A (max) 33 B (min) 1.5 C (±.2) 13 F 2.2 G (+ 2 / -) 12.4 N (min) 6 T (max) 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb Tape width W 12 Tape ole Spacing P (±.1) 4 Component Spacing P 8 ole Diameter D (±.5) 1.5 ole Diameter D1 (min) 1.5 ole Position F (±.1) 5.5 Compartment Depth K (max) 4.5 ole Spacing P1 (±.1) 2 All dimensions are in mm. End Start Top cover tape No components 5mm min Components No components 5mm min Empty components pockets saled with cover tape. User direction of feed 29/31

30 Revision history VND516J-E 6 Revision history Table 16. Document revision history Date Revision Changes 7-Jan-24 1 Initial release. 3-Feb-26 2 Major series of updates incorporated. 2-Mar Jun Dic-27 5 Reformatted. Added list of tables and list of figures. Added Section 3.5: Maximum demagnetization energy (VCC = 13.5V). Added new disclaimer. Updated Table 4: Absolute maximum ratings: EMAX entries. Updated Table 13: Electrical transient requirements :Test level values III and IV for test pulse 5b and notes. Figure 34: Thermal fitting model of a double channel SD in PowerSSO-12 added note. Updated Section 4.1: PowerSSO-12 thermal data: Changed Figure 32: Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). Changed Figure 33: PowerSSO-12 Thermal impedance junction ambient single pulse (one channel ON). Updated Table 14: Thermal parameters: R1 and R7 values changed from 1.2 to.1 C/W. R2 = R8 values changed from 6 to.2 C/W. R3 value changed from 7 to 4 C/W. R4 values changed from 1/1/9 to 8/8/7 C/W. C1=C7 values changed from.8 to.1 C/W. C2=C8 values changed from.16 to.2 C/W. 24-Sep Updated disclaimer. 3/31

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