VN5016AJ-E SINGLE CHANNEL HIGH SIDE DRIVER WITH ANALOG CURRENT SENSE FOR AUTOMOTIVE APPLICATIONS

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1 查询 VIPER5-E 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 SINGE CANNE IG SIDE DRIVER WIT ANAOG CURRENT SENSE FOR AUTOMOTIVE APPICATIONS ADVANCE DATA Table 1. General Features Figure 1. Package TYPE R DS(on) I D 41V 16mΩ 4A CURRENT: 4A 3.V CMOS COMPATIBE CURRENT SENSE DISABE PROPORTIONA OAD CURRENT SENSE UNDERVOTAGE SUT-DOWN OVERVOTAGE CAMP TERMA SUT DOWN CURRENT AND POWER IMITATION VERY OW STAND-BY CURRENT PROTECTION AGAINST OSS OF GROUND AND OSS OF VERY OW EECTROMAGNETIC SUSCEPTIBIITY OPTIMIZED EECTROMAGNETIC EMISSION REVERSE BATTERY PROTECTION (*) IN COMPIANCE WIT TE 22/95/EC EUROPEAN DIRECTIVE DESCRIPTION The is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). PowerSSO-12 This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when is driven low or left open. When is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Table 2. Order Codes Package Tube Tape and Reel PowerSSO-12 VN516AJTR-E Note: (*) See application schematic at page 8 January 25 This is preliminary information on a new product now in development. Details are subject to change without notice. Rev. 2 1/13

2 Figure 2. Block Diagram CAMP UNDERVOTAGE GND DRIVER PwCAMP I IM OGIC Pwr IM OVERTEMP. V DSIM I OUT K CURRENT SENSE Table 3. Pin Function Name Function Battery connection Power output GND Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current Active high CMOS compatible pin, to disable the current sense pin Figure 3. Current and Voltage Conventions I S V F V CSD I CSD I IN CURRENT SENSE I OUT I SENSE V OUT V IN GND V SENSE I GND 2/13

3 Figure 4. Configuration Diagram (Top View) & Suggested Connections For Unused and n.c. Pins TAB = V cc GND CURRENT SENSE Connection / Pin Current Sense N.C. Output Input Floating X X X X To Ground Through 1KΩ resistor X Through 1KΩ resistor Through 1KΩ resistor Table 4. Absolute Maximum Ratings Symbol Parameter Value Unit DC supply voltage 41 V - Reverse DC supply voltage -.3 V - I GND DC reverse ground pin current -2 ma I OUT DC output current Internally limited A - I OUT Reverse DC output current -3 A I IN DC input current -1 to 1 ma I CSD DC current sense disable input current -1 to 1 ma V CSENSE Current sense maximum voltage -41 V + V V ESD Electrostatic discharge (R=1.5kΩ; C=1pF) 2 V T j Junction operating temperature -4 to 15 C T stg Storage temperature -55 to 15 C Table 5. Thermal Data Symbol Parameter Max Value Unit R thj-case Thermal resistance junction-case 2.3 C/W R thj-amb Thermal resistance junction-ambient 75 (see note 1) C/W Note: 1. When mounted on a standard single-sided FR4 board with.5cm 2 of Cu (at least 35 µm thick) connected to TAB. 3/13

4 EECTRICA CARACTERISTICS (8V< <36V; -4 C<T j <15 C, unless otherwise specified) Table 6. Power Section Symbol Parameter Test Conditions Min. Typ. Max. Unit Operating supply voltage V V USD Undervoltage shutdown V V USDhyst Undervoltage Shut-down hysteresis.5 V R ON On state resistance I OUT =5A; T j =25 C I OUT =5A; T j =15 C I OUT =5A; =5V; T j =25 C mω mω mω V clamp Clamp Voltage I S =2mA V I S Supply current Off State; =13V; T j =25 C; V IN =V OUT =V SENSE =V CSD =V On State; =13V; V IN =5V; I OUT =A 2(**) 1.5 5(**) 3 µa ma I (off) Off state output current V IN =V OUT =V; =13V; T j =25 C V IN =V OUT =V; =13V; T j =125 C 3 5 µa Note: (**) PowerMOS leakage included Table 7. Switching ( =13V) Symbol Parameter Test Conditions Min. Typ. Max. Unit t d(on) Turn-on delay time R =2.6Ω 15 µs t d(off) Turn-off delay time R =2.6Ω 4 µs (dv OUT /dt) on Turn-on voltage slope R =2.6Ω.3 V/µs (dv OUT /dt) off Turn-off voltage slope R =2.6Ω.35 V/µs W ON Switching losses energy at turn-on R =2.6Ω mj W OFF Switching losses energy at turn-off R =2.6Ω mj 4/13

5 EECTRICA CARACTERISTICS (continued) Table 8. ogic Input Symbol Parameter Test Conditions Min. Typ. Max. Unit V I Input low level voltage.9 V I I ow level input current V IN =.9V 1 µa V I Input high level voltage 2.1 V I I igh level input current V IN =2.1V 1 µa V I(hyst) Input hysteresis voltage.25 V V IC Input clamp voltage I IN =1mA 5.5 V I IN =-1mA -.7 V V CSD low level voltage.9 V I CSD ow level current V CSD =.9V 1 µa V CSD high level voltage 2.1 V I CSD igh level current V CSD =2.1V 1 µa V CSD(hyst) hysteresis voltage.25 V V CSC clamp voltage I CSD =1mA 5.5 V I CSD =-1mA -.7 V Table 9. Protections and Diagnostics (see note 2) Symbol Parameter Test Conditions Min. Typ. Max. Unit I lim DC Short circuit current =13V 5V< <36V I lim Short circuit current during thermal cycling =13V T R <T j <T TSD 24 A T TSD Shutdown temperature C T R Reset temperature T RS + 1 T RS + 5 C T RS Thermal reset of STATUS 135 C T YST Thermal hysteresis (T TSD -T R ) 7 C V DEMAG Turn-off output voltage clamp I OUT =2A; V IN =; =6m A A V V ON Output voltage drop limitation I OUT =.3A; T j = -4 C C (see figure 9) 25 mv Note: 2. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles 5/13

6 EECTRICA CARACTERISTICS (continued) Table 1. Current Sense (8V< <16V) Symbol Parameter Test Conditions Min. Typ. Max. Unit I OUT =1.5A; V SENSE =.5V; V CSD =V; K 1 I OUT /I SENSE 5 T j = -4 C...15 C K 2 I OUT /I SENSE T j =-4 C I OUT =1A; V SENSE =4V; V CSD =V; T j =25 C...15 C K 3 I OUT /I SENSE T j =-4 C I OUT =25A; V SENSE =4V; V CSD =V; T j =25 C...15 C I SENSE V SENSE Analog sense current Max analog sense output voltage I OUT =A; V SENSE =V; V CSD =5V; V IN =V; T j =-4 C...15 C V CSD =V; V IN =5V; T j =-4 C...15 C I OUT =15A; V CSD =V; R SENSE =3.9KΩ 5 V 5 1 µa µa V SENSE I SENSE t DSENSE1 t DSENSE1 t DSENSE2 t DSENSE2 Analog sense output voltage in overtemperature condition Analog sense output current in overtemperature condition Delay Response time from falling edge of pin Delay Response time from rising edge of pin Delay Response time from rising edge of pin Delay Response time from falling edge of pin =13V; R SENSE =3.9KΩ 9 V =13V, V SENSE =5V 8 ma V SENSE <4V, 1.5A<Iout<25A I SENSE =9% of I SENSE max (see fig 5) 5 1 µs V SENSE <4V, 1.5A<Iout<25A I SENSE =1% of I SENSE max (see fig 5) 5 2 µs V SENSE <4V, 1.5A<Iout<25A I SENSE =9% of I SENSE max (see fig 5) 27 6 µs V SENSE <4V, 1.5A<Iout<25A 1 25 µs I SENSE =1% of I SENSE max (see fig 5) Table 11. Truth Table CONDITIONS Normal operation Overtemperature Undervoltage Short circuit to GND Short circuit to Negative output voltage clamp Note: 3. If the V CSD is high, the SENSE output is at a high impedance. SENSE (V CSD =V) (see note 3) Nominal V SENSE < Nominal 6/13

7 Figure 5. OAD CURRENT SENSE CURRENT t DSENSE2 t DSENSE1 t DSENSE1 tdsense2 Figure 6. Switching Characteristics V OUT 8% 9% dv OUT/dt (on) t r 1% t f dv OUT/dt (off) t t d(on) t d(off) t Table 12. Electrical Transient Requirements TEST EVES ISO T/R 7637/1 I II III IV Delays and Test Pulse Impedance 1-25 V -5 V -75 V -1 V 2 ms 1 Ω V +5 V +75 V +1 V.2 ms 1 Ω 3a -25 V -5 V -1 V -15 V.1 µs 5 Ω 3b +25 V +5 V +75 V +1 V.1 µs 5 Ω 4-4 V -5 V -6 V -7 V 1 ms,.1 Ω V V V V 4 ms, 2 Ω ISO T/R 7637/1 TEST EVES RESUTS Test Pulse I II III IV 1 C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E CASS C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 7/13

8 Figure 7. Application Schematic +5V R prot D ld µc R prot R prot CURRENT SENSE GND R SENSE V GND R GND D GND Note: Channel 2 has the same internal circuit as channel 1. GND PROTECTION NETWORK AGAINST REVERSE BATTERY Solution 1: Resistor in the ground line (R GND only). This can be used with any type of load. The following is an indication on how to dimension the R GND resistor. 1) R GND 6mV / (I S(on)max ). 2) R GND ( ) / (-I GND ) where -I GND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in R GND (when <: during reverse battery situations) is: P D = (- ) 2 /R GND This resistor can be shared amongst several different SDs. Please note that the value of this resistor should be calculated with formula (1) where I S(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the R GND will produce a shift (I S(on)max * R GND ) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R GND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). Solution 2: A diode (D GND ) in the ground line. A resistor (R GND =1kΩ) should be inserted in parallel to D GND if the device drives an inductive load. This small signal diode can be safely shared amongst several different SDs. Also in this case, the presence of the ground network will produce a shift (j6mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one SD shares the same diode/resistor network. OAD DUMP PROTECTION D ld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the max DC rating. The same applies if the device is subject to transients on the line that are greater than the ones shown in the ISO T/R 7637/1 table. µc I/Os PROTECTION: If a ground protection network is used and negative transient are present on the line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot ) in line to prevent the µc I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µc and the current required by the SD I/Os (Input levels compatibility) with the latch-up limit of µc I/Os. -peak /I latchup R prot (V OµC -V I -V GND ) / I Imax Calculation example: For peak = - 1V and I latchup 2mA; V OµC 4.5V 5kΩ R prot 65kΩ. Recommended R prot value is 1kΩ. 8/13

9 Figure 8. Waveforms OAD CURRENT SENSE CURRENT NORMA OPERATION UNDERVOTAGE V USD V USDhyst OAD CURRENT SENSE CURRENT SORT TO OAD VOTAGE OAD CURRENT SENSE CURRENT <Nominal <Nominal OVEROAD OPERATION T j T TR TSD T RS OAD CURRENT SENSE CURRENT I IM I IM V SENSE current limitation power limitation SORTED OAD thermal cycling NORMA OAD 9/13

10 Figure 9. V cc -V out T j =15 o C T j =25 o C T j =-4 o C V on V on /R on(t) I out 1/13

11 PACKAGE MECANICA Table 13. PowerSSO-12 Mechanical Data Symbol millimeters Min Typ Max A A1..1 A B C D E e h k º 8º X Y ddd.1 Figure 1. PowerSSO-12 Package Dimensions 11/13

12 REVISION ISTORY Table 14. Revision istory Date Revision Description of Changes Oct First issue. Jan Minor text changes. 12/13

13 Information furnished is believed to be accurate and reliable. owever, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 24 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - ong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 13/13