L4925. Very low drop voltage regulator. Features. Description

Transcription

1 Very low drop voltage regulator Features Operating DC supply voltage range 6 V to 28 V Transient supply voltage up to 40 V Extremely low quiescent current High precision output voltage Output current capability up to 500 ma Very low dropout voltage less than 0.6 V Reset circuit sensing the output voltage Programmable reset pulse delay with external capacitor Thermal shutdown and short circuit protections Description PowerSO-20 The is a monolithic integrated 5 V voltage regulator with a very low dropout output and additional functions such as power-on reset and programmable reset delay time. It is designed for supplying microcomputer controlled systems especially in automotive applications. Table 1. Device summary Package Tube Order codes Tape and reel PowerSO-20 PD PD013TR September 2013 Doc ID 1770 Rev 8 1/14 1

2 Contents Contents 1 Block and pin connections diagrams Thermal data Electrical specifications Absolute maximum ratings Electrical characteristics Functional description Voltage regulator Reset circuit Application information Supply voltage transients Application circuit Package Informations Revision history /14 Doc ID 1770 Rev 8

3 List of tables List of tables Table 2. Thermal data Table 3. Absolute maximum ratings Table 4. Electrical characteristics Table 5. Document revision history Doc ID 1770 Rev 8 3/14

4 List of figures List of figures Figure 1. Block diagram Figure 2. PowerSO-20 pin connections (top view) Figure 3. Foldback characteristics of V O Figure 4. Output voltage vs input voltage Figure 5. Quiescent current vs supply voltage Figure 6. Block circuit diagram Figure 7. Reset output waveforms Figure 8. Application circuit diagram Figure 9. PowerSO-20 mechanical data and package dimensions /14 Doc ID 1770 Rev 8

5 Block and pin connections diagrams 1 Block and pin connections diagrams Figure 1. Block diagram PREREGULATOR 5V Vz VREF 1.23V V O C S V S + Vz 2μ CT RES - = 2V GND REG RESET D95AT151 Figure 2. PowerSO-20 pin connections (top view) Connected to pin GND N.C. 1 2 V S 3 V S 4 N.C. 5 N.C. 6 RES 7 N.C. 8 N.C. 9 GND GND 19 N.C. 18 N.C. 17 V OUT 16 V OUT 15 N.C. 14 CT 13 N.C. 12 N.C. 11 GND D95AT Thermal data Table 2. Thermal data Symbol Parameter PowerSO-20 Unit R th(j-amb) Thermal resistance junction to ambient 15 to 60 C/W R th(j-c) Thermal resistance junction to case (max) 3.5 C/W Doc ID 1770 Rev 8 5/14

6 Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit V SDC DC operating supply voltage 28 V V STR Transient supply voltage (t < 1s) 40 V I O Output current internally limited V O Output voltage 20 V V RES Output voltage 20 V I RES Output current 5 ma T stg Storage temperature -55 to 150 C T j Operating junction temperature -40 to 150 C T j-sd Thermal shutdown-junction temperature 165 C Note: The circuit is ESD protected according to MIL-STD-883C. According to ISO/DIS 7637 the transients must be clamped with external circuitry (see Application Circuit). 2.2 Electrical characteristics Table 4. V S =14 V; T j = 40 to 125 C unless otherwise specified. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit V O Output voltage V I = 6 to 28 V; I O = 1 to 500 ma V V O V DP V IO Output voltage Dropout voltage Input to output voltage difference in undervoltage condition V I = 35 V; T < 1 s; I O = 1 to 500 ma 5.50 V I O = 100 ma V I O = 500 ma V V I = 4 V; I O = 100 ma 0.5 V V OL Line regulation V I = 6 to 28 V; I O = 1 to 1 ma 10 mv V OLO Load regulation I O = 1 to 500 ma 50 mv I LIM Current limit V O = 4.5 V; ma V O = 0; Foldback characteristic 250 ma I QSE Quiescent current I O = 0.3 ma µa I Q Quiescent current I O = 500 ma 20 ma 6/14 Doc ID 1770 Rev 8

7 Electrical specifications Table 4. Reset Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit V RT Reset threshold voltage V V RTH Reset threshold mv t RD Reset pulse delay C T = 100 nf; t R 100 µs ms t RR Reset reaction time C T = 100 nf; 5 30 µs V RL Reset output low voltage R RES = 10 K to V O ; V S = 3 V 0.4 V I RH Reset output high leakage current V RES = 5 V 1 µa V CTth Delay comparator threshold 2 V V CTth hy Delay comparator threshold hysteresis 200 mv Doc ID 1770 Rev 8 7/14

8 Functional description 3 Functional description The is a monolithic integrated voltage regulator, based on the STM modular voltage regulator approach. Several outstanding features and auxiliary functions are implemented to meet the requirements of supplying microprocessor systems in automotive applications. Nevertheless, it is suitable also in other applications where the present functions are required. The modular approach of this device allows to get easily also other features and functions when required. 3.1 Voltage regulator The voltage regulator uses an Isolated Collector Vertical PNP transistor as a regulating element. With this structure very low dropout voltage at currents up to 500 ma is obtained. Figure 3. Foldback characteristics of V O The dropout operation of the standby regulator is maintained down to 3 V input supply voltage. The output voltage is regulated up to the transient input supply voltage of 35 V. With this feature no functional interruption due to overvoltage pulses is generated. The typical curve showing the standby output voltage as a function of the input supply voltage is shown in Figure 4. The current consumption of the device (quiescent current) is less than 250 µa. To reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region, the dropout voltage is controlled. The quiescent current as a function of the supply input voltage is shown in Figure 5. 8/14 Doc ID 1770 Rev 8

9 Functional description Figure 4. Output voltage vs input voltage Figure 5. Quiescent current vs supply voltage 3.2 Reset circuit The block circuit diagram of the reset circuit is shown in Figure 6. The reset circuit supervises the output voltage. The reset threshold of 4.5 V is defined with the internal reference voltage and standby output divider. The reset pulse delay time t RD, is defined with the charge time of an external capacitor CT: C t T 2V RD = A The reaction time of the reset circuit originates from the discharge time limitation of the reset capacitor CT and it is proportional to the value of CT. The reaction time of the reset circuit increases the noise immunity. Standby output voltage drops below the reset threshold only a bit longer than the reaction time results in a shorter reset delay time. The nominal reset delay time is generated for standby output voltage drops longer than approximately 50 ms. The typical reset output waveforms are shown in Figure 7. Doc ID 1770 Rev 8 9/14

10 Functional description Figure 6. Block circuit diagram Figure 7. Reset output waveforms 10/14 Doc ID 1770 Rev 8

11 Application information 4 Application information 4.1 Supply voltage transients High supply voltage transients can cause a reset output signal disturbance. For supply voltage greater than 8 V the circuit shows a high immunity of the reset output against supply transients of more than 100 V/ms. For supply voltage lower than 8 V, supply transients of more than 0.4 V/ms. can cause a reset signal disturbance. 4.2 Application circuit Figure 8. Application circuit diagram PREREGULATOR 5V Vz VREF 1.23V Vo Co Vout VBAT V S Vz CT C S + 2μ RES RES - = 2V GND REG RESET D95AT153 For stability: C S 1µF; C O 10 µf; ESR 2.5 at 10 KHz Recommended for application: C S = C O = 10 µf to 100 µf Doc ID 1770 Rev 8 11/14

12 Package Informations 5 Package Informations Figure 9. PowerSO-20 mechanical data and package dimensions DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A a a a b c D (1) D1 (2) E e e E1 (1) E E G H h L N 8 (typ.) S 8 (max. ) T (1) D and E1 do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006 ) - Critical dimensions: E, G and a3. (2) For subcontractors, the limit is the one quoted in jedec MO-166 Weight: 1.9gr OUTLINE AND MECHANICAL DATA JEDEC MO-166 PowerSO-20 N N R a2 A c b DETAIL A e DETAIL B E a1 e3 H lead DETAIL A D a3 slug DETAIL B Gage Plane C - E2 E1 BOTTOM VIEW S L SEATING PLANE G C (COPLANARITY) T E h x 45 PSO20MEC D I 12/14 Doc ID 1770 Rev 8

13 Revision history 6 Revision history Table 5. Document revision history Date Revision Changes 01-Oct First issue in EDOCD DMS 18-Nov Added GND pins to fig. 4 Added order code and changed the formatting style in compliance with the new template 03-Feb Feb Reset Threshold Voltage changed from 4.5V / 5.2V (min/max) to 4.2V / 4.8V on Table 4. Reformatted entire document. Removed PENTAWATT package Updated Table 2: Thermal data 20-Sep Updated disclaimer. Doc ID 1770 Rev 8 13/14

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