ICL7106, ICL7107 ICL7106S, ICL7107S

Transcription

1 August 99 SEMICONDUCTOR Complete Dt Sheet ville vi we, Hrris home pge: or vi Hrris AnswerFAX, see Setion ICL06, ICL0 ICL06S, ICL0S 3 / 2 Digit, LCD/LED Disply, A/D Converters Fetures Gurnteed Zero Reding for 0V Input on All Sles True Polrity t Zero for Preise Null Detetion pa Typil Input Current True Differentil Input nd Referene, Diret Disply Drive LCD ICL06, LED lcl0 Low Noise Less Thn 5µV PP On Chip Clok nd Referene Low Power Dissiption Typilly Less Thn 0mW No Additionl Ative Ciruits Required Enhned Disply Stility (ICL06S, ICL0S) Ordering Informtion PART NO. TEMP. RANGE ( o C) PACKAGE PKG. NO. Desription The Hrris ICL06 nd ICL0 re high performne, low power, 3 / 2 digit A/D onverters. Inluded re seven segment deoders, disply drivers, referene, nd lok. The ICL06 is designed to interfe with liquid rystl disply (LCD) nd inludes multiplexed kplne drive; the ICL0 will diretly drive n instrument size light emitting diode (LED) disply. The ICL06 nd ICL0 ring together omintion of high ury, verstility, nd true eonomy. It fetures utozero to less thn 0µV, zero drift of less thn µv/ o C, input is urrent of 0pA (Mx), nd rollover error of less thn one ount. True differentil inputs nd referene re useful in ll systems, ut give the designer n unommon dvntge when mesuring lod ells, strin guges nd other ridge type trnsduers. Finlly, the true eonomy of single power supply opertion (ICL06), enles high performne pnel meter to e uilt with the ddition of only 0 pssive omponents nd disply. ICL06CPL 0 to 0 Ld PDIP E.6 ICL06RCPL 0 to 0 Ld PDIP (Note) E.6 ICL06CM44 0 to 0 44 Ld MQFP Q44.0x0 ICL06SCPL 0 to 0 Ld PDIP E.6 ICL0SCPL 0 to 0 Ld PDIP E.6 ICL0CPL 0 to 0 Ld PDIP E.6 ICL0RCPL 0 to 0 Ld PDIP (Note) E.6 ICL0CM44 0 to 0 44 Ld MQFP Q44.0x0 NOTE: R indites devie with reversed leds for mounting to PC ord underside. S indites enhned stility. CAUTION: These devies re sensitive to eletrostti dishrge. Users should follow proper IC Hndling Proedures. Copyright Hrris Corportion 99 3 File Numer 82.

2 Pinouts ICL06, ICL0 (PDIP) TOP VIEW ICL06R, ICL0R (PDIP) TOP VIEW D 2 2 D C 3 3 C B 4 4 B ( s) A 5 5 A ( s) F 6 6 F G G E 8 8 E D2 9 9 D2 C2 0 0 C2 (0 s) B2 A2 2 2 B2 A2 (0 s) F2 3 3 F2 E2 4 4 E2 D3 5 5 D3 (00 s) B3 F3 E3 6 8 (0 s) (00 s) (0 s) (00 s) 6 8 B3 F3 E3 (00 s) (000) AB4 9 9 (000) AB4 (MUS) POL 20 BP/GND BP/GND 20 POL (MUS) ICL06, ICL0 (MQFP) TOP VIEW NC NC NC D C B NC BP/GND POL AB4 E3 F3 B3 A F G E D2 C2 B2 A2 F2 E2 D3 3

3 Asolute Mximum Rtings Supply Voltge ICL06, to V ICL0, to GND V ICL0, to GND V Anlog Input Voltge (Either Input) (Note ) to Referene Input Voltge (Either Input) to Clok Input ICL to ICL GND to Operting Conditions Temperture Rnge o C to 0 o C Therml Informtion Therml Resistne (Typil, Note 2) θ JA ( o C/W) PDIP Pkge MQFP Pkge Mximum Juntion Temperture o C Mximum Storge Temperture Rnge o C to 50 o C Mximum Led Temperture (Soldering 0s) o C (MQFP Led Tips Only) CAUTION: Stresses ove those listed in Asolute Mximum Rtings my use permnent dmge to the devie. This is stress only rting nd opertion of the devie t these or ny other onditions ove those indited in the opertionl setions of this speifition is not implied. NOTES:. Input voltges my exeed the supply voltges provided the input urrent is limited to ±00µA. 2. θ JA is mesured with the omponent mounted on n evlution PC ord in free ir. Eletril Speifitions (Note 3) SYSTEM PERFORMANCE PARAMETER CONDITIONS M TYP MAX UNIT Zero Input Reding V = 0.0V, Full Sle = 200mV ± Digitl Reding Stility (Lst Digit) (ICL06S, ICL0S Only) Fixed Input Voltge (Note ) ± Digitl Reding Rtiometri Reding V ln = V REF, V REF = 00mV / Digitl Reding Rollover Error Linerity V = V ln 200mV Differene in Reding for Equl Positive nd Negtive Inputs Ner Full Sle Full Sle = 200mV or Full Sle = 2V Mximum Devition from Best Stright Line Fit (Note 5) ±0.2 ± Counts ±0.2 ± Counts Common Mode Rejetion Rtio V CM = V, V = 0V, Full Sle = 200mV (Note 5) 50 µv/v Noise V = 0V, Full Sle = 200mV (PekToPek Vlue Not Exeeded 95% of Time) 5 µv Lekge Current Input V ln = 0 (Note 5) 0 pa Zero Reding Drift V ln = 0, 0 o C To 0 o C (Note 5) 0.2 µv/ o C Sle Ftor Temperture Coeffiient V = 99mV, 0 o C To 0 o C, (Ext. Ref. 0ppm/ o C) (Note 5) 5 ppm/ o C End Power Supply Chrter Supply Current V = 0 (Does Not Inlude LED Current for ICL0).0.8 ma End Power Supply Chrter Supply Current ICL0 Only ma Pin Anlog Common Voltge Temperture Coeffiient of Anlog Common DISPLAY DRIVER ICL06 ONLY kω Between Common nd Positive Supply (With Respet to Supply) kω Between Common nd Positive Supply (With Respet to Supply) V 80 ppm/ o C PekToPek Segment Drive Voltge PekToPek Bkplne Drive Voltge = to = 9V (Note 4) V 3

4 Eletril Speifitions (Note 3) (Continued) PARAMETER CONDITIONS M TYP MAX UNIT DISPLAY DRIVER ICL0 ONLY Segment Sinking Current = 5V, Segment Voltge = 3V (Exept Pins 9 nd 20) 5 8 ma Pin 9 Only 0 6 ma Pin 20 Only 4 ma NOTES: 3. Dissiption rting ssumes devie is mounted with ll leds soldered to printed iruit ord. 4. Unless otherwise noted, speifitions pply to oth the ICL06 nd ICL0 t T A = o C, f CLOCK = 48kHz. ICL06 is tested in the iruit of Figure. ICL0 is tested in the iruit of Figure Bk plne drive is in phse with segment drive for off segment, 80 o out of phse for on segment. Frequeny is 20 times onversion rte. Averge DC omponent is less thn 50mV. 6. Not tested, gurnteed y design.. Smple Tested. Typil Applitions nd Test Ciruits 9V R R 5 R 3 D 2 C 4 C B 3 4 C R C 5 C R2 4 2 C 3 COM ICL06 A F G E D2 C2 B2 A2 F2 E2 D3 B DISPLAY F3 E3 AB POL BP C = 0.µF C 2 = 0.4µF C 3 = 0.µF C 4 = C 5 = 0.02µF R = kω R 2 = 4kΩ R 3 = R 4 = kω R 5 = MΩ DISPLAY FIGURE. ICL06 CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 5V 5V R R 5 R 3 D 2 C R C 5 C R2 4 2 C 3 C 4 DISPLAY COM ICL0 C B A F G E D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB POL GND C = 0.µF C 2 = 0.4µF C 3 = 0.µF C 4 = C 5 = 0.02µF R = kω R 2 = 4kΩ R 3 = R 4 = kω R 5 = MΩ DISPLAY FIGURE 2. ICL0 CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 3

5 Design Informtion Summry Sheet OSCILLATOR FREQUENCY f OSC = 0.45/RC C OSC > 50pF; R OSC > 50kΩ f OSC (Typ) = 48kHz OSCILLATOR PERIOD t OSC = RC/0.45 EGRATION CLOCK FREQUENCY f CLOCK = f OSC /4 EGRATION PERIOD t = 000 x (4/f OSC ) 60/50Hz REJECTION CRITERION t /t 60Hz or t lnt /t 60Hz = Integer OPTIMUM EGRATION CURRENT I = 4µA FULL SCALE ANALOG PUT VOLTAGE V lnfs (Typ) = 200mV or 2V EGRATE RESISTOR V FS R = I EGRATE CAPACITOR ( t )( I ) C = V EGRATOR OUTPUT VOLTAGE SWG ( t )( I ) V = C V MAXIMUM SWG: ( 0.5V) < V < ( 0.5V), V (Typ) = 2V DISPLAY COUNT V COUNT = 000 V REF CONVERSION CYCLE t CYC = t CL0CK x 00 t CYC = t OSC x 6,000 when f OSC = 48kHz; t CYC = 3ms MODE PUT VOLTAGE ( V) < V ln < ( 0.5V) AUTOZERO CAPACITOR 0.0µF < C AZ < µf REFERENCE CAPACITOR 0.µF < < µf V COM Bised etween Vi nd. V COM 2.8V Regultion lost when to < 6.8V If V COM is externlly pulled down to ( to )/2, the V COM iruit will turn off. ICL06 POWER SUPPLY: SGLE 9V = 9V Digitl supply is generted internlly V GND 4.5V ICL06 DISPLAY: LCD Type: Diret drive with digitl logi supply mplitude. ICL0 POWER SUPPLY: DUAL ±5.0V = 5V to GND = 5V to GND Digitl Logi nd LED driver supply to GND ICL0 DISPLAY: LED Type: NonMultiplexed Common Anode Typil Integrtor Amplifier Output Wveform ( Pin) AUTO ZERO PHASE (COUNTS) SIGNAL EGRATE PHASE FIXED 000 COUNTS DEEGRATE PHASE COUNTS TOTAL CONVERSION TIME = 00 x t CLOCK = 6,000 x t OSC 3

6 Detiled Desription Anlog Setion Figure 3 shows the Anlog Setion for the ICL06 nd ICL0. Eh mesurement yle is divided into three phses. They re () utozero (), (2) signl integrte () nd (3) deintegrte (DE). AutoZero Phse During utozero three things hppen. First, input high nd low re disonneted from the pins nd internlly shorted to nlog. Seond, the referene pitor is hrged to the referene voltge. Third, feedk loop is losed round the system to hrge the utozero pitor C AZ to ompenste for offset voltges in the uffer mplifier, integrtor, nd omprtor. Sine the omprtor is inluded in the loop, the ury is limited only y the noise of the system. In ny se, the offset referred to the input is less thn 0µV. Signl Integrte Phse During signl integrte, the utozero loop is opened, the internl short is removed, nd the internl input high nd low re onneted to the externl pins. The onverter then integrtes the differentil voltge etween nd for fixed time. This differentil voltge n e within wide ommon mode rnge: up to V from either supply. If, on the other hnd, the input signl hs no return with respet to the onverter power supply, n e tied to nlog to estlish the orret ommon mode voltge. At the end of this phse, the polrity of the integrted signl is determined. DeIntegrte Phse The finl phse is deintegrte, or referene integrte. Input low is internlly onneted to nlog nd input high is onneted ross the previously hrged referene pitor. Ciruitry within the hip ensures tht the pitor will e onneted with the orret polrity to use the integrtor output to return to zero. The time required for the output to return to zero is proportionl to the input signl. Speifilly the digitl reding displyed is: DISPLAY COUNT = 000 V. V REF Differentil Input The input n ept differentil voltges nywhere within the ommon mode rnge of the input mplifier, or speifilly from 0.5V elow the positive supply to V ove the negtive supply. In this rnge, the system hs CMRR of 86dB typil. However, re must e exerised to ssure the integrtor output does not sturte. A worst se ondition would e lrge positive ommon mode voltge with ner full sle negtive differentil input voltge. The negtive input signl drives the integrtor positive when most of its swing hs een used up y the positive ommon mode voltge. For these ritil pplitions the integrtor output swing n e redued to less thn the reommended 2V full sle swing with little loss of ury. The integrtor output n swing to within 0.3V of either supply without loss of linerity. STRAY STRAY R C AZ C ER 0µA 2.8V EGRATOR TO DIGITAL SECTION DE DE PUT HIGH 6.2V DE DE AND DE(±) N PUT LOW COMPARATOR FIGURE 3. ANALOG SECTION OF ICL06 AND ICL0 3

7 Differentil Referene The referene voltge n e generted nywhere within the power supply voltge of the onverter. The min soure of ommon mode error is rollover voltge used y the referene pitor losing or gining hrge to stry pity on its nodes. If there is lrge ommon mode voltge, the referene pitor n gin hrge (inrese voltge) when lled up to deintegrte positive signl ut lose hrge (derese voltge) when lled up to deintegrte negtive input signl. This differene in referene for positive or negtive input voltge will give rollover error. However, y seleting the referene pitor suh tht it is lrge enough in omprison to the stry pitne, this error n e held to less thn 0.5 ount worst se. (See Component Vlue Seletion.) Anlog This pin is inluded primrily to set the ommon mode voltge for ttery opertion (ICL06) or for ny system where the input signls re floting with respet to the power supply. The pin sets voltge tht is pproximtely 2.8V more negtive thn the positive supply. This is seleted to give minimum endoflife ttery voltge of out 6V. However, nlog hs some of the ttriutes of referene voltge. When the totl supply voltge is lrge enough to use the zener to regulte (>V), the voltge will hve low voltge oeffiient (0.00%/V), low output impedne ( 5Ω), nd temperture oeffiient typilly less thn 80ppm/ o C. The limittions of the on hip referene should lso e reognized, however. With the ICL0, the internl heting whih results from the LED drivers n use some degrdtion in performne. Due to their higher therml resistne, plsti prts re poorer in this respet thn ermi. The omintion of referene Temperture Coeffiient (TC), internl hip dissiption, nd pkge therml resistne n inrese noise ner full sle from µv to 80µV PP. Also the linerity in going from high dissiption ount suh s 000 (20 segments on) to low dissiption ount suh s (8 segments on) n suffer y ount or more. Devies with positive TC referene my require severl ounts to pull out of n overrnge ondition. This is euse overrnge is low dissiption mode, with the three lest signifint digits lnked. Similrly, units with negtive TC my yle etween overrnge nd nonoverrnge ount s the die lterntely hets nd ools. All these prolems re of ourse eliminted if n externl referene is used. The ICL06, with its negligile dissiption, suffers from none of these prolems. In either se, n externl referene n esily e dded, s shown in Figure 4. Anlog is lso used s the input low return during utozero nd deintegrte. If is different from nlog, ommon mode voltge exists in the system nd is tken re of y the exellent CMRR of the onverter. However, in some pplitions will e set t fixed known voltge (power supply ommon for instne). In this pplition, nlog should e tied to the sme point, thus removing the ommon mode voltge from the onverter. The sme holds true for the referene voltge. If referene n e onveniently tied to nlog, it should e sine this removes the ommon mode voltge from the referene system. Within the lc, nlog is tied to n NChnnel FET tht n sink pproximtely ma of urrent to hold the voltge 2.8V elow the positive supply (when lod is trying to pull the ommon line positive). However, there is only 0µA of soure urrent, so my esily e tied to more negtive voltge thus overriding the internl referene. V ICL06 ICL0 V ICL06 ICL0 FIGURE 4A. FIGURE 4B. FIGURE 4. USG AN EXTERNAL REFERENCE The pin serves two funtions. On the ICL06 it is oupled to the internlly generted digitl supply through 500Ω resistor. Thus it n e used s the negtive supply for externlly generted segment drivers suh s deiml points or ny other presenttion the user my wnt to inlude on the LCD disply. Figures 5 nd 6 show suh n pplition. No more thn ma lod should e pplied. ICL06 BP 20kΩ MΩ 6.8V ZENER I Z 6.8kΩ ICL8069.2V REFERENCE TO LCD DECIMAL PO TO LCD BACKPLANE FIGURE 5. SIMPLE VERTER FOR FIXED DECIMAL PO 3

8 The seond funtion is lmp test. When is pulled high (to ) ll segments will e turned on nd the disply should red 888. The pin will sink out 5mA under these onditions. CAUTION: In the lmp test mode, the segments hve onstnt DC voltge (no squrewve). This my urn the LCD disply if mintined for extended periods. ICL06 BP DECIMAL PO SELECT CD GND TO LCD DECIMAL POS FIGURE 6. EXCLUSIVE OR GATE FOR DECIMAL PO DRIVE Digitl Setion Figures nd 8 show the digitl setion for the ICL06 nd ICL0, respetively. In the ICL06, n internl digitl ground is generted from 6V Zener diode nd lrge PChnnel soure follower. This supply is mde stiff to sor the reltive lrge pitive urrents when the k plne (BP) voltge is swithed. The BP frequeny is the lok frequeny divided y 800. For three redings/se., this is 60Hz squre wve with nominl mplitude of 5V. The segments re driven t the sme frequeny nd mplitude nd re in phse with BP when OFF, ut out of phse when ON. In ll ses negligile DC voltge exists ross the segments. Figure 8 is the Digitl Setion of the ICL0. It is identil to the ICL06 exept tht the regulted supply nd k plne drive hve een eliminted nd the segment drive hs een inresed from 2mA to 8mA, typil for instrument size ommon node LED displys. Sine the 000 output (pin 9) must sink urrent from two LED segments, it hs twie the drive pility or 6mA. In oth devies, the polrity indition is on for negtive nlog inputs. If nd re reversed, this indition n e reversed lso, if desired. e f g d e f g d e f g d BACKPLANE LCD PHASE DRIVER TYPICAL OUTPUT 0.5mA 2mA OUTPUT ERNAL DIGITAL GROUND DECODE LATCH DECODE DECODE 000 s 00 s 0 s s COUNTER COUNTER COUNTER COUNTER 200 THREE VERTERS ONE VERTER SHOWN FOR CLARITY TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK 4 ERNAL DIGITAL GROUND LOGIC CONTROL V TH = V 6.2V 500Ω FIGURE. ICL06 DIGITAL SECTION 3

9 e f g d e f g d e f g d DECODE DECODE DECODE TYPICAL OUTPUT LATCH 0.5mA 8mA DIGITAL GROUND TO THREE VERTERS ONE VERTER SHOWN FOR CLARITY TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK 000 s 00 s 0 s s COUNTER COUNTER COUNTER COUNTER 4 LOGIC CONTROL 500Ω DIGITAL GROUND FIGURE 8. ICL0 DIGITAL SECTION System Timing Figure 9 shows the loking rrngement used in the ICL06 nd ICL0. Two si loking rrngements n e used:. Figure 9A. An externl osilltor onneted to pin. 2. Figure 9B. An RC osilltor using ll three pins. The osilltor frequeny is divided y four efore it loks the dede ounters. It is then further divided to form the three onvertyle phses. These re signl integrte (000 ounts), referene deintegrte (0 to 2000 ounts) nd utozero (000 to 00 ounts). For signls less thn full sle, utozero gets the unused portion of referene deintegrte. This mkes omplete mesure yle of 4,000 ounts (6,000 lok pulses) independent of input voltge. For three redings/seond, n osilltor frequeny of 48kHz would e used. To hieve mximum rejetion of 60Hz pikup, the signl integrte yle should e multiple of 60Hz. Osilltor frequenies of 0kHz, 20kHz, 80kHz, 60kHz, 48kHz, khz, / 3 khz, et. should e seleted. For 50Hz rejetion, Osilltor frequenies of 200kHz, 00kHz, 66 2 / 3 khz, 50kHz, khz, et. would e suitle. Note tht khz (2.5 redings/seond) will rejet oth 50Hz nd 60Hz (lso 0Hz nd 4Hz). ERNAL TO PART GND ICL0 ICL06 FIGURE 9A. ERNAL TO PART R C FIGURE 9B. 4 CLOCK 4 CLOCK RC OSCILLATOR FIGURE 9. CLOCK CIRCUITS 3

10 Component Vlue Seletion Integrting Resistor Both the uffer mplifier nd the integrtor hve lss A output stge with 00µA of quiesent urrent. They n supply 4µA of drive urrent with negligile nonlinerity. The integrting resistor should e lrge enough to remin in this very liner region over the input voltge rnge, ut smll enough tht undue lekge requirements re not pled on the PC ord. For 2V full sle, 40kΩ is ner optimum nd similrly 4kΩ for 200mV sle. Integrting Cpitor The integrting pitor should e seleted to give the mximum voltge swing tht ensures tolerne uildup will not sturte the integrtor swing (pproximtely. 0.3V from either supply). In the ICL06 or the ICL0, when the nlog is used s referene, nominl 2V fullsle integrtor swing is fine. For the ICL0 with 5V supplies nd nlog tied to supply ground, ±3.5V to 4V swing is nominl. For three redings/seond (48kHz lok) nominl vlues for C lnt re 0.µF nd 0.0µF, respetively. Of ourse, if different osilltor frequenies re used, these vlues should e hnged in inverse proportion to mintin the sme output swing. An dditionl requirement of the integrting pitor is tht it must hve low dieletri sorption to prevent rollover errors. While other types of pitors re dequte for this pplition, polypropylene pitors give undetetle errors t resonle ost. AutoZero Cpitor The size of the utozero pitor hs some influene on the noise of the system. For 200mV full sle where noise is very importnt, 0.4µF pitor is reommended. On the 2V sle, 0.04µF pitor inreses the speed of reovery from overlod nd is dequte for noise on this sle. Referene Cpitor A 0.µF pitor gives good results in most pplitions. However, where lrge ommon mode voltge exists (i.e., the pin is not t nlog ) nd 200mV sle is used, lrger vlue is required to prevent rollover error. Generlly µf will hold the rollover error to 0.5 ount in this instne. Osilltor Components For ll rnges of frequeny resistor is reommended nd the pitor is seleted from the eqution: f = 0.45 For 48kHz Clok (3 Redings/se), RC C =. Referene Voltge The nlog input required to generte full sle output (2000 ounts) is: V ln = 2V REF. Thus, for the 200mV nd 2V sle, V REF should equl 00mV nd V, respetively. However, in mny pplitions where the A/D is onneted to trnsduer, there will exist sle ftor other thn unity etween the input voltge nd the digitl reding. For instne, in weighing system, the designer might like to hve full sle reding when the voltge from the trnsduer is 0.662V. Insted of dividing the input down to 200mV, the designer should use the input voltge diretly nd selet V REF = 0.V. Suitle vlues for integrting resistor nd pitor would e 20kΩ nd 0.µF. This mkes the system slightly quieter nd lso voids divider network on the input. The ICL0 with ±5V supplies n ept input signls up to ±4V. Another dvntge of this system ours when digitl reding of zero is desired for V 0. Temperture nd weighing systems with vrile fre re exmples. This offset reding n e onveniently generted y onneting the voltge trnsduer etween HI nd nd the vrile (or fixed) offset voltge etween nd. ICL0 Power Supplies The ICL0 is designed to work from ±5V supplies. However, if negtive supply is not ville, it n e generted from the lok output with 2 diodes, 2 pitors, nd n inexpensive lc. Figure 0 shows this pplition. See ICL660 dt sheet for n lterntive. In ft, in seleted pplitions no negtive supply is required. The onditions to use single 5V supply re:. The input signl n e referened to the enter of the ommon mode rnge of the onverter. 2. The signl is less thn ±.5V. 3. An externl referene is used. ICL0 GND = 3.3V CD µf 94 0 µf FIGURE 0. GENERATG NEGATIVE SUPPLY FROM 5V 3

11 Typil Applitions The ICL06 nd ICL0 my e used in wide vriety of onfigurtions. The iruits whih follow show some of the possiilities, nd serve to illustrte the exeptionl verstility of these A/D onverters. The following pplition notes ontin very useful informtion on understnding nd pplying this prt nd re ville from Hrris Semiondutor. Applition Notes NOTE # DESCRIPTION AnswerFAX DOC. # AN06 Seleting A/D Converters 906 AN0 The Integrting A/D Converter 90 AN08 Do s nd Don ts of Applying A/D Converters 908 AN0 Low Cost Digitl Pnel Meter Designs 90 AN0 AN046 AN052 Understnding the AutoZero nd Common Mode Performne of the ICL//9 Fmily Building BtteryOperted Auto Rnging DVM with the ICL06 Tips for Using Single Chip 3 / 2 Digit A/D Converters Typil Applitions SET V REF = 00mV SET V REF = 00mV 0.µF kω kω 0.µF kω kω 5V 0.4µF 4kΩ MΩ 0.0µF 9V 0.4µF 4kΩ MΩ 0.0µF V 0.µF V 0.µF 5V BP TO BACKPLANE GND Vlues shown re for 200mV full sle, 3 redings/se., floting supply voltge (9V ttery). FIGURE. ICL06 USG THE ERNAL REFERENCE Vlues shown re for 200mV full sle, 3 redings/se. my e tied to either for inputs floting with respet to supplies, or GND for single ended inputs. (See disussion under Anlog.) FIGURE 2. ICL0 USG THE ERNAL REFERENCE 3

12 Typil Applitions (Continued) SET V REF = 00mV SET V REF = 00mV 0.µF kω 0kΩ 0kΩ.2V (ICL8069) 0.µF kω 5V 6.8V 0.4µF 4kΩ MΩ 0.0µF 0.4µF 4kΩ MΩ 0.0µF 0.µF V V 0.µF 5V GND GND is tied to supply estlishing the orret ommon mode voltge. If is not shorted to GND, the input voltge my flot with respet to the power supply nd ts s preregultor for the referene. If is shorted to GND, the input is single ended (referred to supply GND) nd the preregultor is overridden. FIGURE 3. ICL0 WITH AN EXTERNAL BANDGAP REFERENCE (.2V TYPE) Sine low TC zeners hve rekdown voltges ~ 6.8V, diode must e pled ross the totl supply (0V). As in the se of Figure 4, my e tied to either or GND. FIGURE 4. ICL0 WITH ZENER DIODE REFERENCE V 0.µF 0.04µF 0.µF 40kΩ kω SET V REF = 00mV kω MΩ 0.0µF V 0.µF 0.4µF 0.µF 4kΩ kω SET V REF = 00mV 0kΩ MΩ 0.0µF 5kΩ.2V (ICL8069) 5V GND BP/GND An externl referene must e used in this pplition, sine the voltge etween nd is insuffiient for orret opertion of the internl referene. FIGURE 5. ICL06 AND ICL0: RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE FIGURE 6. ICL0 OPERATED FROM SGLE 5V 3

13 Typil Applitions (Continued) V GND 0.µF 0.µF 0.4µF 4kΩ The resistor vlues within the ridge re determined y the desired sensitivity. FIGURE. ICL0 MEASUREG RATIOMETRIC VALUES OF QUAD LOAD CELL O /RANGE U /RANGE CD OR 4C0 TO LOGIC V CC CD 3 FIGURE 9. CIRCUIT FOR DEVELOPG UNDERRANGE AND OVERRANGE SIGNAL FROM ICL06 OUTPUTS D C B A F G E D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP TO LOGIC GND SCALE FACTOR ADJUST kω C MΩ REF 0.µF 0kΩ ZERO SILICON NPN 0.0µF ADJUST MPS 04 OR 0.4µF SIMILAR 4kΩ 9V V 0.µF BP TO BACKPLANE A silion diodeonneted trnsistor hs temperture oeffiient of out 2mV/ o C. Clirtion is hieved y pling the sensing trnsistor in ie wter nd djusting the zeroing potentiometer for reding. The sensor should then e pled in oiling wter nd the sleftor potentiometer djusted for 00.0 reding. FIGURE 8. ICL06 USED AS A DIGITAL CENTIGRADE THERMOMETER O /RANGE U /RANGE CD OR 4C0 TO LOGIC V CC 2kΩ The LM9 is required to ensure logi omptiility with hevy disply loding. 5V 2 D 3 C 4 B 5 A 6 F G 8 E 9 D2 0 C2 B2 2 A2 3 F2 4 E2 5 D3 6 B3 F3 8 E3 9 AB4 20 POL kω BP FIGURE 20. CIRCUIT FOR DEVELOPG UNDERRANGE AND OVERRANGE SIGNALS FROM ICL0 OUTPUT 3

14 Typil Applitions (Continued) 0.µF kω 0µF kω SCALE FACTOR ADJUST (V REF = 00mV FOR AC TO RMS) 40kΩ N94 5µF CA 2.2MΩ AC 0.4µF 4kΩ 0.µF 0µF 9V µf 4.3kΩ 0kΩ µf (FOR OPTIMUM BANDWIDTH) 0kΩ µf 0.µF BP TO BACKPLANE Test is used s ommonmode referene level to ensure omptiility with most op mps. FIGURE. AC TO DC CONVERTER WITH ICL06 5V ICL0 DM Ω LED S Ω Ω FIGURE. DISPLAY ERG FOR CREASED DRIVE CURRENT 3