Array chip resistors size ARC241/ARC242 ARV241/ARV242

Transcription

1 Arry chip resistors FEATURES sized resistors in one 1206-sized pckge Reduced reel exchnge time Low ssembly costs Reduced PCB re Reduced size of finl equipment Higher component nd equipment relibility. APPLICATIONS Cmcorders Hnd held mesuring equipment Cr telephones Computers Portble rdio, CD nd cssette plyers. DESCRIPTION The resistors re constructed on high grde cermic body (luminium oxide). Internl metl electrodes re dded t ech end nd connected by resistive pste which is pplied to the top surfce of the substrte. The composition of the pste is djusted to give the pproximte resistnce required nd the vlue is trimmed to within tolernce, by lser cutting of this resistive lyer. The resistive lyer is covered with protective coting nd printed with the resistnce vlue. Finlly, externl end termintions re dded. For ese of soldering the outer lyer of these end termintions is led-tin lloy. hndbook, 2 columns R1 R2 R3 R4 CCA862 R1 = R2 = R3 = R4. For dimensions see Fig.3 nd Tble 3. Fig.1 Equivlent circuit digrm. QUICK REFERENCE DATA Resistnce rnge R-Arry overview DESCRIPTION VALUE 10 Ω to 1 MΩ Resistnce tolernce nd E-series ±5%; E24 series ±1%; E96 series ±1%; E24/E96 series Temperture coefficient ± /K ± /K ± /K Absolute mximum dissiption per resistive element t T mb =70 C Mximum permissible voltge W 50 V (DC or RMS) Climtic ctegory ( 60068) 55/155/56 Bsic specifiction TYPE TERMINATION TECHNOLOGY SIZE TOLERANCE (%) ARC241 concve ARC242 concve ARV241 convex ARV242 convex

2 Arry chip resistors FUNCTIONAL DESCRIPTION Product chrcteriztion Stndrd vlues of nominl resistnce re tken from the E24 or E96 series for resistors with tolernce of ±5% or ±1%. The vlues of the E24/E96 series re in ccordnce with publiction Limiting vlues DERATING The power tht the resistor cn dissipte depends on the operting mbient temperture; see Fig.2. hndbook, 4 columns P mx (%P rted ) 100 CCB412 TYPE LIMITING VOLTA GE (1) (V) LIMITING POWER (W) 50 ARC241 ARC242 ARV241 ARV T mb ( C) Note 1. This is the mximum voltge tht my be continuously pplied to the resistor element, see publiction Fig.2 Mximum dissiption (P mx ) in percentge of rted power s function of the operting mbient temperture (T mb ). 3

3 Arry chip resistors MECHANICAL DATA Mss per 100 units Mrking TYPE MASS (g) ARC ARC ARV ARV All resistors within the E24 series re mrked with 3-digit code nd 4-digit code for resistors of the E96 series, on the protective cot to designte the nominl resistnce vlue. PACKAGE MARKING The pckging is lso mrked nd includes resistnce vlue, tolernce, ctlogue number, quntity, production period, btch number nd source code. Outlines hndbook, 4 columns B A P L B C P L A T W 3-DIGIT MARKING For vlues up to 91 Ω the R is used s deciml point. For vlues of 100 Ω or greter the first 2 digits pply to the resistnce vlue nd the third indictes the number of zeros to follow. G C convex termintion G E C concve termintion CCA863 Exmple 12R MARKING 4-DIGIT MARKING For vlues up to 976 Ω the R is used s deciml point. For vlues of 1 K or greter the first 3 digits pply to the resistnce vlue nd the fourth indictes the number of zeros to follow. Exmple RESISTANCE 12 Ω kω 000 jumper 12R0 MARKING RESISTANCE 12 Ω kω Dimensions in mm. For dimensions see Tble 3. Fig.3 Outlines. Tble 3 Physicl dimensions; see Fig.3 SYMBOL ARC241/242 ARV241 ARV242 VALUE TOL. VALUE TOL. VALUE TOL. UNIT L / ± ±0.15 mm W / ± ±0.15 mm T 0.60 ± ± ±0.10 mm A 0.60 ± ± ±0.05 mm B 0.35 ± ± ±0.20 mm P 0.80 ± ± ±0.15 mm E 0.50 ±0.15 mm G 0.50 ± ± ±0.15 mm C 0.10 min min ±0.15 mm 4

4 S AND REQUIREMENTS Essentilly ll tests re crried out in ccordnce with the schedule of publiction , ctegory LCT/UCT/56 (rted temperture rnge: Lower Ctegory Temperture, Upper Ctegory Temperture; dmp het, long term, 56 dys). The testing lso covers the requirements specified by EIA nd EIAJ. The tests re crried out in ccordnce with publiction 60068, Recommended bsic climtic nd mechnicl robustness testing procedure for electronic components nd under stndrd tmospheric conditions ccording to , subcluse 5.3. Unless otherwise specified the following vlues pply: Temperture: 15 C to 35 C Reltive humidity: 25% to 75% Air pressure: 86 kp to 106 kp (860 mbr to 1060 mbr). In Tble 4 the tests nd requirements re listed with reference to the relevnt cluses of publictions nd ; short description of the test procedure is lso given. In some instnces devitions from the recommendtions were necessry for our method of specifying. All soldering tests re performed with mildly ctivted flux. Arry chip resistors Tble 4 Test procedures nd requirements CLAUSE METHOD PROCEDURE Tests in ccordnce with the schedule of publiction REQUIREMENTS visul exmintion no holes; clen surfce; dimensions (outline; see Fig.3) guge (mm) see Tble resistnce pplied voltge (+0/ 10%): R R nom : 10 Ω R < 100 Ω: 0.3 V mx. ±5% (Tb) resistnce to soldering het (X) component solvent resistnce 100 Ω R<1kΩ: 1V 1kΩ R < 10 kω: 3V 10 kω R < 100 kω: 10V 100 kω R<1MΩ: 25V R 1MΩ: 50V unmounted chips; 10 ±1 s; 260 ±5 C isopropyl lcohol or H 2 O followed by brushing in ccordnce with MIL 202 F (T) solderbility unmounted chips completely immersed for 2 ±0.5 s in solder bth t 235 ±2 C R R nom : mx. ±1% ±(0.5% Ω) good tinning ( 95% covered); R R nom : mx. ±5%

5 CLAUSE METHOD 4.7 voltge proof on insultion mximum voltge (RMS) during 1 minute, metl block method 4.13 short time overlod room temperture; P = 6.25 P n ; 5 s (V 2 V mx ) 4.33 bending resistors mounted on 90 mm glss epoxy resin PCB (FR4), bending: 5 mm (N) rpid chnge of temperture (C) dmp het (stedy stte) 30 minutes t LCT nd 30 minutes t UCT; 5 cycles 56 dys; 40 ±2 C; 93 +2/ 3% RH; loded with 0.01 P n endurnce / 0 hours; 70 ±2 C; loded with P n or V mx ; 1.5 hours on nd 0.5 hours off (B) endurnce t upper ctegory temperture temperture coefficient PROCEDURE no brekdown or flshover ±(0.5% Ω) ±(0.5% Ω) ±(3% +0.1 Ω) / 0 hours; no lod REQUIREMENTS t 20/LCT/20 C nd 20/UCT/20 C ± /K ± /K ± /K Arry chip resistors Other tests in ccordnce with cluses nd test method (T) solderbility (fter geing) insultion resistnce 8 hours stem or 16 hours 155 C; unmounted chips completely immersed for 2 ±0.5 s in solder bth t 235 ±2 C voltge (DC) fter 1 minute, metl block method: 10 V 4.12 noise publiction (mesured with Quntech-equipment): R 100 Ω good tinning ( 95% covered); no dmge R ins min.: 10 3 MΩ mx µv/v ( 10 db) 100 Ω <R 1kΩ mx. 1 µv/v (0 db) 1kΩ <R 10 kω mx. 3 µv/v (9.54 db) 10 kω <R 100 kω mx. 6 µv/v (15.56 db) 100 kω <R 1MΩ mx. 10 µv/v (20 db)

6 CLAUSE Other pplicble tests (JIS) C EIA EIA/IS METHOD endurnce (under dmp nd lod) / 0 hours; 40 ±2 C; 93 +2/ 3% RH; loded with P n or V mx ; 1.5 hours on nd 0.5 hours off ±(3% +0.1 Ω) leching unmounted chips; 60 ±1 s; 260 ±5 C good tinning; no leching lod humidity PROCEDURE / 0 hours; 85 ±2 C; 85 ±5% RH; loded with 0.01 P n or V mx REQUIREMENTS Arry chip resistors 7