Array E System Grounding Philosophy. This ATM briefly describes modifications to system grounding

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1 Array E System Grounding Philosophy NO. ATM-962 PAGE 1 REV. NO. OF 14 DATE This ATM briefly describes modifications to system grounding philosophy from those applied on previous flights and provides system component and experiment grounding details. Prepared by: Approved by: 'lj~:rl~ D. Fithian"

2 'MO. ATM-962 R!V. MO. Array E System Grounding Philosophy PAGE 2 OF DATE This ATM is written to document the ALSEP Array E grounding philosophy which has been modified from that employed in previous ALSEP systems. The grounding philosophy employed in flights A thru Dis documented in ATM and 530. Figures 1 thru 11 provide the details of the Array E component central station and experiment grounding arrangements. The most significant changes in grounding philosophy from that of previous systems involves the use of the central station thermal plate as a ground plane Previous systems employed a single point ground located in the PDU. n Array E the ground plane approach which essentially enlarges the magnitude of the single point ground is used to minimize inductance of paths between components. nter-component inductance must be minimized in Array E because low power TTL logic capable of faster switching rates than previous employed logic is used extensively in the redesigned command decoder data processor and PCU/PDU. Reducing inductance thus reduces L{di/dt) noise generated by logic switching coupled from circuit to circuit in the grounds. nductive paths in the central station are minimized by employing ground planes on component PC boards and by using the component mounting structure and base plate as an electrical signal return path. The thermal plate therefore provides the remaining portion of the signal return path. This concept minimizes inductance by employing the largest physical structures as a conducting ground path. To successfully implement this concept the component mounting structure base and the thermal plate surface must be designed to provide good electrical continuity and a low impedance path at high frequencies. A design goal of less than 20 millivolts Xc or XL drop and less than 20 milliohm resistance between two signal points has been established. The thermal plate 2.nd new components will employ gold mounting interfaces to optimize electrical <::cntir;.uity between mechanical interfaces. Thermal grease will not be empljy'~d : :t is detri~ental to electrical characteristics. The entire thermal plate wle ':1e gold plated to provic~e a low ~mpedance path between components. The thermal plate ground plane provides three means for completing ground connections. a. Component mechanical mounting interface. b. Terminal board mounting interface c. Two ground studs.

3 '= :. ;.;:::.: ;"'" _~.. era apace Array E System Grounding Philosophy MO. ATM-962 PAGE 3 REV. MO. OF DATE New component designs will employ method (a) but will carry a "safety" ground wire thru the component connector for test purposes. Previously designed components have been designed to operate on an anodized thermal plate Their grounds will therefore be connected thru the central station harness to the thermal plate ground studs (method c). The RTG PCU/PDU and experiment grounds will use method b) to complete ground connections to the thermal plate ground plane. The use of multiple grounding techniques on the thermal plate does not violate the single point ground philosophy. This is possible because the impedance of signal return paths will be maintained below a level which can cause significant noise. Figures 1 thru 9 depict the component grounding arrangements. The following comments apply: a. Capacitors are depicted in signal lines to show DC isolation. b nternal dashed lines indicated component chassis which may be isolated from mounting surface chassis. c A chassis ground symbol depicts the conductive component/ experiment mounting surface. d. To minimize capacitive pickup the LEAM experiment may not use a separate chassis ground. The grounding arrangement employed will be dependent on development testing. System grounding arrangements are depicted in Figures 10 and 11. The following comments apply: a. Parallel alternate signal return conduc'.>::>rs will be used in the experiment flat cab'.es in l".eu of the previousl;.r employed alternate shield conductors. Th[s ml)dirication wi11 reduce crosstalk on the timing and control line~. b. The receiver mounting surface is not compatible with the gold finish and will thus be isolated from the thermal plate by an anodized aluminum shim less than 1 32 inch thick. c. The PSE CSE will be iso:.ated from the thermal plate in a manner similar to the receiver because its mounting surface is incompatible with gold.

4 ATM-962 Page fs( REG T SPLT PHASE DATA LOW FREQ RF O ( D PLEXER SWTCH. PWR S G & TM 1_-] N~ EM Fl LfER *. SOME TM CHANNELS MAY BE UNFLTERED ALSEP TRANSMTTER - TELEDYNE FGURE

5 A 'T'- ""62 P.. +29V ~ TM TM LOW FREQ )o r- SPLT PHASEj ~ 1 SPLiT PHASE NPUT -~ 1 ~ 1 s G & D'l''~' l.q JH( --~-~'"'.. ~..-. ~-~~~-- 06 $-...J 1 ~ CHASSS -~- : +29V CURRENT 1 SENSOR RF H t ~ DPLEXE H L j ~ SWTCH :> ll/ ALSEP TRANSM TER - BxA FGURE P-Wl2 ~ - 'i

6 ALSE P AKf?..AY E RECEVER P 'T1\.f:._q6z V PWR AUDO OUTPUT TM DC ACT. FL TM?. <":"f."l ~..._~.. r ~--- LOW FREQ RF : ( l < D p LEX E R FLTER FEED TM S G. PWR. &TM i i ("f) N $ n.. 0.-f ("''\ ' 00 CHASSS L FGURE EM FLTER

7 ATM-o' Page' ALSEP ARRAY E D PLEXER SWTCH & FLTER +12V + 12V TRANS A NPUT TRANS 8 NPUT > l L MAG sw D PLEXER ll---+-l - H-J... FLTER L~ --tb....j D PLEXER SWTCH ).' ANTENNA -<f- ~ t :~ H ~ ~~~~:~: SWTCH D PLEXER FLTER FGURE P-Wl5

8 A TM- 9f-... Page 8 NPUT PWR _::l2v 5V ANALOG NTERFACE s DGTAL ~ NTERFACE ) PWR&SG (SAFETY) r_ T ANALOG f - l DGTAL T ~-err ALSEP ARRAY E COMMAND DECODER & DATA PROCESSOR FGURE P-W-22

9 Arl'M- 962 Page 9 ALSEP ARRAY E PCU/PDU PDU PCU RELAY RTG NPUT DC"7DC '- DR VERS +16V +5V CONVERTER- CKT BKRS & FUSES PWR ~n -_._..._ ~ (SAFETY) +29V EX P R MENTS & TR ANSMTTER ~l2v 5V PWR (SAFETY).-.: ! W6 FGURE 6 ").

10 A 'llvi-. '.. Page EXPERMENT GROUND lng- TYPCAL FOR LMS LSG HFE AND PSE +29V PWR +29V PWR T - c --& CMD ANALOG DGTAL SGNAL CHASSS DC-DC CONVERTER... ~~~- --'... EXPERMENT POWER --~--- _.. EXPERMENT ELECTRONCS EXP PWR PSE SENSOR SENSOR Sl G CHASSS RT N : PSE CSE T/ ONLY 8310P-Wl7 FGURE 7

11 EXPERMENT l JND NG - LEAM ATM-96.2 Page J +29V PWR DC-DC +29V PWR CONVERTER TC & EXPERMENT CMD ELECTRON lcs ~ ANALOG DGTAL DATA SGNAL& 1 CHASSSi-J r EXP PWR ) 8310P-Wl8 ~. FGURE 8

12 ATM-962 Page 12 EXPERMENT GROUND lng- LSPE +29V PWR +29V PWR DC-DC CONVERTER _ TC& CMD - ''""...;.r'"'' "- """~~c.. C/S ANALOG --"''"""'' -=-="'"''"" ;;.~!.;-"._ >X"' ~ ~.w ~ ' LOW FREQ -if-+ RF... ~J ANTENNA FEED DGTAL.. DATA EXP PWR SGNAL & CHASSS a-.> r-:-f 5 -- n ('("\ 00 -'l'//~ fw FGURE 9

13 ATM-q6z Pagf CS THERMAL PLATE GROUND PLANE TYPCAL EXPERMENT NOTE: PWR & SGNAL S ARE PARALLEL CONDUCTORS N FLAT CABLE PWR S G CHASSS TB GROUND PWR ' TRANSMTTERS~~.. ~~ -- }kchasss PWR COMMAND DECODER STUD RECEVER DPLEXER S\V TCH & FLTER PCU PCU ~m.jy DATA l PROCESSOR ALSEP ARRAY E SYSTEM GROUNDNG FGURE P-W20 ) '. ; #.. 1

14 ATM-Of-~... Pag( ) 14 ALSEP ARRAY E EXPERMENT GROUNDNG ) ~ js-50 FOOT FLAT CABLE CS THERMAL PLATE r- TB GROUND GROUND PLAN E PWR RlN LEAM SGNAL & CHASSS PWR SGNAL LSPE CHA SSS ELECTRONCS PWR LMS SGNAL (f.- D-lj CHASSS r- ~ n.!dfrhtal SGNAU HONES t J r PWR l LSG HF ~..L:'? 290 FEET SHELDED TWSTED PAR SGNAL CHASSS PWR SGNAL CHASSS NOTE: POWER & SGNAL S ARE PARALLEL CONDUCTORS N FLAT CABLE FGURE 11 dn TB GROUND PWR PSE SGNAL CHASSS ELECTRONCS (OPTONAL) ~ 8310P-W21 wo- ~-;

- - v INCLUDING THE HEAT FLOW EXPERIMENT PAGI

- - v INCLUDING THE HEAT FLOW EXPERIMENT PAGI t '\ ( J!_ AA f"\ f I,:( '(.), L."'v