United States Patent (19)

Transcription

1 United State Patent (19) Holloway (54) TWO-STAGE HIGH RESOLUTION DIGITAL-TO-ANALOG CONVERTER (75) Inventor: Peter R. Holloway, Andover, Ma. 73) Aignee: Analog Device, Incorporated, Norwood, Ma. 21) Appl. No.: 581, Filed: Feb. 17, ) Int. Cl.... H03K 13/02 52 U.S. C /347 DA 58 Field of Search /347 AD; 357/51 (56) Reference Cited U.S. PATENT DOCUMENTS 3,997,892 12/1976 Suet /347 DA 4,338,591 7/1982 Tuthill /347 DA 4,447,747 5/1984 La Potin /51 4,491,825 1/1985 Tuthill /347 DA FOREIGN PATENT DOCUMENTS /1975 Fed. Rep. of Germany /347 DA OTHER PUBLICATIONS Hamade et al., A Single Chip 8 Bit A/D Converter', 11 Patent Number: 45) Date of Patent: 4,543,560 Sep. 24, /19/76, IEEE International Solid State Circuit Con ference, Diget of Technical Paper, pp Hamade, "A Single Chip All-MOS 8 Bit A/D Con verter', Dec. 1978, IEEE Journal of Solid State Cir cuit, vol. SC-13, No. 6, pp Primary Examiner-William M. Shoop, Jr. Aitant Examiner-Sharon Logan Attorney, Agent, or Firm-Parmelee, Bollinger & Bramblett 57 ABSTRACT A 16-bit D/A converter formed on a ingle monolithic IC chip and having two cacaded tage each including a 256-R reitor-tring DAC. The firt tage employ a witch elector ytem capable of electing any two adjacent tap of the reitor tring to produce a egment voltage to be applied acro the econd tage reitor tring. The reitor tring are formed a elongate thin film trip configured a a ingle, unbent body having integral voltage tap nipple evenly-paced along both ide of the trip. Buffer amplifier between the ca caded tage incorporate NMOS and PMOS-cacoded bipolar current ource in a non-epitaxial tructure on a P-type ubtrate. 13 Claim, 9 Drawing Figure 47t. Aw

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8 1. TWO-STAGE HIGH RESOLUTION DIGITAL-TO-ANALOG CONVERTER BACKGROUND OF THE INVENTION 1. Field of the Invention Thi invention relate to digital-to-analog converter of the egment type formed on a ingle monolithic IC chip. More particularly, thi invention relate to uch converter having two cacaded tage, the firt tage reolving a et of higher-order bit into a correponding analog ignal, and the econd tage reolving the re maining, lower-order bit to produce a econd analog ignal to be combined with the firt tage analog ignal. 2. Decription of the Prior Art Suet U.S. Pat. No. 3,997,892 how a two-tage cacaded converter wherein the firt tage include a reitor-tring DAC (D/A converter) to produce a firt voltage correponding to a et of higher-order input bit. The econd converter tage i another reitor tring DAC arranged to produce a econd voltage cor reponding to a et of lower-order bit. The voltage acro a elected reitor of the firt tage i applied to the end of the reitor tring of the econd tage, o that the latter tage produce an output effectively interpo lating the elected firt-tage egment voltage in accor dance with the lower-order bit. Converter uch a hown by Suet have an impor tant advantage in that they are inherently capable of monotonic performance. However, the Suet con verter i practical only for ue in relatively low-reolu tion application. Thi i becaue the elector witch ytem ued to make connection to the reitor tring would become prohibitively large and complex for a high-reolution monolithic converter uch a one capa ble of reolving a 16-bit input word. For example, the firt tage of uch a converter typically would have a 256-R reitor tring. The complexity of the witch elector ytem for uch a reitor tring epecially re ult from the fact that it mut be able to elect any pair of adjacent voltage tap of the tring to produce the egment voltage for the econd tage converter. The prior art technique ued in cacaded egment converter uffer from till other diadvantage when applied to high-reolution, high performance device developed on a ingle IC chip. For example, prior rei tor-tring arrangement have not been found uitable for achieving atifactory linearity and other deired performance characteritic in a 16-bit converter. SUMMARY OF THE INVENTION In accordance with one apect of the invention, a novel elector witch tree tructure i provided for acceing the voltage tap point of a reitor tring hav ing 256 reitor. Thi tree tructure make it poible to ue common control line for mot of the two et of witche on oppoite ide of the reitor tring, and leading repectively to alternate voltage tap of the reitor tring. The election of adjacent pair of tap i thereby effected with a minimum of additional circuitry required to control the two et of witche. The reitor tring of the preferred embodiment i provided a a ingle-bodied thin film reitor in the form of a continuou homogeneou trip of reitive material (Silicon Chromium) of elongate rectangular hape, hav ing no conductive layer contact interpoed between adjacent reitor. The dicloed tructure provide 4,543, improved untrimmed reitor linearity a a reult of the configuration of thin film. Still other object, apect and advantage of the invention will in part be pointed out in, and in part apparent from, the following decription of a preferred embodiment conidered together with the accompany ing drawing. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 i a implified diagrammatic howing of a converter in accordance with thi invention; FIG. 2 i a diagram howing a portion of the voltage tap elector witche; FIG. 3 preent a table partially howing the develop ment of the ignal for the witch control line for the witch portion hown in FIG. 2. FIG. 4 how the chip layout of the reitor tring; FIG. 5 how a portion of the reitor tring con nected to the aociated witche; FIG. 6 i a circuit diagram of a preferred amplifier; and FIG. 7A, 7B and 7C how detail of N-type and P type MOS-cacoded bipolar current ource formed with a non-epitaxial proce. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Referring firt to FIG. 1, which i a implified dia gram of the preferred 16-bit D/A converter, it will be een that the device include two cacaded tage gener ally indicated at 20 and 22. Each tage comprie a 256-R reitor tring 24, 26. Logic circuitry 28, 30 of known type of deign i ued to develop the witch control ignal for the repective tage. Buffer amplifi er A1, A2 are employed to direct the firt-tage egment output voltage to the econd tage where it i applied to the end of the reitor tring 26. The firt tage reitor tring 24 receive a voltage hown a --VREF and -VREF. That voltage i divided by the reitor tring into 256 nominally equal voltage egment. Any two adjacent voltage tap are elected in accordance with the upper byte (8bit) of the 16-bit input word. Amplifier A1 tranfer the voltage of one elected tap (e.g. tap 251) to the top of the econd tage. Amplifier A2 tranfer the voltage from an immediately adjacent tap (e.g. tap 252) to the bottom of the econd tage. The output amplifier A3 produce a ignal lin early interpolating the voltage drop between tap 251 and 252, weighted by the lower byte of the 16-bit input word. The next code might, for example, lie between tap 252 and 253, in which cae the witching path repre ented by the witch at tap 251 open up, and a new path i developed by cloure of the witch at tap 253. With the hift of witche jut decribed, it will een that the polarity of the voltage upplied to the econd tage converter i revered. Thi reveral occur at every other adjacent reitor egment and mut be corrected in the econd tage to preerve monotonic behavior. Variou known reveral-correction arrangement can be employed, and thu thi apect will not be further decribed herein. Thi feature of the elector witch eliminate differential non-linearity error reulting from diimilar VOFFSETS of amplifier A1 and A2. Leaving the ame amplifier in a given tap' path for both the pedetal of a lower egment and the floor of the adjacent upper egment avoid any modification of the 256 major carry, even at reduced-cale factor.

9 4,543,560 3 Referring now to detail of the elector witch ytem hown in FIG. 2 (repreenting only a mall portion of the reitor tring), it will be een that the ytem com prie two multi-rank group of elector witche gener ally indicated at 32, 34, on oppoite ide of the reitor 5 tring 24. Each group in thi embodiment include four rank, o that the voltage of every reitor tap pae through four erie-connected witche (in thi cae, NMOS FETS) before reaching an amplifier. The witching cheme, a outlined above, require that, for a 10 monotonically increaing input, the witchover from one reitor egment to the next occur by having one contact "leapfrog' around the other tap, i.e. by having a ingle contact move two tep, rather than by having two contact lide together one tep each. The elector tree are arranged uch that their phyi cal connection to the reitor-tring do not exactly over-lap, but, intead, are interleaved. Each tap going along the reitor body alternate between the left ide and the right ide. In thi way, when both elector are 20 given the ame addre, and are phyically identical in their configuration, they connect not to the ame point, but intead to two adjacent point. If one elector i than augmented by a leat-ignificant-bit (by a count of one), that elector will move to the tap immediately on the 25 other ide of the quiecent elector' tap poition. In more detail now, the firt rank 36 of the left-hand elector witche are organized in witch pair 38A, 38B,... 44A, 44B. The firt rank 50 on the right-hand ide include correponding pair 52A, 52B,... 58A, 30 58B. In conidering the relationhip between thee witch pair and the reitor tring 24, it i convenient to view the reitor tring a being ub-divided into ucce ive group of four erie-reitor each, a indicated at 60, 62, 64 and 66. Such a group preent five tap, with 35 the fifth tap (counting downward) erving a the firt tap of the next group down. Each four-reitor group (e.g. 60) i aociated with two correponding witch pair on oppoite ide of the reitor tring (e.g. 38A, 38B on the left, and 52A, 52B 40 on the right). The input terminal of the left-hand witch pair are connected repectively to the 2nd and 4th tap of the reitor group (counting downward), while thoe of the right-hand pair are connected repec tively to the 3rd and 5th tap. Thu, each of the et of 45 witch pair i connected at it inputide to a repective et of ucceive alternate tap, and thee two et of alternate tap are in an interleaved relationhip. The 1t tap of each four-reitor group (correpond ing to the 5th tap of the next group above) i connected to the input terminal of an auxiliary witch 52C, 54C (etc.) having it output connected to the repective output node of the aociated witch pair 52A, 52B, etc. The left-hand et of witche do not include uch auxiliary witche. That i, the output node of the left-hand witch et 36 receive ignal only from the repective witch pair 38A, 38B, etc. The witche of et 36, 50 are operated by control line CL5-CL9 which are controlled together by the logic circuitry in repone to bit 7 and 8 of the upper byte of the input word. The auxiliary witche 52C, etc. erve a carry device, to make connection without having to change the tatu of any of the outer three rank of witche. The outer rank accordingly can hare common control line. Thu, the econd rank 65. Switche on oppoite ide of the reitor tring 24 have common control line CL 1-CL4 and CL 10-CL13. That i, line CL1 and CL 13 are the ame, line CL2 and CL12 are the ame, etc. Similarly, the outer rank alo hare common control line, uch that the four-line et 90 and 92 are the ame line a et 94 and 96. Thi arrangement avoid the need for cotly digital circuitry which otherwie would be required to achieve the re quired tap election. FIG. 3 preent a logic table howing the manner in which the firt-rank witch control line CL5-CL9 are activated in accordance with the tate of bit 7 and 8 of the upper byte. The line ignal are developed by a 2:5 decoder forming part of the firt tage logic circuitry 28. The remainder of the control line are activated in the uual way for uch elector tree. (A word about terminology employed in the claim of thi application: Reference i made at time to ele ment, uch a witche, which are aid to be "adja cent'. Thi i not to imply that they are necearily phyically next to one another on the IC chip, although that could well be the cae. It mean, rather, that the witche are "adjacent with reference to the location of their correponding connection to the voltage tap of the reitor tring. The word "ucceive' a applied to witche imilarly refer to the relationhip of the witch connection to the reitor tring tap.) Etablihing connection to the voltage tap of the reitor tring 26 of the econd converter tage preent a impler problem than that of the firt tage, for only one tap connection need be made for each converion. However, the 256-R reitor tring and elector witch ytem of FIG. 2 can if deired be ued with the econd converter tage. Such a tructure, in conjunction with low-byte XOR'ing, allow the addre to be 2' comple mented. Thi permit the revered voltage egment to be contiguouly canned along with the unrevered OS. Referring now to FIG. 4, the reitor tring 24, 26 i formed on the IC chip a a thin film of Silicon Chro mium. It i an elongate flat trip of metal having evenly paced nipple extending out from both ide to erve a voltage tap. To achieve a high degree of linearity, it i important that the reitor tring be geometrically ho mogeneou, e.g. that each repeat (uch a imilar ec tion including an even number of nipple) of the trip be the ame a every other uch repeat. The term "io morphou' appear properly decriptive. Expreed from a different perpective, the reitor tructure hould be free from any folding or erpentine-like pat tern, i.e. it hould be a ingle, uniform unbent body. FIG. 5 how further detail. It alo i important that there be no interreitor di continuity uch a caued by metallization. Advanta geouly, the nipple hould be longer (laterally, with reference to the reitor tring) than they are wide. Preferably the length-to-width ratio hould be at leat 2:1. Thi avoid interaction between the election of any voltage tap and the current ditribution in the adjacent reitor ection. A reitor tring a implemented herein avoid effect on linearity of contact reitance and any mialignment between conductive and reitive layer, and alo avoid the effect on linearity of folded or imilar repeated tructure. A converter contructed in accordance with the prin ciple decribed herein diplayed carry error typically in the 19-bit range without any trimming. Integral lin earity i a function of reitor accuracy, and a typical range i 0.003% to 0.01%. FIG. 6 how a implified circuit diagram of an amplifier uitable for ue a amplifi er A1, A2 and A3. Thee amplifier were pecified to

10 5 ettle to 16 bit in 3pu and imultaneouly be high preci ion dc op-amp. The amplifier include a ingle differ ential gain tage Q113, Q114, which ue an immittance inverter Q a a load, followed by an MOS/bipolar unity gain impedance buffer. Thi dominant pole com penated amplifier achieve an AVOL of 106 through the ue of boottrapping. Thi minimize the ignal depen dent VCB modulation in Q113, 114 and raie the differen tial load impedance of the gain tage by a factor equal to the loop gain of the amplifier formed by Q , and, finally, linearize the MOS/bipolar unity gain buffer by making VDS track between M117 and M119. To preerve open loop gain, all current ource (hown a an arrow-in-a-circle) are MOS cacoded bipolar tructure. Detail of one uch current ource are hown at M113 and Q113. The reulting impedance enhancement afforded by the revere voltage tranfer ratio of the FET permit an Early voltage of 106 volt to be achieved at the drain of M113. Similarly, Q104 and M105 provide the ame advantage for ource originat ing from the poitive upply, ide-tepping the inher ently low impedance of the plit vertical/lateral PNP' which are problem to form in non-epitaxial procee. It compenation i provided by a PMOS current reflec tor, operating in ubthrehold, hown in part by M and Q100. The Darlington NPN/vertical output tage ha an I, booter for the output VPNP, Q122. M109, 110 in conjunction with Q125,126 boot the bae drive into the output when VoUTlag the voltage at the emitter of Q117 under negative lew. The amplifier oc cupie 1500 mil2 and ettle to 10 ppm in 3 u. The configuration of uch P-type and N-type MOS cacoded bipolar current ource are hown in FIGS. 7A and 7B, repreenting the cro-ection and plan view repectively of the device. FIG. 7C how the electrical circuit repreentation of each device, approxi mately aligned with the correponding element of FIGS. 7A and 7B. Referring now to the left-hand portion of FIGS. 7A and 7B, the non-epitaxial P-type ubtrate i formed with the uual N-well 100. At the left end of the N-well i a firt P-type diffuion 102 of generally rectilinear outline which erve a the drain of a PMOS device. The ource of thi device i formed by a econd P-type diffuion 104 having it principal portion arranged a a quare-haped ring. The PMOS gate 106 i poitioned between the ource and the drain. Within the quare ring of diffuion 104 i another P-type diffuion 108 which erve a the emitter of a lateral PNP tranitor. The N-type material of the N well erve a the bae of thi tranitor, and connection i made to the bae by an N- diffuion 109 of generally U-hape and extending partially around the quare-ring P-type diffuion 104. The collector of the LPNP i formed by the latter diffuion 104. Thu it will be een that thi diffuion erve a both the collector of the LPNP and the ource of the PMOS device. Since both of thee function are performed by the ame diffuion, the PMOS ource and the PNP collec tor are effectively connected together electrically, without any need for bridging metallization. That i, no additional layer of metal ha to be added to the ubtrate to make thi connection, which i illutrated in the cir cuit diagram of FIG. 3C at 110. No electrode i provided for the P-type diffuion 104, ince no external connection i needed to be made to the ource/collector of the MOS-bipolar current ource. 4,543, Electrode are provided for the PMOS drain and for the bae and emitter of the LPNP tranitor. A ditinct characteritic of the PMOS-bipolar current ource i that the entire circuit i integrated into a ingle N-well, which afford important benefit in carrying out the proce. Turning now to the right-hand portion of FIGS. 7A and 7B, there i hown another N-well diffuion 112 within which i a P-type diffuion 114 containing an other N-type diffuion 116. Thee three element func tion repectively a the collector, bae and emitter of an NPN tranitor. Bae and emitter electrode 118, 120 are formed above the ubtrate to make the neceary connection. The N-well 112 i effectively extended laterally by mean of an N-- diffuion 122 which overlap the initial N-type diffuion. The N-- diffuion reache to a region alongide a gate electrode 124, and a further N-- diffu ion 126 i made on the other ide of the gate. Thi latter diffuion erve a the drain of an NMOS device. The ource of thi device i formed by the N-type material with the N-well 112. Thu, it will be een that the N-well 112 (which in thi embodiment include extenion 122) erve a both the ource of an NMOS device and the collector of an NPN tranitor. Accordingly, thee two element are effec tively electrically connected, a indicated at 128 in FIG. 7C, without the need for a metallization layer. The incluion of diffuion 122, a low reitivity ource-drain diffuion comparable to that routinely ued in N-MOS and CMOS fabrication, i to enhance the performance of the compoite tructure through the reduction of the ohmic reitance diagrammatically repreented a path 128 in FIG.7C. The operation of thi invention i other wie unaffected by the omiion of 122. Although a preferred embodiment of thi invention ha been decribed hereinabove in detail, it i deired to emphaize that thi ha been for the purpoe of illutrat ing the invention, and hould not be conidered a nec earily limitative of the invention, it being undertood that many modification can be made by thoe killed in the art while till practicing the invention claimed herein. What i claimed i: 1. A two-tage cacaded digital-to-analog converter wherein the firt of aid tage comprie a erie-con nected tring of reitor energized by a ource of volt age o that the reitor tap preent progreively differ ing voltage level; an improved witch arrangement for electing pair of adjacent tap in accordance with higher-order code bit, thereby to develop egment voltage to be di rected to aid econd converter tage for interpola tion in accordance with lower-order code bit, aid witch arrangement compriing: a firt et of witche having input and output terminal, aid input terminal being connected repectively to a firt et of alternate tap of aid reitor tring; aid firt witch et being organized in pair of firt and econd witche having their input terminal con nected to ucceive alternate tap and having their output terminal connected together to form a firt et of output node; a econd et of witche having input and output termi nal, aid input terminal being connected repec tively to a econd et of alternate tap of aid reitor tring;

11 4,543,560 7 aid econd et of alternate tap being interleaved with aid firt et of alternate tap; aid econd witch et being organized in pair of firt and econd witche having their input terminal connected to ucceive alternate tap and having 5 their output terminal connected together to form a econd et of output node; a third et of witche having input and output termi nal, each of aid third et of witche being aoci ated with a correponding one of aid pair of 10 witche of aid econd et of witche; each of aid output terminal of aid third et of witche being connected repectively to the output node of it correponding pair of witche of aid econd et; the input terminal of each of aid third et of witche being connected to the input terminal of the adjacent one of the next ucceive pair of aid econd et of witche; and witch activating mean for controlling aid witche to elect any pair of adjacent tap in accordance with a et of code bit. 2. A converter a claimed in claim 1, wherein aid converter i formed on a ingle monolithic IC chip. 3. A converter a claimed in claim 2, wherein aid econd tage comprie a reitor tring imilar to that of aid firt tage. 4. A converter a claimed in claim 3, wherein aid converter tage comprie 256-R reitor tring. 5. A two-tage cacaded digital-to-analog converter wherein the firt tage comprie a erie-connected tring of reitor energized by a ource of voltage o that the reitor tap preent progreively differing voltage level; aid tring of reitor being ub-divided into ucceive group each having four reitor preenting five tap, with the fifth tap of one group erving a the firt tap of the next adjacent group; an improved witch arrangement for electing pair of 40 adjacent tap in accordance with higher-order code bit, thereby to develop egment voltage to be di rected to the econd converter tage for interpolation in accordance with lower-order bit, aid witch ar. rangement compriing: a firt et of witch pair compriing firt and econd Switche having input and output terminal, the input terminal of each pair being connected repectively to the econd and fourth tap of a correponding one of aid reitor group; the output terminal of each pair of aid firt et of witch pair being connected together to form a firt et of output node; a econd et of witch pair compriing firt and econd Switche having input and output terminal, the input 55 terminal of each pair being connected repectively to the third and fifth tap of a correponding one of aid reitor group; the output terminal of each pair of aid econd et of Switch pair being connected together to form a ec- 60 ond et of output node; a third et of witche having input and output termi nal, each of aid third et of witche being aoci ated with a correponding one of aid econd et of witch pair; each of aid output terminal of aid third et of witche being connected repectively to the output node of it correponding pair of witche; the input terminal of each one of aid third et of witche being connected to the firt tap of the group of reitor aociated with aid correponding ec ond et of witch pair; and witch activating mean for controlling aid witche to elect any pair of adjacent tap in accordance with a et of code bit. 6. A converter a claimed in claim 5, wherein aid witche all are formed on a ingle monolithic IC chip a NMOS device. 7. A converter a claimed in claim 6, wherein aid reitor tring comprie 256 reitor, aid et of witche providing a 256 to 64 election; and three further rank of elector witche, wherein the outer rank provide a 4 to 1 election, the next pro vide a 16 to 4 election, and the third provide a 64 to 16 election. 8. A converter a claimed in claim 7, wherein aid reitor tring i formed on the chip a an elongate thin film of metal which i geometrically homogeneou. 9. A converter a claimed in claim 8, wherein aid thin film i free of inter-reitor metallization; and a plurality of nipple formed integrally with aid thin film and extending out laterally on both ide of aid thin film to erve a voltage tap to the reitor. 10. A two-tage cacaded digital-to-analog converter wherein the firt tage comprie a erie-connected tring of reitor energized by a ource of voltage o that the reitor tap preent progreively differing voltage level; aid tring of reitor being ub-divided into ucceive group of equal number of reitor having tap to which connection can be made, the end tap of one group erving a the firt tap of the next adjacent group; an improved witch arrangement for electing any pair of adjacent tap in accordance with a higher-order et of code bit, thereby to develop a egment voltage to be delivered to aid econd tage converter for inter polation in accordance with a lower-order et of code bit, aid witch arrangement compriing: a firt et of witch group each compriing a plurality of witche for making connection to any one of a firt et of alternate tap of a correponding reitor group and to produce the elected voltage level on a correponding output node; a econd et of witch group each compriing a plural ity of witche for making connection to any one of a econd et of alternate tap of a correponding rei tor group and to produce the elected voltage level on a correponding output node; aid firt and econd et of alternate terminal being interleaved; a third et of witche each aigned to a correponding one of aid econd et of witch group; the output terminal of aid third et of witche being connected repectively to the output node of the aigned witch group; the input terminal of aid third et of witche being connected repectively to an end tap of the reitor group correponding to the aigned witch group; and Switch activating mean for controlling aid witche to provide for electing any pair of adjacent voltage tap in accordance with the higher-order et of code bit. 11. A two-tage cacaded D/A converter formed on a ingle monolithic IC chip for converting a 16-bit word into a correponding analog ignal, and wherein the firt

12 9 tage comprie a 256-R reitor tring connected to a witch elector ytem to produce egment voltage repreenting the voltage between any two adjacent tap of the reitor; aid reitor tring compriing an elongate geometri cally flat trip of Silicon Chronium formed on aid IC chip a a ingle geometrically homogeneou element, free from folding or erpentine pattern; mean to apply a voltage to the end of aid elongate trip; 4,543, a plurality of elector witche formed along-ide aid elongate flat trip, on both ide thereof, and mean connecting aid witche to evenly-paced point along the ide edge of aid trip. 12. A converter a claimed in claim 12, wherein aid trip i integrally formed with a plurality of nipple evenly-paced along both ide edge of the trip and extending out laterally from both ide thereof; and mean connecting the outer tip of aid nipple to aid witche. 13. A converter a claimed in claim 13, wherein the length of aid nipple i at leat twice the width thereof. ck k e ck 2k