TB059. Using The MCP2150 Developer s Board With The MCP2155 INTRODUCTION MCP2150 DEVELOPER S BOARD LAYOUT

Transcription

1 M TB059 Using The MCP50 Developer s Board With The MCP55 Author: INTRODUCTION Mark Palmer Microchip Technology Inc. This Technical Brief describes how the MCP50 Developer s Board can be used for development of MCP55 applications. The MCP50 is designed for use in Data Terminal Equipment (DTE) applications, while the MCP55 is designed for use in Data Communication Equipment (DCE) applications. This requires some of the UART s non-data circuits to operate differently in these two devices. While the MCP50 can be connected to the DB-9 connector (J5) or the interface Header (J), the MCP55 can only be connected via the interface Header (J). The DB-9 connector is useful for easily connecting to a Host PC. The MCP50 Developer s Board layout is shown in Figure. This Technical Brief focuses on the Host UART signals from the U socket (MCP50/ MCP55) to the MAX8 device (U) and the Header (J). The MCP50 Developer s Board is available in the MCP0/MCP50 Developer s Kit (part number DM6008). FIGURE : MCP50 DEVELOPER S BOARD LAYOUT 00 Microchip Technology Inc. Preliminary DS9059B-page

2 MCP50 DEVELOPER S BOARD UART SIGNALS Table shows the direction of the MCP50 and MCP55 UART signals and the direction of the MAX8 device (U) with respect to the U socket (where the MCP50 or MCP55 reside). Table also shows that only the Carrier Detect (CD) signal has a different direction between the MCP50 and MCP55 UART signals. This will not cause a drive conflict because this signal is an input to the MAX8. Figure shows the layout of the UART driver signals. Each UART signal from the MAX8 device (U) is labeled with the UART signal name and have via s so that they may be cut and then later jumpered back to the original state. If desired, a signal line may be cut for your MCP55 application development. USING THE MCP55 Since the CD signal has a different direction between the MCP50 and MCP55, the DB-9 interface (J5) cannot be used. To interface with the MCP55, the MCP50 Developer s Board must be connected through the Header (J). This requires jumpers J, J and J to have the Header selected (see Figure and Figure ). The application s Host Controller can now implement an IrDA Standard IRCOMM 9-wire "cooked" service class serial link to communicate with the MCP55 via the Header J. The board can be powered by the and GND connectors next to the J header (bottom right of Figure ). Controlling the power to the MCP50 Developer s Board allows the application to reset the MCP50/ MCP55 device when required. TABLE : MCP55 SIGNAL DIRECTION Signal Signal Direction MAX8 (U) to U DB-9 Pin # Name Function MCP50 MCP55 Pin Direction U Pin Number U Pin Number Comment CD Carrier Detect MCP50 HC HC MCP55 Input 7 Different Direction. No drive conflict, MAX8 pin is input. RX Received Data MCP50 HC MCP55 HC Input 7 8 Same Direction. TX Transmit Data HC MCP50 HC MCP55 Output 8 7 Same Direction. DTR () Data Terminal Ready HC MCP50 HC MCP55 Output Same Direction. 5 GND Ground 6 DSR Data Set MCP50 HC MCP55 HC Input 0 Same Direction. Ready 7 RTS Request to HC MCP50 HC MCP55 Output 0 Same Direction. Send 8 CTS Clear to Send MCP50 HC MCP55 HC Input Same Direction. 9 RI () Ring Indicator HC MCP55 9 No issue. Not connected to MAX8. Legend: HC = Host Controller Note : This signal is used for Device Programmable ID mode entry. : This signal is not implemented in the MCP50. DS9059B-page Preliminary 00 Microchip Technology Inc.

3 FIGURE : MCP50 DEVELOPER S BOARD UART DRIVER LAYOUT Board Via (Through-hole) MAX8 (U) CTS DSR DTR TX UART Control, Status and Data Signal Traces (TTL levels) RTS RX CD Jumper UART Control and Data Signals (MAX8 Outputs) to come from Developer Board Header 00 Microchip Technology Inc. Preliminary DS9059B-page

4 MCP50 AND MCP55 PIN DESCRIPTIONS Table gives the pin descriptions for the MCP50, while Table gives the pin descriptions for the MCP55. TABLE : MCP50 PIN DESCRIPTIONS SUMMARY The MCP50 Developer s Board (available in the MCP0/MCP50 Developer s Kit, part number DM6008) can also be used for developing MCP55 applications. This development is straight forward through the use of the Header interface (J) and appropriate configuration of board jumpers. Pin Number Pin Buffer Pin Name PDIP SOIC SSOP Type Type Description BAUD0 I ST BAUD:BAUD0 specify the baud rate of the device. TXIR O Asynchronous transmit to Infrared transceiver. RXIR I ST Asynchronous receive from Infrared transceiver. RESET I ST = Device is operating. 0 = Device is in reset. VSS 5 5 5, 6 P Ground reference for logic and I/O pins. EN I TTL Device enable. = Device is enabled. 0 = Device is disabled (low power). MCP50 only monitors this pin when in the NDM state. TX I TTL Asynchronous receive; from Host Controller UART. RX O Asynchronous transmit; to Host Controller UART. RI Ring Indicator. The value on this pin is driven high. DSR 0 0 O Data Set Ready. Indicates that the MCP50 has completed reset. = MCP50 is initialized. 0 = MCP50 is not initialized. DTR I TTL Data Terminal Ready. The value on this pin is ignored once the MCP50 is initialized. It is recommended that this pin be connected such that the voltage level is either VSS or VCC. At device power-up, this signal is used with the RTS signal to enter device ID programming. = Enter Device ID programming mode (if RTS is cleared). 0 = Do not enter Device ID programming mode. CTS O Clear to Send. Indicates that the MCP50 is ready to receive data from the Host Controller. = Host Controller should not send data. 0 = Host Controller may send data. RTS I TTL Request to Send. Indicates that a Host Controller is ready to receive data from the MCP50. The MCP50 prepares to send data, if available. = Host Controller not ready to receive data. 0 = Host Controller ready to receive data. At device power-up, this signal is used with the DTR signal to enter device ID programming. = Do not enter Device ID programming mode. 0 = Enter Device ID programming mode (if DTR is set). VDD 5, 6 P Positive supply for logic and I/O pins. OSC O Oscillator crystal output. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power CMOS = CMOS compatible input DS9059B-page Preliminary 00 Microchip Technology Inc.

5 TABLE : MCP50 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PDIP SOIC SSOP Type Type Description OSC/CLKIN I CMOS Oscillator crystal input/external clock source input. CD O Carrier Detect. Indicates that the MCP50 has established a valid link with a Primary Device. = An IR link has not been established (No IR Link). 0 = An IR link has been established (IR Link). BAUD I ST BAUD:BAUD0 specify the baud rate of the device. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power CMOS = CMOS compatible input 00 Microchip Technology Inc. Preliminary DS9059B-page 5

6 TABLE : MCP55 PIN DESCRIPTIONS Pin Name Pin Number PDIP SOIC SSOP Pin Type Buffer Type Description BAUD0 I ST BAUD:BAUD0 specify the baud rate of the device. TXIR O Asynchronous transmit to Infrared transceiver. RXIR I ST Asynchronous receive from Infrared transceiver. RESET I ST = Device is operating. 0 = Device is in reset. VSS 5 5 5, 6 P Ground reference for logic and I/O pins. EN I TTL Device enable. = Device is enabled. 0 = Device is disabled (low power). MCP55 only monitors this pin when in the NDM state. TX I TTL Asynchronous receive; from Host Controller UART. RX O Asynchronous transmit; to Host Controller UART. RI I TTL Ring Indicator. The state of this bit is communicated to the IrDA Primary Device. = No Ring Indicate Present. 0 = Ring Indicate Present. DSR 0 0 O Data Set Ready. Indicates that the MCP55 has established a valid link with a Primary Device. This signal is locally emulated and not related to the DTR bit of the IrDA Primary Device. = An IR link has not been established (No IR Link). 0 = An IR link has been established (IR Link). DTR I TTL Data Terminal Ready. Indicates that the Embedded device connected to the MCP55 is ready for IR data. The state of this bit is communicated to the IrDA Primary Device, via the IrDA DSR bit carried by IrCOMM. = Embedded device not ready, clear IrDA DSR bit. 0 = Embedded device ready, set IrDA DSR bit. At device power-up, this signal is used with RTS to enter device ID programming. = Enter Device ID programming mode (if RTS is cleared). 0 = Do not enter Device ID programming mode. CTS O Clear to Send. Indicates that the MCP55 is ready to receive data form the Host Controller. This signal is locally emulated and not related to the CTS/RTS bit of the IrDA Primary Device. = Host Controller should not send data. 0 = Host Controller may send data. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power CMOS = CMOS compatible input DS9059B-page 6 Preliminary 00 Microchip Technology Inc.

7 TABLE : MCP55 PIN DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP SOIC SSOP Pin Type Buffer Type Description RTS I TTL Request to Send. Indicates that the Host Controller is ready to receive data from the MCP55. This signal is locally emulated and not related to the CTS/RTS bit of the IrDA Primary Device. = Host Controller not ready to receive data. 0 = Host Controller ready to receive data. At device power-up, this signal is used with DTR to enter device ID programming. = Do not enter Device ID programming mode. 0 = Enter Device ID programming mode (if DTR is set). VDD 5, 6 P Positive supply for logic and I/O pins. OSC O Oscillator crystal output. OSC/CLKIN I CMOS Oscillator crystal input/external clock source input. CD I ST Carrier Detect. The state of this bit is communicated to the IrDA Primary Device. = No Carrier Present. 0 = Carrier Present. BAUD I ST BAUD:BAUD0 specify the baud rate of the device. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power CMOS = CMOS compatible input 00 Microchip Technology Inc. Preliminary DS9059B-page 7

8 MCP50 DEVELOPER S BOARD SCHEMATIC Figure shows the schematic for the MCP50 Developer s Board. FIGURE : MCP50 DEVELOPER S BOARD SCHEMATIC R J U 8 5 C+ VDD 7 C- VCC 6 C+ C- TIN TOUT 5 TIN TOUT 6 9 TIN TOUT 7 TOUT 0 7 TIN T5IN T5OUT FORCEOFF FORCEON 6 INVALID 5 ROUTB 0 ROUT RIN 8 8 ROUT RIN 9 ROUT RIN GND VEE MAX8CAI IN D C5 AC COM.µF DE9S-FRS C0 5 Y +9 D R7 70 UA7800KTE OUT N9 BT 0µF RX CD CTS DSR DTR TX RTS C7.µF 0µF PHDR C J PHDR J PHDR J 00K U 5K 5K -IN MCP60 +IN C D 000pF U:A.7K D R8.µF IN9 K D5 R9 R0 IN9 70K.µF TFDS U K C C JP J6 DJ005B X X X FIDUCIAL FIDUCIAL FIDUCIAL CR BATTERY R6.7K PHDR J8 PHDR 000PF.K R D7 JP JP C9.7pF R R R C D6 C8 8pF C7.059 MHz 8pF C8 SPI _ 0 C.µF C.µF GRN Power C C.µF.µF C6 C C.µF C5.µF C6 C C R 00 AC J5 R5 LM9NE C.µF U6 VDD RESET CD BAUD BAUD0 TXIR RXIR OSC OSC VSS EN TX RX RI DSR DTR CTS RTS MCP50 7 R J7 R Note: U pin 5 is getting power through R 00 ohm resistor. (Filter) DS9059B-page 8 Preliminary 00 Microchip Technology Inc.

9 APPENDIX A: REVISION HISTORY Revision A Initial Release of Document. Revision B Corrected DTR and RTS pin descriptions for Programmable Device ID mode (Page ). Added Revision History Section (Appendix A). 00 Microchip Technology Inc. Preliminary DS9059B-page 9

10 NOTES: DS9059B-page 0 Preliminary 00 Microchip Technology Inc.

11 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microid, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dspic, dspicdem.net, ECONOMONITOR, FanSense, FlexROM, fuzzylab, In-Circuit Serial Programming, ICSP, ICEPIC, microport, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfpic, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 00, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 999 and Mountain View, California in March 00. The Company s quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 900 certified. 00 Microchip Technology Inc. DS9059B - page

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