AOD4132 N-Channel Enhancement Mode Field Effect Transistor
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- Dortha Lawson
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1 N-Channel Enhancement Mode Field Effect Transistor General Description The OD3 uses advanced trench technology to provide excellent R DS(ON), low gate charge and low gate resistance. This device is ideally suited for use as a low side switch in CPU core power conversion. Standard Product OD3 is Pb-free (meets ROHS & Sony 59 specifications). Features V DS (V) = 3V I D = 5 (V GS = V) R DS(ON) < mω (V GS = V) R DS(ON) < mω (V GS =.5V) UIS Tested Rg,Ciss,Coss,Crss Tested TO-5 D-PK D Top View Drain Connected to Tab G S G D S bsolute Maximum Ratings unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage Symbol V DS V GS Maximum 3 ± Units V V Continuous Drain T C =5 C G 5 Current B,G T C = C B I D 3 Pulsed Drain Current valanche Current C I DM I R 3 Repetitive avalanche energy L=.mH C E R mj T C =5 C Power Dissipation B P D T C = C 5 W.5 Power Dissipation P DSM T =7 C. W Junction and Storage Temperature Range T J, T STG -55 to 75 C Thermal Characteristics Parameter Symbol Typ Max Units Maximum Junction-to-mbient t s. R θj Maximum Junction-to-mbient Steady-State 39 5 Maximum Junction-to-Case C Steady-State R θjc..5
2 Electrical Characteristics (T J =5 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STTIC PRMETERS BV DSS Drain-Source Breakdown Voltage I D =5µ, V GS =V 3 V I DSS Zero Gate Voltage Drain Current V DS =V, V GS =V T J =55 C 5 µ I GSS Gate-Body leakage current V DS =V, V GS = ±V n V GS(th) Gate Threshold Voltage V DS =V GS I D =5µ. 3 V I D(ON) On state drain current V GS =V, V DS =5V 5 V GS =V, I D =. R DS(ON) Static Drain-Source On-Resistance T J =5 C. 5.5 mω V GS =.5V, I D =. mω g FS Forward Transconductance V DS =5V, I D = S V SD Diode Forward Voltage I S =,V GS =V.7 V I S Maximum Body-Diode Continuous Current 5 DYNMIC PRMETERS C iss Input Capacitance 37 pf C oss Output Capacitance V GS =V, V DS =5V, f=mhz 7 pf C rss Reverse Transfer Capacitance 39 pf R g Gate resistance V GS =V, V DS =V, f=mhz.5.7 Ω SWITCHING PRMETERS Q g (V) Total Gate Charge 3 7 nc Q g (.5V) Total Gate Charge 33 nc V GS =.5V, V DS =5V, I D = Q gs Gate Source Charge. nc Q gd Gate Drain Charge 7. nc t D(on) Turn-On DelayTime ns t r Turn-On Rise Time V GS =V, V DS =5V, R L =.75Ω, 5.5 ns t D(off) Turn-Off DelayTime R GEN =3Ω ns t f Turn-Off Fall Time ns t rr Body Diode Reverse Recovery Time I F =, di/dt=/µs 3 ns Q rr Body Diode Reverse Recovery Charge I F =, di/dt=/µs 3 nc : The value of R θj is measured with the device mounted on in FR- board with oz. Copper, in a still air environment with. The Power dissipation P DSM is based on steady-state R θj and the maximum allowed junction temperature of 5 C. The value in any given application depends on the user's specific board design, and the maximum temperature fo 75 C may be used if the PCB or heatsink allows it. B. The power dissipation P D is based on T J(MX) =75 C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. C: Repetitive rating, pulse width limited by junction temperature T J(MX) =75 C. D. The R θj is the sum of the thermal impedence from junction to case R θjc and case to ambient. E. The static characteristics in Figures to are obtained using <3 µs pulses, duty cycle.5% max. F. These tests are performed with the device mounted on in FR- board with oz. Copper, in a still air environment with T =5 C. The SO curve provides a single pulse rating. G. The maximum current rating is limited by the package current capability. Rev : Jan 7 THIS PRODUCT HS BEEN DESIGNED ND QULIFIED FOR THE CONSUMER MRKET. PPLICTIONS OR USES S CRITICL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS RE NOT UTHORIZED. OS DOES NOT SSUME NY LIBILITY RISING OUT OF SUCH PPLICTIONS OR USES OF ITS PRODUCTS. OS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS ND RELIBILITY WITHOUT NOTICE.
3 TYPICL ELECTRICL ND THERML CHRCTERISTICS V I D () 5 3.V 3.5V I D () 5 3 V DS =5V 5 C 5 C V GS =3V 3 5 Fig : On-Region Characteristics Figure : Transfer Characteristics R DS(ON) (mω) V GS =.5V V GS =V 3 5 I D () Figure 3: On-Resistance vs. Drain Current and Gate Voltage Normalized On-Resistance.... I D = V GS =V V GS =.5V Temperature ( C) Figure : On-Resistance vs. Junction Temperature.E+ 5 C.E+.E+ 5 C R DS(ON) (mω) I D = 5 C I S ().E-.E-.E-3 5 C.E- Figure 5: On-Resistance vs. Gate-Source Voltage.E V SD (Volts) Figure : Body-Diode Characteristics
4 TYPICL ELECTRICL ND THERML CHRCTERISTICS V DS =5V I D = 5 C iss Capacitance (pf) 3 C oss Q g (nc) Figure 7: Gate-Charge Characteristics C rss Figure : Capacitance Characteristics I D (mps) R DS(ON) limited ms ms.s s µs µs Power (W) T J(Max) =5 C T J(Max) =5 C s DC.. Figure 9: Maximum Forward Biased Safe Operating rea (Note F).. Pulse Width (s) Figure : Single Pulse Power Rating Junction-to- mbient (Note F) Z θj Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T +P DM.Z θj.r θj R θj =5 Single Pulse In descending order D=.5,.3,.,.5,.,., single pulse P D T on T Pulse Width (s) Figure : Normalized Maximum Transient Thermal Impedance (Note F)
5 TYPICL ELECTRICL ND THERML CHRCTERISTICS I D (), Peak valanche Current T =5 C t L I D = BV V DD Power Dissipation (W)..... Time in avalanche, t (s) Figure : Single Pulse valanche capability T CSE ( C) Figure 3: Power De-rating (Note B) Current rating I D () T CSE ( C) Figure : Current De-rating (Note B)
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More informationSymbol Drain-Source Voltage -30 Gate-Source Voltage Continuous Drain T A =25 C T A =70 C Pulsed Drain Current C V DS V GS
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Description The uses advanced trench technology to provide excellent R DS(ON), low gate charge and operation with gate voltages as low as 2.5V. This device is suitable for use as a load switch or in PWM
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General Description The QM3056M6 is the highest performance trench N-ch MOSFETs with extreme high cell density, which provide excellent RDSON and gate charge for most of the synchronous buck converter
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