Integrated CM Filter for Single-Phase and Three-Phase PWM Rectifiers

Transcription

1 Integrated CM Filter for Single-Phase and Three-Phase PWM Rectifiers A thesis submitted for the degree of Doctor of Philosophy in the Faculty of Engineering By Mohammad Hassan Hedayati Department of Electrical Engineering Indian Institute of Science Bangalore India June 2015

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3 To my parents and my wife...

4 To my parents and my wife...

5 Acknowledgements I would like to express my special appreciation and thanks to my advisor Professor Vinod John, you have been a tremendous mentor for me. I appreciate all his contributions of time, ideas, and funding to make my Ph.D. experience productive and stimulating. Your advices on both research as well as on my career have been priceless. I would like to thank Prof.G.Narayanan, Prof.M.K.Gunasekaran, and Prof.Nagendra Rao and all the faculties of the EE department for the knowledge they shared with me through the course work. I am grateful to Mr. D. M. Chennegowda, and his team at EE office for smooth conduct of administrative affairs. I would like to thank workshop people for teaching me how to use the machines available in the workshop. I thank all the members associated with the Power Electronics Group, Department of Electrical Engineering for the fruitful discussions and support. I would like to thank all my friends and colleagues for their constant support and valuable inputs. Finally, I express my deepest gratitude towards my parents, wife, parents in law, sisters, brother, and all the other relatives and friends for their patience, support, encouragement and understanding. Without them it has not been possible. i

6 ii Acknowledgements

7 Abstract The use of insulated-gate bipolar transistor (IGBT)-based power converters is increasing exponentially. This is due to high performance of these devices in terms of efficiency and switching speed. However, due to the switching action, high frequency electromagnetic interference (EMI) noises are generated. Design of a power converter with reduced EMI noise level is one of the primary objectives of this research. The first part of the work focuses on designing common-mode (CM) filters, which can be integrated with differential-mode (DM) filters for three-phase pulse-width modulation (PWM) rectifier-based motor drives. This work explores the filter design based on the CM equivalent circuit of the drive system. Guidelines are provided for selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed topology. Analytical results based on Bode plot of the transfer functions are presented, which suggest effective EMI reduction. Experimental results based on EMI measurement on the grid side and CM current measurement on the motor side are presented. These results validate the effectiveness of the filter. In the second part of the work, it is shown that inclusion of CM filters into DM filters results in resonance oscillations in the CM circuit. An active damping strategy is proposed to damp the oscillations in both line-to-line and line-to-ground ac voltages and currents. An approach based on pole placement by state feedback is used to actively damp both the DM and CM filter oscillations. Analytical expressions for state-feedback controller gains are derived for both continuous- and discrete-time models of the filter. Trade-off in selection of the active damping gain on the lower-order grid current harmonics is analysed using a weighted admittance function method. In the third part of the work, single-phase grid-connected power converters are considered. An integrated CM filter with DM LCL filter is proposed. The work explores the iii

8 iv Abstract suitability of PWM methods for single-phase and parallel single-phase grid-connected power converters. It is found that bipolar PWM and unipolar PWM with 180 interleaving angle are suitable for single-phase and parallel single-phase power converters, respectively. The proposed configuration along with the PWM methods reduces the CM voltage, CM current, and EMI noise level effectively. It is also shown that the suggested circuit is insensitive to nonidealities of the power converter such as dead-time mismatch, mismatch in converter-side inductors, unequal turn on and turn off of the switches, and propagation delays. In the fourth part of the work, the inter-phase inductor in parallel interleaved power converters is integrated with LCL filter boost inductor. Different variant designs are presented and compared with the proposed structure. It is shown that the proposed structure makes use of standard core geometries and consumes lesser core material as well as copper wire. Hence, it reduces the overall size and cost of the power converter. In the present work, a 10kVA three-phase back-to-back connected with input LCL filter and output dv/dt filter, a 5kVA single-phase grid-connected power converter with LCL filter, and a 7.5kVA parallel single-phase grid-connected power converter with LCL filter are fabricated in the laboratory to evaluate and validate the proposed methods. The experimental results validate the proposed methods that result in significant EMI performance improvement of grid-connected power converters.

9 Contents Acknowledgements Abstract List of Figures List of Tables Acronyms Nomenclature List of Publications i iii xiii xxi xxiii xxv xxix 1 Introduction Power converters, loads and cables parasitics Parasitic capacitances Parasitic inductances Differential mode and common mode definition CM and DM currents in two conductors CM and DM currents in multi conductors CM and DM voltages Electromagnetic interference Conducted emission Radiated emission Filters for power converters v

10 vi Contents DM filters L-filter LC-filter LCL-filter Higher order filter CM-filters Combined DM and CM filters Resonant oscillations Passive damping Active damping Approaches in the literature CM and DM filters for PWM rectifier Active and passive damping of resonant oscillations Integrated CM inductor Power converters topology and design aspects Topology DM and CM filters Damping of the resonant oscillations Modulation technique Phase locked loops Voltage controller Current controller Scope of the work Experimental setup Organisation of the thesis Summary Common Mode Filter Design for PWM Rectifier Based Motor Drives Adjustable speed drive Three-phase diode bridge rectifier Three-phase PWM rectifier Principle of PWM rectifier PWM rectifier control

11 Contents vii LCL filter dv/dt filters The topology for the analysis Common mode circuit analysis CM analysis of ASD CM voltage and CM current of ASD using DBR CM voltage and CM current of ASD using PWM rectifier Design of the CM filter Selection of C y1 and C y Selection of capacitor C Mg Passive damping design DM filter passive damping CM filter passive damping Selection of damping resistance R d Power loss calculation in the damping resistor R d Experimental result Summary Control of Three-Phase PWM Rectifier Three-phase PWM rectifier PWM rectifier control Current control Voltage control Unit-vector generation Modelling of higher-order filters Differential-mode filter model Common-mode filter model State space control law for active damping Differential-mode control law Common-mode control law Analysis in discrete-time domain Discrete-time representation Expressions for Φ and Γ for differential-mode filter modelling 70

12 viii Contents Expressions for Φ cm and Γ cm for common-mode filter modelling Discrete-time state feedback control law Differential-mode control law in DT Common-mode control law in DT Circulating power test setup for a PWM rectifier motor drive Circulating power method Analysis of the DFIM operation Procedure for start up of the test circuit Calculating power losses Experimental results Experimental setup Distortions at low frequency and resonance frequency Effects of active damping gain on grid current lower-order harmonics Energy contained in signal Passive damping and active damping control algorithms Passive damping Active damping Analysis of the experimental results Transient performance of the damping methods Active damping effects on low frequency THD Recommended damping settings Circulating power test DFIM rotor voltage Synchronization of DFIM with SCIM Loading of the setup Power losses and efficiency Summary EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier Grid-side common-mode voltage analysis PWM methods analysis Unipolar PWM method

13 Contents ix Bipolar PWM method Common-mode circuit design Common-mode equivalent circuit derivation Common-mode circuit analysis Parallel single-phase PWM rectifier CM voltage analysis of parallel PWM rectifier PWM method for parallel PWM rectifier Common-mode circuit design Insensitivity to nonidealities Experimental results Single-phase PWM rectifier connected to a motor drive Single-phase parallel PWM rectifier Summary Ground Current and EMI Measurement for Grid-Tied Power Converter EMI generation EMI filter EMI standards Conducted emission test equipment LISN design Line impedance stabilization network (LISN) LISN circuit topology and transfer function analysis LISN component design Resistor selection Inductor design Capacitor selection Single-phase LISN Ground current measurement Leakage current measurement of single-phase systems Leakage current measurement of three-phase three-wire systems Leakage current measurement of three-phase four-wire systems Accuracy enhancement of the measurement Experimental results

14 x Contents Conducted emission test Summary Integrated CM Inductor for Parallel Interleaved Converters Parallel interleaved converters Interleaving of carriers Circulating current Inter-phase inductor Combined boost and inter-phase inductor Integrated CM inductor (ICMI) Integrated CM inductor design Inductance calculation Inter-phase inductance calculation Boost inductance calculation Reluctance calculation Modification of ICMI for use in single converter Modified ICMI Design example Finite element analysis of ICMI Comparison between ICMI design and other designs Separated inter-phase and boost inductor design Inter-phase inductor design Boost inductor design Comparison between ICMI and separated boost and inter-phase inductor Experimental results Summary Conclusion and Future Work Integrated CM and DM filters Three-phase PWM rectifier Single-phase PWM rectifier Parallel single-phase PWM rectifier Integrated CM inductor

15 Contents xi 7.3 Active damping of LCL resonance Circulating power test setup Future work Summary Appendix A Parseval s Theorem 195 Appendix B Experimental Setup 197 B.1 Fabricated power converter specifications B.2 Details of FPGA digital controller B.3 Experimental setup References 205

16 xii Contents

17 List of Figures 1.1 Three-phase power converter with parasitic capacitances C p1 and C p Current in parallel conductors (a) total current, (b) DM current, (c) CM current L-filter configuration LC-filter configuration LCL-filter configuration A typical CM-filter configuration A typical CM-filter configuration Passive damping configurations. (a) Resistive damping, (b) split-capacitor resistive damping, and (c) split-capacitor inductive-resistive damping Three-phase grid-connected adjustable speed motor drive Three-phase off-grid adjustable speed motor drive Three-phase PWM rectifier connected to grid using L filter (a) Single-line equivalent circuit of a PWM rectifier connected to grid using L filter and (b) phasor representation of (1) Phasor diagrams of a PWM rectifier under different operating modes. (a) Unity power factor, (b) lagging power factor, (c) regeneration at unity power factor, (d) leading power factor, (e) regeneration at leading power factor, and (f) regeneration at lagging power factor Per-phase equivalent circuit of an LCL filter Bode magnitude plot of transfer function ig v i, where L g = L i =2.5mH and C =20µF Schematic of grid-connected ASD with LCL filter, dc bus CM filter, and dv/dt filter at inverter terminal for the motor load xiii

18 xiv List of Figures 2.9 Schematic of PWM rectifier with LCL filter CM equivalent circuit of the PWM rectifier shown in Fig Waveforms illustrating (a) CM voltage due to drive inverter alone, (b) resulting CM current due to the presence of parasitic capacitance, (c) CM voltage due to PWM rectifier switching at higher frequency than the inverter, (d) CM voltage due to combined effect of inverter and PWM rectifier, and (e) CM current with PWM rectifier ASD due to the presence of parasitic capacitance Schematic of grid-connected PWM rectifier with LCL filter and CM filter CM equivalent circuits of the PWM rectifier excluding the passive damping resistor, (a) without IGBT module parasitics and (b) with IGBT parasitic capacitors Low frequency approximation of CM equivalent circuit of the filter I 2.15 Admittance magnitude plot of com(s) for different values of effective C V AF E (s) y. A lower admittance of the filter will lead to smaller internal circulating current Frequency response plot of I Mg (s) V AF E (s) for different values of C Mg High frequency approximation of CM equivalent circuit of the filter Passive damping of the oscillation in LCL filter using a split-capacitor parallel R d -C d damping branch Frequency response plot of transfer function Vc(s) V i (s) given in (29) for different values of damping resistance, where, R b = 3V b 2 P b =17.28Ω (a) CM equivalent circuit for the PWM rectifier shown in Fig (b) Low frequency approximation Frequency response plot of transfer function I comi(s) V com(s) given in (31) for different values of damping resistance Effect of damping resistance on filter magnitude response and power loss. (a) Peak magnitude of response at resonant frequency versus the damping resistance, for the transfer function Vc(s) V i in db and the transfer function (s) I comi(s) V com(s) in db. (b) Power loss in the damping resistors versus damping resistance values due to both differential- and common-mode excitation

19 List of Figures xv 2.23 Different variants of filter topology. (a) Case B, where the capacitor C Mg and the connection between N and M are removed, and the star point, N, is connected to the ground directly. (b) Case C, where the capacitor C Mg and the connection between N and M are removed, and the point M is connected to the ground directly The Bode plot of admittance I Mg(s) V AF E (s) offered to CM voltage by ground LISN connected between the grid and EUT Conducted noise emission test measured on the grid side of the ASD. (a) The CM filter configuration shown in Fig (b) The capacitor C Mg and the connection between N and M are removed, and the star point, N, is connected to the ground directly, as shown in Fig. 2.23(a). (c) The capacitor C Mg and the connection between N and M are removed, and the point M is connected to the ground directly, as shown in Fig. 2.23(b) CM current noise at the motor load side measured by the sum of three phase currents. (a) The CM filter configuration shown in Fig (b) The capacitor C Mg and the connection between N and M are removed, and the star point, N, is connected to the ground directly, as shown in Fig. 2.23(a). (c) The capacitor C Mg and the connection between N and M are removed, and the point M is connected to the ground directly, as shown in Fig. 2.23(a). (d) No CM filter at all PWM rectifier connected to grid using L filters Current control loop using PI controller in SRF Voltage control loop using PI controller SRF-PLL block diagram used for the PWM rectifier control PWM rectifier with combined CM and DM filters Differential model of the LCL filter shown in Fig (a) The CM equivalent circuit of the PWM rectifier shown in Fig (b) Low frequency approximation of CM equivalent circuit The overall circuit configuration of motor drive coupled to a DFIM, which is used to circulate power back to the grid Positions of the stator, rotor, and the air gap field reference frames

20 xvi List of Figures 3.10 Rotor voltage (V r ) versus speed difference (N RMF -N r ) between RMF and DFIM rotor. The modes of operation of the SCIM are indicated The circuit configuration to measure the circulating and input power of the PWM rectifier motor drive Control block diagram of a vector controlled PWM rectifier with DM and CM active damping loops Admittance offered by the PWM rectifier to different harmonics and weighted admittance, evaluated for different DMAD gain given in (48) Filter capacitor line to line voltage and grid-side phase current (top); CM dc-bus capacitor midpoint to ground voltage (middle); and FFT of line to line voltage (F1), FFT of grid current (F2), and FFT of CM voltage (F3) (bottom). (a) Case (i)-no damping, (b) case (ii)-passive damping, and (c) case (v)-with active damping. With load of 5.5kW and active damping gain corresponding to ζ = Spectrum of LCL capacitor line to line voltage (F1) and spectrum of dc-bus capacitor midpoint to ground voltage (F2). (a) Case (iii)-with only DMAD, (b) case (iv)-with only CMAD, and (c) case (v)-with both DMAD and CMAD. With active damping gain of ζ = Filter capacitor line to line voltage and grid-side phase current for step load change from 1kW to 5.5kW at t =0.1s. (a) Case (i) with no damping, (b) case (ii) with passive damping, and (c) case (v) with active damping with ζ = Grid-side current low frequency THD for different settings of the DMAD gains The SCIM line current while shorting the DFIM rotor terminals at different speed mismatch between RMF and rotor. The solid lines are SCIM current and the dotted lines show the time when the rotor terminals are shorted. (a) Synchronization at minimum rotor voltage, (b) with 90rpm speed mismatch between RMF and rotor speed, and (c) with 185rpm speed mismatch between RMF and rotor speed Loading of the motor drive in (a) motoring mode and (b) regenerative mode Conventional single-phase PWM rectifier with symmetrical LCL filter [1] connected to a three-phase motor drive inverter with LC filter

21 List of Figures xvii 4.2 Switching states of a single-phase H-bridge converter using (a) unipolar PWM method and (b) bipolar PWM method Switching states of a single-phase H-bridge converter using bipolar PWM method with unequal dead time Conventional single-phase PWM rectifier with combined symmetrical LCL filter with CM filter, connected to a three-phase motor drive inverter with LC filter CM equivalent circuit of the single-phase to three-phase motor drive shown in Fig Grid-side CM equivalent circuit of the filter with (a) low-frequency approximation and (b) high-frequency approximation Parallel single-phase PWM rectifier with symmetrical LCL filter Switching states for a parallel single-phase inverter with 180 carrier interleaving Parallel single-phase PWM rectifier with symmetrical LCL filter along with the CM filter CM equivalent circuit of parallel single-phase inverter along with the modifications to the topology Bode magnitude plot of admittance transfer function I com2 v inv for the CM circuit with and without the proposed CM filter Grid voltage and grid current of the power converter operating at 3.5kW as a UPF, 200V/div, 20A/div, 5ms/div CM voltage v Og (i.e., dc-bus midpoint to ground voltage) in the single-phase PWM rectifier, 200V/div, 5ms/div. (a) Case A, no CM filter with unipolar PWM and (b) case B, no CM filter with bipolar PWM EMI noise level comparison: (a) case A, no CM filter with unipolar PWM and (b) case B, no CM filter with bipolar PWM. 20dBV/div, 1MHz/div EMI noise level comparison with different filter configurations and with bipolar PWM. Top, case C with OM connection (F 1 ). Bottom (F 2 ), case D with OM connection and with capacitor C Mg. 20dBV/div, 1MHz/div CM voltage with unequal dead time (a) without the CM filter and (b) with the CM filter. 200V/div, 5ms/div EMI noise level with unequal dead time (a) without the CM filter and (b) with the CM filter. 20dBV/div, 1MHz/div

22 xviii List of Figures 4.18 Grid voltage and grid current of the PWM rectifier operating at 7.5kW Measured leakage current of parallel single-phase PWM rectifier as a function of PWM interleaving angles, (a) without the modifications to the circuit topology, as shown in Fig. 4.7, and (b) with and without modifications to the circuit topology CM voltage (dc-bus midpoint to ground voltage V Og ) and FFT of CM current i comg (summation of line and neutral currents) of a parallel single-phase PWM rectifier. (a) and (b) the case A with 0 carrier interleaving, (c) and (d) the case B with 90 carrier interleaving, (e) and (f) the case C with 180 carrier interleaving, (g) and (h) the case D with 180 carrier interleaving angle and with modifications to the circuit shown in Fig Note that the ampere per division in (f) and (h) is 2.0mA/div, whereas in (b) and (d) it is 40mA/div. The center frequency in (b), (d), (f), and (h) is 50kHz EMI noise level comparison, (c) case C with 180 carrier interleaving and (d) case D with 180 interleaving angle along with modifications to the circuit shown in Fig Efficiency of parallel single-phase PWM rectifier, (a) as a function of interleaving angles at 4kW and (b) with 180 interleaving angle along with the modifications as a function of input power Voltage transient caused by IGBT switching. 250V/div, 250ns/div A typical single-phase EMI filter Conducted emission test equipment Typical three-phase CE compliant measurement setup schematic to measure conducted EMI noise Bode magnitude plots of LISN transfer functions. (a) Receiver to input Vrec V in, (b) output to input Vout V in, and (c) receiver to output Vrec V out The dimensions of coil L 1 shown Fig.5.7(a) Fabricated inductors. (a) Inductor L 1 and (b) inductor L Mechanical layout of the designed LISN Single-phase LISN Leakage current flow in a single-phase system Leakage current measurement of single-phase systems

23 List of Figures xix 5.12 Leakage current measurement of three-phase three-wire systems Leakage current measurement of three-phase four-wire systems Use of multiple turns with current clamp: (a) schematic and (b) experiment Measured frequency response of (a) Vrec V in, (b) Vout V in, and (c) Vout V rec of the LISN Admittance plot of (a) inductor L 1, (b) inductor L 2, and (c) the newly designed 50µH inductor with N=30 turns, D=14.5cm, and l=30cm CE test results of (a) three-phase motor drive and (b) background noise of the high frequency oscilloscope CE test results of (a) single-phase SMPC and (b) CM current of the SMPC scaled by LISN factor of Parallel single-phase PWM converters with inter-phase inductors and LCL filter. The solid boxes contain the components incorporated into the integrated CM inductor Interleaved carriers with interleaving angle of α= States of the top switch of first converter, S a1, + and the bottom switch of the second converter, Sa2, of phase a An inductor with a center tap used as an inter-phase inductor Structure of ICMI. (a) The magnetic structure given in [2]. (b) ICMI fluxes path due to the circulating currents (dotted lines) and output currents (dashed lines). (c) ICMI winding connections Flowchart for designing the integrated CM inductor Ratio of core reluctance to total reluctance as a function of air gap, for different core sizes ICMI with (a) individual winding voltage drops and fluxes due to circulating current. (b) Magnetic equivalent circuit for circulating current. (c) Core geometric dimensions Single-phase grid-connected power converter with LCL filter and CM choke, proposed in [3] (a) The LCL filter and CM choke shown in Fig (b) Sense of the windings and the connections of the proposed ICMI. (c) Fluxes in the core due to DM current, i dm. (d) Fluxes in the core due to CM current, i cm

24 xx List of Figures 6.11 Maximum number of turns that can be accommodated in the window area of cores, and the required number of turns for different core sizes Flux density and flux linkage plot of the ICMI due to (a) output current only, (b) circulating current only, and (c) combined output and circulating currents Separated inter-phase and boost inductor: (a) case A with two boost inductors, one for each leg, and (b) case B with a boost inductor between the inter-phase inductor and the output filter (a) The fabricated integrated CM inductor for a 7.5kW, 240V, single-phase inverter. (b) The thermal image of the ICMI after running the setup for two hours at full-load condition under natural convection cooling Current waveform in the parallel inverters. (a) Converter currents, (b) converter currents harmonic spectra, and (c) circulating current with its harmonic spectrum Grid voltage and grid current and their harmonic spectra Schematic of grid-connected ASD with LCL filter, dc bus common-mode filter, and dv/dt filter at inverter terminal for the motor load Single-phase PWM rectifier with combined symmetrical LCL filter with CM filter, connected to a three-phase motor drive inverter with LC filter Parallel single-phase PWM rectifier with symmetrical LCL filter along with the CM filter B.1 An ALTERA Cyclone II FPGA based controller board employed in the experimental tests B.2 (a) Two power converters sharing the same dc bus. (b) Auxiliary power supplies and the passive filters B.3 Gate driver card and protection and delay card B.4 The ICMI structure presented in Chapter B.5 A 5.5kW SCIM coupled with a 10kW DFIM B.6 Fabricated three-phase 10kW LISN B.7 The cabinet housing the power converters

25 List of Tables 2.1 Different modes of operation and power flow directions of PWM rectifiers Designed CM dc-bus filter values Design values for the filter State space gain for damping coefficient ζ = Energy contained in signals (V 2 s) near the filter resonance frequency Single-phase grid-connected inverter parameter values shown in Fig Power losses and efficiency with bipolar and unipolar PWM Case studies of grid-side and motor-side CM current values with equal dead time of 3µs and with unequal dead time of 3µs and 2µs Single-phase parallel PWM rectifier circuit parameter values shown in Fig Allowable conducted emission levels (dbµv) Component values of LISN shown in Fig Specification of Inductors L 1 and L ICMI core and winding parameters evaluation ICMI core and winding parameters evaluation Design parameters of the separated inter-phase and boost inductors Comparison between different inductor design cases Designed and measured parameters of the integrated CM inductor B.1 Power Converter Specifications B.2 Designed Parameters of the ICMI B.3 Nameplate details of the SCIM and DFIM xxi

26 xxii List of Tables B.4 Specifications of Inductors L 1 and L

27 Acronyms AD ADC AFE AM ASD CE CM CMAD CSVPWM CT DM DBR DT DFIM DMAD ECS EMC EMI ESL ESR EUT FEC FEM FFT Active Damping Analog to digital converter Active Front End Amplitude Modulation Adjustable Speed Drive Conducted Emission Common Mode Common Mode Active Damping Conventional Space Vector PWM Continuous Time Differential Mode Diode Bridge Rectifier Discrete Time Doubly Fed Induction Machine Differential Mode Active Damping Energy Contained in Signal Electromagnetic Compatibility Electromagnetic Interference Equivalent Series Inductance Equivalent Series Resistance Equipment Under Test Front End Converter Finite Element Method Fast Fourier Transform xxiii

28 xxiv Acronyms FPGA GaN IGBT LISN PCB PF PFC PI PLL PR PRS PVC PWM RE RMF RPM SCIM SiC SMPC SOGI SRF SWG TBR THD UPF UPS VSI Field Programmable Gate Array Gallium Nitride Insulated Gate Bipolar Transistor Line Impedance Stabilization Network Printed Circuit Board Power Factor Power Factor Correction Proportional Integral Phase Locked Loop Proportional Resonant Phase Reversal Switch Polyvinyl Chloride Pulse Width Modulation Radiated Emission Rotating magnetic Field Revolutions per minute Squirrel Cage Induction Machine Silicon Carbide Switched-Mode Power Converter Second Order Generalized Integrator Synchronized Reference Frame Standard Wire Gauge Thyristor Bridge Rectifier Total Harmonic Distortion Unity Power Factor Uninterruptible Power Supply Voltage Source Inverter

29 Nomenclature ω d ω dcm ω s σ σ cm σ l ω r ζ ζ cm Imaginary part of DM desired pole locations Imaginary part of CM desired pole locations Angular velocity of the stator RMF in electrical Real part of DM desired pole locations Real part of CM desired pole locations Leakage factor Angular velocity of rotor in electrical DM damping factor CM damping factor µ Angle between stator and air gap field axis ɛ Angle between stator and rotor axis R Total reluctances R core R gap Core reluctances Air-gap reluctances µ 0 Magnetic permeabilities of air µ r Magnetic permeabilities of core material Φ DM state matrix in DT Φ cm Γ Γ cm A A c A cm A w CM state matrix in DT DM input matrix in DT CM input matrix in DT DM state matrix in CT Cross section of the core CM state matrix in CT Cross section of a single wire xxv

30 xxvi Nomenclature B B cm B max C L C y1, C y2 C Mg C dc C d d a, d b E CS F f f res f rescm F sw G I abc i ai, i bi, i ci i cir I CM I DM i g i i I comg I comi I n I p i r i s J k 1 k 2 DM input matrix in CT CM input matrix in CT Maximum peak flux density Capacitor of LCL filter DC bus Y capacitor of CM filter CM filter capacitor Dc bus capacitance Damping capacitor PWM modulation duty ratio Energy Contained in Signal Fringing factor Frequency of the grid voltage LCL filter resonance frequency CM filter resonance frequency Switching frequency Converter gain set of three-phase current Converter side phase currents Circulating current CM current DM current Grid side current Inverter side current Grid side CM current Inverter side CM current Input current harmonics to the power converter Peak current Rotor current space phasor in rotor reference frame Stator current space phasor in stator reference frame Current density Voltage sensor gain Current sensor gain

31 Nomenclature xxvii K 1,2,3 K 1cm,2cm K 1D,2D,3D K 1Dcm,2Dcm k c k v K w L 0 L g L i L P L r M n N p P P b R b R d R r R s T T 1 T 2 T c T d T s T v u r V b V C V com DMAD state feedback gain in continuous time CMAD state feedback gain in continuous time DMAD state feedback gain in discrete time CMAD state feedback gain in discrete time Current loop PI controller gain Voltage loop PI controller gain Winding factor Magnetizing inductance Grid side inductor of LCL filter Inverter side inductor of LCL filter Parallel combination of L g and L i Rotor windings self-inductance PWM modulation index Harmonic number Possible number of turns that can be occupied in the window area of core Number of poles Base power Base impedance Damping resistor Rotor windings resistance Filter inductor resistance ADC sampling time Voltage sensor time constant Current sensor time constant Current loop PI controller time constant Converter delay Filter inductor time constant Voltage loop PI controller time constant Rotor voltage space phasor in rotor reference frame Base voltage LCL filter capacitor voltage Common mode voltage of inverter

32 xxviii Nomenclature V i V n V S, e g W a x X(f) X[k] x[kt] Y n Inverter output voltage line voltage harmonics Grid voltage Window area of the core State vector in CT Continuous Fourier transform of x(t) Discrete Fourier transform of x[n] State vector in DT Input admittance of the power converter offered to n th harmonic

33 List of Publications 1. M. Hedayati, A. Acharya B, and V. John, Common mode filter design for PWM rectifier based motor drives, IEEE Trans. Power Electron., vol. 28, no. 11, pp , M. Hedayati, A. Acharya B, and V. John, Common-mode and differential-mode active damping for PWM rectifiers, IEEE Trans. Power Electron., vol. 29, no. 6, pp , June M. Hedayati and V. John, Filter configuration and PWM method for single phase inverters with reduced conducted EMI noise, IEEE Tran. Ind. Appl., vol. PP, no. 99, pp. 1 1, M. Hedayati and V. John, Circulating power test setup for a PWM rectifier motor drive, IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Bangalore, India, Dec 2012, pp M. Hedayati and V. John, Design of a 3-phase line impedance stabilization network for conducted emission test, Sixth National Power Electronics Conference, Kanpur, India, Dec M. Hedayati and V. John, Filter configuration and PWM method for single phase inverters with reduced conducted EMI noise, IEEE Transportation Electrification Conference and Expo, Beijing, China, pp. 1 6, Aug M. Hedayati and V. John, A novel integrated cm inductor for parallel converters with interleaved carrier, IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Mumbai, India, Dec 2014, pp xxix

34 xxx List of Publications 8. M. Hedayati, and V. John, Integrated Common-Mode Inductor for Parallel Interleaved Converters, IEEE Trans. Power Electron., ( Under review) 9. M. Hedayati, and V. John, A Novel Integrated CM Inductor for Single-Phase Power Converters, 2015 IEEE International Transportation Electrification Conference (ITEC), Chennai, India, ( Under review) 10. M. Hedayati, and V. John, Ground Leakage Current Reduction in Single-Phase Grid- Connected Power Converter, 2015 Intl Aegean Conference on Electrical Machines & Power Electronics (ACEMP), 2015 Intl Conference on Optimization of Electrical & Electronic Equipment (OPTIM) & 2015 Intl Symposium on Advanced Electromechanical Motion Systems (ELECTROMOTION), Side, Turkey, ( Under review) 11. M. Hedayati, and V. John, High Performance Parallel Single-Phase Converter Reconfiguration for Enhanced Availability, 2015 Intl Aegean Conference on Electrical Machines & Power Electronics (ACEMP), 2015 Intl Conference on Optimization of Electrical & Electronic Equipment (OPTIM) & 2015 Intl Symposium on Advanced Electromechanical Motion Systems (ELECTROMOTION), Side, Turkey, ( Under review)

35 Chapter 1 Introduction The use of insulated-gate bipolar transistor (IGBT)-based grid-connected power converters is increasing in applications such as power factor correction (PFC), adjustable speed drives (ASD), pulse-width modulation (PWM) rectifiers, battery chargers, and active filters. This is due to high efficiency, ease of control, low total harmonic distortion (THD), etc., of the power converters. As the technology of semiconductor devices advances further, power converters become more efficient. Faster devices can be switched at a higher frequency and made more efficient; this makes the power converters even more attractive [12 14]. The output powers of many renewable resources applications are dc. Hence, power converters are essential in renewable resources applications for converting the dc power to ac. The power converters convert dc power to ac power and deliver it directly to the consumers in the case of standalone applications or transfer it to the grid in grid-connected applications. Sizes of gridconnected converters have reached a few Megawatts. It is expected that the considerable amount of power to be provided by renewable resources will soon lead to the utilization of such power converters. Extensive research is going on for making power converters more efficient, more reliable, and safer. For a power converter to be connected to the grid, several standards and recommendations should be met. There are standards related to current and voltage ripple, THD, electromagnetic interference EMI/EMC, and ground leakage current [4 6, 15, 16]. These standards basically specify limits on the level of disturbance that a power converter can have. Problems like pulsating torque in motor drive application, increased losses, and heating are caused by high THD. High EMI noise level can affect the performance of the power converter itself, and it can also interfere with the operation of the neighbouring equipment. The leakage current of power converters must be as low as possible as it is directly related 1

36 2 to safety concerns. In domestic applications the ground leakage current has a very stringent limit and it cannot be more than a few milliamperes. Electromagnetic interference consists of conducted emission (CE) and radiated emission (RE). All unintentional electromagnetic energy radiated from an electric device is called RE. Standards specify the allowable RE level [4]. A high level of RE can interfere with the operation of the nearby electronic devices as well as the power converter itself. In CE, the electromagnetic energy generated by an electronic device is transferred to the grid directly through the ac power mains. Similar to RE, CE standards specify the limits for maximum allowable CE generated by power converters. The frequency range specified for CE is lower than that for RE. The problem with CE is that, when it propagates to the grid, it can become RE and radiate out. This is because the lower frequency waves would have longer wavelengths. The antenna needed to send and receive waves with longer wavelengths is larger than that required for waves with shorter wavelengths. CE may not radiate from the device itself, but it can propagate to the grid network and find a larger antenna and radiate out. The RE generated from CE will interfere with the operations of other electronic equipment. In some cases, the CE can affect the neighbouring equipment through electrical connections. This thesis focuses on the following: Studying different filter topologies for single-phase, parallel single-phase, and threephase grid-connected power converters with reduced EMI and ground leakage current Integrated common mode (CM) with output LCL filter design Different PWM methods and their impact on EMI and ground leakage current Active and passive damping of the resonant oscillations in CM and differential mode (DM) Design of a magnetic structure for parallel converters Section 1.1 explains the parasitic capacitances and inductances of the power converter s load and cables. In Section 1.2, CM and DM currents and voltages are discussed. Section 1.3 explains conducted and radiated emissions. DM and CM filters are discussed in Section 1.4. Approaches described in the literature are summarized in Section 1.5. In Section 1.6 the topology and design aspects of power converters are presented. In Section 1.7 the scope of the

37 Chapter 1. Introduction 3 work is listed. Section 1.8 provides the details of the experimental setup. The organization of the chapters is outlined in Section 1.9. Section 1.10 summarizes the chapters. 1.1 Power converters, loads and cables parasitics Parasitic capacitances Parasitic capacitances refer to all unintentional capacitors that are present in electrical systems. Capacitors are made of two metallic surfaces (wire, metallic body, or any metallic material) and a dielectric medium. Hence, wherever two conducting materials with an insulator between them are present, parasitic capacitance is also present. Parasitic capacitances can be categorized into different groups. The first group consists of parasitic capacitances that are useful and can be utilized. For instance, in a printed circuit board (PCB) it is possible to use the parasitic capacitances as desired capacitances in the circuit by carefully designing the thickness of the PCB and the tracks. The second group consists of parasitic capacitances that do not have any effect on the system and its operation. This can be found in applications where the circuit configuration is such that the parasitic capacitances are either in parallel with short circuits or in parallel with capacitors that have a reasonably higher capacitance value compared with parasitic capacitances. Also included in this group are the parasitic capacitances that are formed at places with no significant voltage variation. The last group consists of parasitic capacitances that are harmful; they affect the normal operation of the system. In most cases, these parasitic capacitances are found between the component parts and the ground, for example, the parasitic capacitances between unearthed equipment body and the component parts inside the equipment. They can result in electric shock. Parasitic capacitances are very important in power converters. Because of fast switching actions of semiconductor devices, high dv/dt is generated. In the presence of parasitic capacitances, these voltage-level changes with high dv/dt transitions excite the parasitic capacitances and cause injection of a narrow peaky current to the ground. This increases the ground leakage current. In Fig. 1.1 a three-phase power converter is shown. The switches parasitic capacitances C p1 and C p2 are the parasitic capacitances between the collector, emitter, and the base plate. The base plate is mounted on a heat sink, and the heat sink is

38 Power converters, loads and cables parasitics Figure 1.1: Three-phase power converter with parasitic capacitances C p1 and C p2. normally grounded. Hence, the switches parasitic capacitances are practically between the switches and the ground, as shown in Fig Parasitic capacitances of cables are between the phase conductors and the ground conductor or ground shield. They can also be formed between the cables. Parasitic capacitances of cables can increase the wave travelling time in cables and cause voltage doubling. They also increase the ground leakage current. Parasitic capacitances of a motor are formed between the windings and the body of the motor. They cause problems such as increased ground leakage current and bearing current Parasitic inductances Every conductor has finite inductance. This inductance is called parasitic inductance. Parasitic inductances are also categorized into three groups: the parasitic inductances that are useful, the parasitic inductances whose presence does not matter, and the parasitic inductances that are problematic. In some cases, the parasitic inductances and parasitic capacitances interact with each other and cause resonant oscillations. The parasitic inductances that need extra care in power converters are the dc-bus inductance and the gate wire lead inductance. High value of dc-bus parasitic inductance causes high voltage generation across the switches because of high di/dt. The gate wire parasitic inductance causes ringing in the gate signal.

39 Chapter 1. Introduction 5 (a) (b) (c) Figure 1.2: Current in parallel conductors (a) total current, (b) DM current, (c) CM current. 1.2 Differential mode and common mode definition CM and DM currents in two conductors DM current is defined as the current that passes through a conductor and returns through the return conductor. This is shown in Fig. 1.2(b). CM current, shown in Fig. 1.2(c), is defined as the current that passes through a conductor and also passes through the return conductor with the same polarity. Hence, an arbitrary current through a pair of conductors can be split into CM current and DM current, as shown in Fig Conventional power electronic circuit analysis only analyses the DM current, and the CM current is assumed to be zero. The CM current is the key reason for EMI/EMC problems. From Fig. 1.2 the DM and CM currents can be written as: I DM = I 1 I 2 2 I CM = I 1 + I 2 2 The significance of the CM current becomes evident when RE is considered. For parallel conductors the radiated electric fields generated by DM are the opposite of each other and they cancel each other. Hence, negligible radiated electric field is generated. The radiated electric field generated by CM currents has the same polarities and add up resulting in higher net radiated electric field.

40 Electromagnetic interference CM and DM currents in multi conductors In multi-conductor applications such as the three-phase system, the CM current is defined as the current that passes through all the conductors with the same magnitude and same polarity. The DM current is defined as a current that passes through a conductor and returns through the rest of the conductors. Hence, the summation of DM currents equals zero. The DM and CM components of a three-phase system can be calculated as follows, I CM = I a + I b + I c 3 I DMabc = I abc I CM where, I CM is the CM current, I abc is the set of three-phase current, and I DMabc component of the three-phase current. is the DM CM and DM voltages The DM voltage between two nodes is defined as the voltage that is applied between these nodes. The CM voltage is the average voltage that appears at two or more nodes of the circuit, with respect to a common reference like ground. The significance of the CM voltage with respect to ground is that high frequency CM voltage can excite the parasitic capacitances between the circuit and ground or cabinet. The excitation of parasitic capacitances results in flow of CM current and ground leakage current. In power electronic applications with switching actions, high dv/dt in the CM voltage results in injection of a high peaky current to ground. This will increase the CE as well as the ground leakage current. 1.3 Electromagnetic interference Conducted emission The CE is the electromagnetic energy generated by electronic equipment and is coupled with the grid through the ac power plug. The range specified for CE by the standards is 150kHz to 30MHz. Different standards and classes are available specifying the limits on CE generated by electronic devices. For instance, CISPR class B recommends that the noise level should not be higher than 60dBµV [17]. This standard is for the equipment intended to be used in domestic areas. CE tests are carried out to measure the amount of CE noise generated by the equipment. The knowledge about CM and DM is very important for the analysis of

41 Chapter 1. Introduction 7 the CE. CM and DM currents and voltages are explained in Section 1.2. A line impedance stabilization network (LISN) and a spectrum analyser are essential for CE test. The LISN is connected between the equipment under test (EUT) and the grid. The spectrum analyser is connected to the port provided by the LISN and is used to measure the CE Radiated emission The main reason for the RE is the CM current flowing through the circuit. This is due to the radiated electric field, which is high in the case of CM current. The RE range recommended by the respective standards is from 30MHz to a few GHz. In this range, the wavelength is comparable to the size of conductors. In that case, the RE can easily radiate out. In this thesis, only CE is considered. 1.4 Filters for power converters Filters are essential for applications such as grid-connected converters. The converters cannot be connected to the grid directly, and a filter is needed. The filter, which connects the power converter to the grid, is a low-pass filter. It passes the fundamental frequency and blocks the undesired higher frequency. IEEE and IEEE [15, 16] are the standards that recommend the limits on the ac-side current and the voltage harmonics and their THD. To meet these standards, the filter should be properly designed [18]. These filters are designed such that they filter out the high frequency DM current and are called DM filters or output filters. As mentioned in Section 1.3, there are limits on the CE and RE noise levels. Structures of CM filters are such that the power converter s CM currents are reduced, resulting in lower CE and RE noise levels. The design of the CM filter should be such that the power converter meets the respective standards DM filters L-filter A series inductor (L) can be used as a low-pass filter, as shown in Fig The attenuation provided by L filter is -20dB/dec. The value of L is normally chosen such that the funda-

42 Filters for power converters mental voltage drop is not more than 10%. In some cases, it is not possible to meet the standard recommendation with an L filter. Figure 1.3: L-filter configuration LC-filter A series inductor (L) followed by a shunt capacitor (C), as shown in Fig. 1.4, is used as a filter in applications such as motor drive, uninterruptible power supply (UPS), voltage source inverter (VSI), etc. This filter is not normally used in grid-connected applications. In applications with high inductive load, LC filters act like LCL filters. The attenuation offered by the LC filter is -40dB/dec. Figure 1.4: LC-filter configuration LCL-filter LCL filters consist of two series inductors with a shunt capacitor connected in between, as shown in Fig They are widely used in grid-connected VSI applications. The LCL filters have an attenuation of -60dB/dec. Compared with L filters, LCL filters need a smaller inductance value for the same level of output ripple current. The basic guidelines for designing

43 Chapter 1. Introduction 9 Figure 1.5: LCL-filter configuration. the LCL-filter parameters are provided in [19, 20]. The converter-side inductor is designed based on tolerable current ripple. The LCL capacitor value is chosen based on the percentage of reactive power absorbed. The grid-side inductor is designed based on the high frequency current attenuation from the inverter side to the grid side Higher order filter The order of a filter is defined based on the number of passive elements in the filter. For instance, LCL filters are third-order filters as there are two inductors and one capacitor. Higher-order filters are used in some applications that have special filtering requirements [21 23] CM-filters Fig. 1.6 shows a typical CM-filter configuration. CM filters are practically low-pass filters for CM currents. CM filters can reduce RE and CE noise levels by reducing the CM current. These filters are designed based on power converter topologies and switching patterns used in the converter. The CM filters have to reduce the CM current below a certain level such that the EMI/EMC standards are met. In high power converter applications, normally the CM filters needed are quite bulky. However, proper design of power converters can eliminate or reduce the size of CM filters drastically Combined DM and CM filters In most of the configurations, the DM filters have some CM filtering effects also. For instance, in a three-phase system the effective CM filter with LCL filter is as shown in Fig In the effective CM filter, the value of inductors and capacitors is equal to the values of the

44 Filters for power converters Figure 1.6: A typical CM-filter configuration. parallel combination of inductors and capacitors. In most cases this is not sufficient, and a CM filter is needed to be added to the system. It is possible to modify the DM filters so as to get better effective CM filters. Hence, the CM filter can be eliminated or its size can be reduced. Figure 1.7: A typical CM-filter configuration Resonant oscillations All higher-order filters suffer from the resonant oscillations between passive components L and C. These oscillations cause losses and reduce the overall system efficiency. They can also cause instability in the system. To eliminate the resonance or reduce the magnitude of these oscillations, either passive or active damping can be used Passive damping In passive damping of the resonant oscillations, lossy components like resistors are added to the filter. The resistors are needed to dissipate the energy that causes the oscillations. This method is easy to implement and reliable, but the downside is the losses. Different passive damping circuit configurations are available that can reduce the losses in the damping

45 Chapter 1. Introduction 11 (a) (b) (c) Figure 1.8: Passive damping configurations. (a) Resistive damping, (b) split-capacitor resistive damping, and (c) split-capacitor inductive-resistive damping. circuit, as shown in Fig Fig. 1.8(a) shows the damping resistor R d in series with the filter capacitor. In this configuration, all the current components (fundamental, resonance, and switching components) pass through the resistor. In this case the losses in the damping resistor are high; it also degrades the performance of the filter. Fig. 1.8(b) shows the splitcapacitor resistive damping. The losses in this case are reduced by providing a path for the switching component through capacitor C 1. In Fig. 1.8(c) the split-capacitor inductiveresistive damping is shown. In this configuration, by properly designing the capacitances and inductance values, losses are minimized. This is done by passing the resonant component through the damping resistor and providing a path for other components Active damping In active damping methods, the resonant frequency current is controlled with the help of power converter controllers. The controller practically removes the excitation of the resonant

46 Approaches in the literature frequency from the source by injecting a same signal as the excitation but with opposite polarity. If resonant frequency excitations are removed from the source then the circuit cannot oscillate. The advantage of active damping is that it is a lossless method. The disadvantages of this method are that when compared with passive damping it is less reliable, it exerts extra computational burden on the controller, and there is a need for extra sensors in some cases. 1.5 Approaches in the literature Standards such as CISPR and IEC specify the limits of voltage disturbance on the mains by power converters for industrial, commercial, and domestic applications [5, 17]. This voltage disturbance is caused by current injection into the mains. Hence, to have the voltage disturbance within limits, current injection must be limited. NEMA MG-1, Part 31, recommends the maximum allowable dv/dt that can be applied at the motor terminal for safe operation [24] CM and DM filters for PWM rectifier To meet these recommendations, and to address the other problems related to IGBT-based ASD with PWM rectifiers, different solutions have been proposed [25 33]. To prevent voltage doubling and to reduce CM noise due to high dv/dt, an LC filter is added to the inverter that feeds an induction machine [25]. Different PWM methods and their CM voltage characteristics are studied in [26] with an objective of identifying the method with the lowest CM voltage. Clamping filter is employed in [27 29] to reduce the dv/dt, thus preventing voltage doubling at motor terminals. This also inhibits excitation of the parasitic capacitance of the cable and motor. Filter capacitors are introduced between dc bus positive rail to the ground and negative rail to the ground in [30, 31], which eliminates CM voltage due to PWM rectifier. This method cannot be used with conventional space vector pulse width modulation (CSVPWM), since the ground current would carry significant third harmonic in addition to switching components. In [32] a specific filter to eliminate the high frequency leakage current due to a grounded heat sink is presented, which requires RC networks to be connected between the grid star point, machine neutral point, and Y filter on the dc bus. The number of additional components required for the CM filter is high in this case.

47 Chapter 1. Introduction 13 A topology to reduce the conducted EMI noise as well as the dc-side leakage current is proposed in [22]. The circulating current can be high, and the proposed topology uses LLCL filter, which needs additional passive components. In [3] an ac CM choke is added at the output of the inverter to reduce the dc-side leakage current. However, the value of CM choke inductance itself is much larger than that of the output filter. In [1] ground current in a single-phase grid-connected inverter is evaluated with different PWM methods, and it is shown that the bipolar PWM method results in lower ground current when compared with unipolar PWM method. This configuration can be sensitive to nonidealities like switching delays in the legs of the inverter. In [34] the problems of EMI generated by a single-phase PFC are investigated. In [35] a new filter configuration to reduce the EMI noise level and leakage current is presented. The filter topologies need additional passive components. [36] proposes an active CM filter for reducing the ground leakage current in transformer-less single-phase grid-connected photovoltaic converters. This method needs additional magnetic components with a full-bridge converter. Different solutions [9,37 42] have been provided in the literature to reduce the ground leakage current as well as the EMI noise level to meet the respective recommendations [5, 6, 17]. In [9] a CM filter is presented for a three-phase PWM rectifier using CSVPWM. In [37,38] the impact of interleaving angle on EMI noise in parallel threephase VSI is presented. [39] investigates the conducted EMI using separate heat sinks for a silicon carbide JFET inverter for motor drive applications. In [40,41], modulation techniques for three-phase transformer-less inverters for photovoltaic applications are investigated. [42] presents the study of an alternative space vector modulation implementation for matrix converters to reduce the CM voltage Active and passive damping of resonant oscillations Higher-order filters, LCL filters, are preferred over lower-order L filters for their performance such as higher attenuation rate and smaller filter parameter values. The higher-order filters required to meet standard specifications are in general less bulky compared with lower-order filters. However, the higher-order filters have a tendency to oscillate at a particular frequency, referred to as resonant frequency, because of disturbances around these frequencies. Even a small disturbance produces large amplitude of oscillations if the damping in the filter is poor. The damping in the filter can be enhanced by appropriately introducing resistive elements; this is referred to as passive damping. Passive damping is simple to implement but has its

48 Approaches in the literature drawbacks. It increases the power loss and decreases the effectiveness of the filter. In order to decrease the power loss in the filters and to maintain their effectiveness it is desirable to damp the oscillations using a suitable control strategy, referred to as active damping. Active damping emulates the action of the resistors and damps the oscillations, and it is a lossless damping method. However, active damping methods can require additional sensors and increase the complexity of the control algorithm, which makes the system less reliable compared with passive damping. Various methods of implementing passive and active damping are discussed in [18,43 49]. In the passive technique a resistive branch, resistive-capacitive branch, inductive-resistive branch, or combinations of these networks are introduced in the filter structure [18,49]. The inclusion of resistive elements damps the oscillations and the resistance is chosen as a tradeoff between power loss and quality factor. The combination of a resistive element with a capacitor or an inductor helps in reducing the power loss and improves the performance of the filter [18]. The active damping methods based on virtual resistor, lead-lag compensation, notch filter, state space method, etc., have been widely studied in the literature [43 48]. The primary attraction of the active damping method is that it is lossless while maintaining the filtering effectiveness. The CM filtering requirements of the power circuit have so far been considered to be independent of the need to filter the line-to-line PWM output of the converter. Hence, the focus of the damping design in the literature has been on the investigation of active damping on a line-to-line basis or DM alone. However, if differential- and common-mode filtering can be integrated into a single-filter structure, then it becomes important to simultaneously address the concerns of both differential- and common-mode resonances of the filter Integrated CM inductor The system power level can be increased by paralleling smaller power converters [50 52]. Paralleling increases the power rating of the system. It also increases the reliability of the system by achieving higher system redundancy and availability [52]. The grid current distortion can be reduced through carrier interleaving [53 56]. Phase shifting the carrier of parallel converters shifts the harmonic components of the converters and can result in cancellation of certain harmonics. This also provides the ability to reduce the switching frequency at higher power levels for the interleaved converters and reduce switching losses.

49 Chapter 1. Introduction 15 However, carrier interleaving can cause circulation of current between the converters. The circulating current consists of low frequency as well as high frequency components. The low frequency component is close to the fundamental frequency and the high frequency component is around the switching frequency. The high frequency circulating current is due to turning on of the top switch of one converter and bottom switch of the second converter, which belong to the same phase group, at the same time. The low frequency component is due to output-voltage mismatch between the converters. This causes unbalanced load sharing in the parallel-connected converters. Circulation of current increases power loss, saturates the inductors, causes instability, and causes overstress or even damage to power devices. Several solutions have been proposed in the literature to control and limit the circulating current in parallel converters. In [57] an interleaved active power filter concept with reduced size of passive components is presented. In [58], inter-phase transformers for connecting power converters in parallel are analysed to reduce the circulating current. In [59] a zero-sequence current control loop is designed to suppress the circulating current. However, it only reduces the low frequency circulating current, and there is no control over the high frequency circulating current. In [31] a control method to limit the low frequency circulating current is presented; the high frequency circulating current is limited by the help of inter-phase inductors. In [2] a special inductor structure is proposed, which integrates the inter-phase inductor with the boost output inductor. However, the steps involved in the design procedure are not provided. The proposed inductor in [2] is not made of standard cores and needs special core geometry with unequal size of the core s legs, which makes it difficult to manufacture. Hence, there is need for a design procedure for integrated CM inductor. It is also highly desirable to be able to manufacture it out of standard magnetic cores. 1.6 Power converters topology and design aspects Topology A large number of converter topologies have been investigated in the literature [33, 60 64]: topologies like single-phase full and half bridge [61,63,64], three-phase full bridge [33,60], and multi-level inverters [62, 64]. Multi-level inverters have the advantages of requiring devices with lower voltage rating and also requiring smaller output filters compared with two-level

50 Power converters topology and design aspects inverters [64]. Two-level inverters are the most commonly used inverters and are considered in this thesis. The topologies considered in this thesis are as follows: In chapter 2, three-phase back-to-back connected to a three-phase VSI are used. In chapter 3, a three-phase grid-connected inverter is used. In chapter 4, a single-phase H-bridge back-to-back connected to a three-phase VSI and two parallel single-phase H-bridge grid-connected converters are used. In chapter 6, two parallel single-phase H-bridge grid-connected converters are used DM and CM filters As mentioned in Section 1.4, filters are needed to reduce the switching current and voltage ripple injected to the grid and to reduce the EMI/EMC noise level. To meet the respective standards [5,15 17] the DM and CM filters must be properly designed. There are several filter design methods available in the literature [19, 65 67]. In this thesis, three-phase and singlephase combined DM and CM, LCL-based filters are used for the grid-connected converters. Either dv/dt filter or LC filter is used at the load side Damping of the resonant oscillations The downside of the higher-order filters is the resonant oscillation between passive components L and C. The oscillations can be damped by either passive damping [18, 19, 49, 68] or active damping [43 48]. The damping strategy used in this thesis, in chapters 2, 4, and 6, is split-capacitor passive damping [18]. Active damping of the DM and CM resonant oscillations [69] is used in chapter Modulation technique PWM techniques convert the reference voltage to pulses with the same average voltage as the reference voltage. Different PWM techniques, such as sine triangle, harmonic injection, space vector based, multi-level PWM, and PWM with carrier interleaved techniques, are available with their own advantages and disadvantages [70 75]. The PWM techniques used in this thesis are as follows: In chapter 2, CSVPWM for grid-connected inverter and sine-triangle modulation technique for the motor drive inverter are used.

51 Chapter 1. Introduction 17 In chapter 3, CSVPWM is used for the grid-connected inverter. In chapter 4, unipolar and bipolar sine-triangle PWM techniques for the grid-connected inverter, and sine-triangle modulation technique for the motor drive inverter, are used. In chapter 6, unipolar sine-triangle PWM technique with carrier interleaved is used Phase locked loops Phase locked loops (PLLs) are used to generate the unit vectors, sine and cosine, from the sensed grid voltage. The generated sine and cosine unit vectors are synchronized with phase and frequency of the grid voltage. The unit vectors are essential for operation of gridconnected converters where full control of active and reactive power flow is needed. Several PLLs have been proposed in the literature in order to improve its performance [76 79]. In this thesis, synchronized reference frame (SRF) PLL is used for grid-connected converters and second-order generalized integrator (SOGI) PLL is used for single-phase grid-connected converters Voltage controller A constant dc voltage is essential for normal operation of power converters. A voltage controller is used to control the dc-bus voltage and to have the desired constant voltage. Methods for controlling the dc-bus voltage of power converters are proposed in the literature [80 84]. A simple PI controller is used in this thesis to regulate the dc-bus voltage Current controller Current controller is used to regulate the power converter current to a desired value. The current controller should have ideal tracking over a wide frequency range, a high dynamic response, low harmonic content in the current, and the capability to work under nonideal grid conditions. Several current control methods have been proposed in the literature based on stationary reference frame, hysteresis, predictive, proportional resonant, resistance emulation current control [85 89]. The current controllers used in this thesis are PI current controller in SRF for three-phase converters and proportional-resonant (PR) controller for single-phase converters [85, 86].

52 Scope of the work 1.7 Scope of the work In this thesis, the CE noise and leakage current of single-phase and three-phase grid-connected converters are studied. The work touches upon combined DM and CM filter design, active damping design, and magnetic component design. Details of the studies conducted are given below: 1- CM filter design for PWM rectifier based motor drive IGBT-based ASDs using diode bridge front-end rectifier or PWM rectifier are widely used. When regenerative capabilities are needed, the PWM rectifier is the suitable alternative [19, 90]. The PWM rectifier eliminates lower-order harmonics compared with the diode bridge rectifier. However, it injects high frequency electrical noise to the grid. High dv/dt due to fast turn on and turn off of the IGBT excites parasitic capacitive coupling in the motor drive. This leads to increased line currents and causes problems such as terminal overvoltage, insulation stress, shaft induced voltage, bearing currents, and EMI/EMC [55,91 101]. Inverters with fast switches, such as IGBTs, are the root cause of the aforementioned problems. These problems get worse in the presence of a PWM rectifier as the CM voltage is doubled. This effect becomes even more predominant as PWM rectifiers are switched at frequency in the order of ten khz. The electrical noise produced by a PWM rectifier, along with the electrical noise due to a PWM inverter, appears at the motor load terminals and leads to higher CM current. A CM filter is essential to keep the electrical noise generated by the motor drive within the specified limits. 2- Active damping Passive filters are necessary in order to meet the standards for grid-connected applications [5, 15 17]. Issues such as switching ripple, ground current, etc., are addressed using either passive or active filtering or a combination of these filtering techniques [19, ]. These passive filters are connected between the grid and the PWM rectifier; the filters used for this purpose are L or LCL [18,19,104]. Higher-order filters, LCL filters, are preferred over lower-order L filters for their performance such as higher attenuation rate and smaller filter parameter values. The higher-order filters required to meet the standards are in general less bulky compared with lower-order filters. However, higher-order filters have a tendency to oscillate at a particular frequency, referred

53 Chapter 1. Introduction 19 to as resonant frequency, because of disturbances around these frequencies. Even a small disturbance produces large amplitude of oscillations if the damping in the filter is poor. The damping in the filter can be enhanced by either passive damping or active damping. Various methods of implementing passive and active damping are discussed in [18, 43 49]. Passive damping is simple to implement but has its drawbacks. It increases the power loss and decreases effectiveness of the filter. Active damping emulates the action of the resistors and damps the oscillations; it is a lossless damping method. However, active damping methods may need additional sensors and increase the complexity of the control algorithm, which makes the system less reliable compared with passive damping. 3- Effect of modulation scheme on EMI and ground leakage current Ground leakage current and EMI filtering in power converters are important design aspects of power electronic converters. The use of grid-connected power converters is increasing in applications such as battery chargers, regenerative drives, front-end converters for renewables, PWM rectifiers, active filters, and PFC [ ]. One reason for the popularity of power converters is that they work very efficiently. As the technology of IGBTs and other switches advances, it is possible to operate power converters at a higher frequency and high efficiency. However, very fast switching action generates high dv/dt. This will excite the parasitic capacitances and increase the challenge in designing power converters with low ground leakage current and minimal EMI/EMC issues [39, 40, 109]. In the case of motor drive applications, high dv/dt due to switching action can cause problems like high EMI noise level, voltage doubling, current leakage, and bearing current [95, ]. These problems are especially severe when long cables are used to connect the power converters to the motors. The ground leakage current has a tight limit. Because of safety reasons, this limit is even more stringent for domestic applications. One of the standards for the leakage current is VDE V for photo-voltaic (PV) systems. It recommends that if the leakage current is higher than 300mA, the system must be disconnected within 0.3 seconds [6]. High dv/dt caused by the switching action injects narrow peaky current to ground. The leakage current has harmonics from switching frequency to very high frequency. One of the major challenges faced during the designing of power converters is to meet

54 Experimental setup the respective standards for EMI/EMC and leakage current. Often a bulky EMI filter is needed to meet the specifications of the standards. This increases the cost and size of the overall system and reduces the overall system efficiency. Modulation methods have a direct effect on the EMI/EMC noise and ground leakage current. Different modulation techniques have different leakage and EMI/EMC signatures. Several studies have been done on investigation of modulation methods and their effects on the EMI/EMC noise and ground leakage current [1, 37, 38, 40 42]. 5- Inter-phase inductors Paralleling increases the power rating of the system. It also increases the reliability of the system by achieving higher system redundancy and availability [52]. The grid current distortion can be reduced through carrier interleaving [53 56]. Phase shifting the carrier of parallel converters shifts the harmonic components of the converters and can result in cancellation of certain harmonics. This also provides the ability to reduce the switching frequency at higher power levels for the interleaved converters and reduces the switching losses. However, carrier interleaving can cause circulation of current between the converters. The circulating current consists of low frequency as well as high frequency components. The high frequency circulating current is limited by adding an inter-phase inductor between the same phases of the paralleled converters. It is also advantageous to integrate the inter-phase inductor and the boost inductor used in the output filter. 1.8 Experimental setup Two 10kVA three-phase back-to-back connected, one 5kVA single-phase, and one 7.5kVA parallel single-phase power converters have been built in the laboratory for the experimental studies. The protection and delay cards, the gate driver cards, voltage and current sensor cards, and the controller board were developed earlier in the laboratory. The controller board is powered by a field-programmable gate array (FPGA) Altera Cyclone II. More details about the hardware setup are provided in Appendix B.

55 Chapter 1. Introduction Organisation of the thesis Chapter 1 gives an introduction to EMI/EMC and the CE and RE. The DM and CM voltage and current definitions are presented. DM and CM filters and the need for damping in higher-order filters are briefly explained. A survey of research and the scope of the work are presented. The experimental setup used in the work and the flow of the thesis are explained. Chapter 2 discusses the design of CM filter, based on the LCL-filter topology and component selection procedure. CM voltage and CM current of ASD are explained. dv/dt filters are briefly discussed. Procedures for designing the CM filter are explained in detail. CM equivalent circuits are used in the analysis. Frequency domain analyses are used for selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the discussed circuit. Passive damping is presented for CM and DM, and the losses in the damping resistor are evaluated. Experimental results based on EMI measurement on the grid side and CM current measurement on the motor side are presented. Chapter 3 discusses the control of three-phase PWM rectifiers. Current control, voltage control, and unit vector generation are explained. An active damping strategy that damps the oscillations in both line-to-line and line-to-ground is developed. An approach based on pole placement by state feedback used to actively damp both differential- and commonmode filter oscillations is detailed. Analytical expressions for the state-feedback controller gains are derived for both continuous- and discrete-time models of the filter. Trade-off in selection of the active damping gain on the lower-order power converter harmonics is analysed using weighted admittance function. Experimental results on a laboratory prototype PWM rectifier are presented. Chapter 4 consists of two parts. The first part discusses an LCL filter topology for a single-phase PWM rectifier that makes use of bipolar PWM method for a single-phase to three-phase motor drive. This filter topology is shown to be insensitive to nonidealities like switching delays between the legs of the inverter. The discussed topology eliminates high dv/dt from the dc-bus CM voltage by making it sinusoidal. Hence, the high frequency CM current injection to the ground as well as the motor-side CM current is minimized. It is shown that the filter configuration makes the system insensitive to nonidealities; it also reduces the load-side CM current. Different variants of the filter topology are compared to establish the effectiveness of the filter circuit. Experimental results based on EMI measurement on the

56 Summary grid side and CM current measurement on the motor side are presented for a motor drive prototype built in the laboratory. The second part discusses a new method to make the CM voltage of a parallel single-phase grid-connected inverter sinusoidal and free of high frequency pulses. The discussed method consists of two parallel-connected H-bridge power converters, which use unipolar PWM with carrier interleaved. The CM equivalent circuit is formulated from the current and voltage analysis. An expression for the dc-side CM voltage (dc-bus midpoint to ground) is derived for a parallel single-phase converter with LCL filter. A method is proposed by which the CM voltage is made sinusoidal. This is done by using unipolar PWM and interleaving the carrier of the parallel-connected converters by an angle of 180. A novel modification to the LCL filter in the circuit is discussed that further reduces the leakage current. The experimental tests are carried out on a parallel single-phase PWM rectifier. Chapter 5 explains the EMI and ground current measurements. LISN and the components used in LISN are detailed. The circuit configuration using LISN for single-phase and three-phase EMI measurements is presented. Different methods for ground current measurements are explained. The experimental results are presented. Chapter 6 discusses a CM design method for parallel interleaved converters, which combines the inter-phase and boost inductors together. Step-by-step design procedure, which reduces the size and weight of the CM inductor, is provided. The discussed design reduces the size and cost of the overall system. A design example is given and compared with the available designs in the literature. It is shown that the available design procedure introduces constraints on the core geometry that are not suitable for high power designs. The discussed design makes use of standard cores, which improves manufacturability. The finite element method (FEM) analysis is carried out to verify the theoretical design analysis. The proposed integrated inductor is compared with separate boost and inter-phase inductors. Experimental results on a parallel single-phase converter are presented Summary In this chapter, an introduction to electromagnetic interference is given. DM and CM current and voltage analyses are explained. Different output filters for power converters and the need for resonant damping are provided. The converter topology and the design aspects are briefed. A literature survey is presented. Scope of the work is listed. Experimental setup for

57 Chapter 1. Introduction 23 experimental validations and the flow of the thesis are provided. Organization of the thesis and the summary are given.

58 Summary

59 Chapter 2 Common Mode Filter Design for PWM Rectifier Based Motor Drives Grid-connected power converters are being increasingly utilized in applications like PWM rectifiers, active filters, motor drives, battery chargers, renewables, etc. There are concerns about CM current in particular when the motor drive uses a regenerative active front-end (AFE) rectifier. In the case where the motor is connected to the inverter with long cables, the issue of dv/dt and CM voltage is another important concern. In this chapter, the increase in CM voltage in a motor drive with PWM rectifier is analysed. An approach for CM filter design is discussed wherein the adverse effects of both PWM rectifier and the inverter are addressed. The explained filter topology is based on an LCL grid-side filter with its star point connected to the dc bus and ground. A number of variants of the filter topology are studied to evaluate the effectiveness of the solution. Passive damping is introduced to damp the resonant oscillations in DM and CM circuits. A laboratory experimental drive system has been built, which is used to evaluate the filtering performance. Conducted noise emission tests have been carried out with different CM filter topologies, and the results show the effectiveness of the filter design. 2.1 Adjustable speed drive Three-phase ASDs are used in applications where the motors need to be run at variable speed and torque or for running a three-phase motor with a single-phase grid. In gridconnected ASD the setup consists of two power conversion parts as shown in Fig The first part converts three-phase or single-phase ac power to dc. Diode bridge rectifier (DBR), thyristor bridge rectifier (TBR), or active rectifier can be used in this part. Three-phase 25

60 Adjustable speed drive Figure 2.1: Three-phase grid-connected adjustable speed motor drive. power converters are used to convert the dc power back to ac power. With the help of the power converters the output voltage and frequency are controlled. Hence, the speed and torque of the motor are controlled. The configuration shown in Fig. 2.1 is a three-phase to three-phase grid-connected ASD. Different variants of the grid-connected ASD, depending on the number of phases and based on the applications, are used. In normal operation mode of the ASD, power is transferred from the grid side to the motor side. In the regenerative mode (braking mode), power is pumped back to the grid. This is only possible if an active rectifier is used for converting ac to dc. Figure 2.2: Three-phase off-grid adjustable speed motor drive. In off-grid applications, like an electric car, the first power conversion part is not needed and dc power is directly supplied to the power converter, as shown in Fig DC power can be supplied from a battery bank or other dc power sources. Combining these sources into a hybrid system is also possible. In some cases, dc-dc power converters are needed to adjust the dc source output voltage to a desired voltage.

61 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 27 Figure 2.3: Three-phase PWM rectifier connected to grid using L filter Three-phase diode bridge rectifier The simplest and most efficient way of converting ac power to dc is by using DBRs. They are simple because control is not needed. They are very efficient as they do not have any hard switching actions. The disadvantages of TBR and DBR are that they operate at very high THD and inject significant amount of lower-order harmonics to grids. Voltage ripple appears at the output dc side. There is no control on active and reactive power flow, and it is not possible to have reverse power flow in case of a DBR. The current drawn from the grid is narrow and peaky for a DBR with large capacitive filter Three-phase PWM rectifier Different names are given to grid-connected ac-to-dc power converters, such as active rectifier, PWM rectifier, front-end converter (FEC), AFE rectifier, etc. PWM rectifiers are capable of bidirectional power flow. It means that they can convert ac to dc and dc to ac. This is very important in motor drive applications, when the regeneration takes place because of braking action. Fig. 2.3 shows a three-phase PWM rectifier connected to grid through L filter. In PWM rectifiers, the active switches are used to control the rectifier voltage v i. Filters are essential to reduce the switching ripples. Normally, L or LCL filters are used in grid-connected applications.

62 Adjustable speed drive (a) (b) Figure 2.4: (a) Single-line equivalent circuit of a PWM rectifier connected to grid using L filter and (b) phasor representation of (1) Principle of PWM rectifier The PWM rectifier voltage v i is controlled by controlling the switching states. By controlling the phase and the magnitude of v i it is possible to control the phase and the magnitude of current flow i g, hence controlling the active and reactive power flow. The single-line equivalent circuit of Fig. 2.3 is shown in Fig. 2.4(a). The PWM rectifier is represented as a pulsed voltage source v i. The phasor expression corresponding to Fig. 2.4(a) is given in (1) and its phasor representation is shown in Fig. 2.4(b). Nonideal resistance of the filter is neglected for simplicity. L here represents the total inductance value between the grid and the rectifier. The control of PWM rectifier is explained in detail in [115] and briefly explained here. Fig. 2.4(a) shows two sources connected together by an inductor. In this kind of configuration, the reactive power flows from the source with higher voltage to the source with lower-magnitude voltage. The active power direction is from the source with greater phase angle to the source with the smaller phase angle. By controlling the phase and the magnitude of the active rectifier voltage v i, the active and reactive power flows are controlled independently. In this chapter, three-phase PWM rectifier is used in ASD to convert ac power to dc. v i = v g jωli g (1)

63 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 29 Figure 2.5: Phasor diagrams of a PWM rectifier under different operating modes. (a) Unity power factor, (b) lagging power factor, (c) regeneration at unity power factor, (d) leading power factor, (e) regeneration at leading power factor, and (f) regeneration at lagging power factor PWM rectifier control In applications with two ac sources connected together with a reactance, as shown in Fig. 2.4(a), the reactive power flows from the source with higher-magnitude voltage to the source with lower voltage. The active power flows from the source with greater phase angle to the source with smaller phase angle. In Fig. 2.4(a), the PWM rectifier is represented as

64 Adjustable speed drive Table 2.1: Different modes of operation and power flow directions of PWM rectifiers Case Mode of Operation Active Power Flow Reactive Power Flow A Unity Power Factor (PF) ac to dc Zero B Lagging PF ac to dc to inverter C Regeneration at Unity PF dc to ac Zero D Leading Power Factor ac to dc to ac grid E Regeneration at Leading PF dc to ac to ac grid F Regeneration at Lagging PF dc to ac to inverter a pulsed voltage source. The PWM rectifier s working principle is based on controlling the phase and the magnitude of the pole voltage independently. By this means, it is possible to control the flow of active and reactive power independently in either direction and regulate the dc-bus voltage. The formula representing Fig. 2.4(a) is given in (1). The PWM rectifier can work in different modes of operations. The phasor representations of the modes are shown in Fig The modes and the direction of active and reactive power flows are tabulated in Table 2.1. The notation ac to dc means that the PWM rectifier draws power from the grid and dc to ac means that the PWM rectifier pumps power to the grid. The resistance of the filter inductors is assumed to be very small. Hence, this is neglected and not considered in the preliminary analysis. Unity power factor (UPF) operation of the PWM rectifier is shown in Fig. 2.5(a). It can be seen that, for UPF operation, the PWM rectifier should generate a v i that is lagging v g by ϕ = tan 1 ( ωlig v g ), with a magnitude equal to v i = vg 2 + (ωli g ) 2. The phase and the magnitude of v i generated by the PWM rectifier are dependent on the grid voltage v g and the voltage drop across filter inductors (ωli g ). Hence, the phase angle and the voltage magnitude of v i must be accordingly adjusted LCL filter Filters are essential in PWM rectifiers to reduce the switching current and voltage ripples. Higher-order filters, like LCL filters, are preferred over lower-order L filters. This is due to higher attenuation offered to the ripples by higher-order filters. The disadvantage of higherorder filters is that they suffer from resonances. These oscillations need to be damped either

65 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 31 Figure 2.6: Per-phase equivalent circuit of an LCL filter. by passive or active means. Transfer function ig v i of the LCL filter, shown in Fig. 2.6, is given by (2). The Bode plot of transfer function ig v i is plotted in Fig The grid is assumed to act as a short circuit for the frequencies other than the fundamental frequency. It can be seen from Fig. 2.7 that the attenuation offered to the frequencies higher than the resonant frequency (1kHz) is -60dB/dec. In Fig. 2.7 the resonant frequency is at 1kHz. If the switching frequency is kept at 10kHz, then the attenuation offered to the grid-side switching frequency current ripple would be -90dB. i g v i = 1 L g L i Cs 3 + (L g + L i )s (2) dv/dt filters Because of fast turn on and turn off of the IGBTs, high dv/dt is produced. This causes voltage doubling at the motor terminals when long cables are used to connect the motor to the inverter. This can be eliminated by decreasing the dv/dt of the voltage applied to the motor terminals. To avoid voltage doubling, the rise time of the applied voltage should be greater than the propagation time of the forward travelling voltage wave. The propagation time depends on the length and insulation material of the cable. The rise time is controlled with the dv/dt filter such that it is greater than the propagation time of the voltage wave in the cable. A lower dv/dt mitigates the voltage doubling phenomena at the motor terminals and this reduces the CM current. In dv/dt filters, the resonant frequency is placed above the switching frequency such that it still meets the required dv/dt limit, such as NEMA MG standards [24]. In this design, the

66 Adjustable speed drive Magnitude Frequency (Hz) Figure 2.7: C =20µF. Bode magnitude plot of transfer function ig v i, where L g = L i =2.5mH and resonant frequency of filter is selected such that the dv/dt is reduced effectively. As a result, voltage doubling is eliminated at the motor terminal. The high resonant frequency of the dv/dt filter reduces the size and cost of the filter. The impact of PWM inverter on induction motor has been extensively outlined [55, ], and a variety of solutions involving dv/dt filter designs for the motor-side inverter with diode front-end rectifier have been suggested. Methods for dv/dt filter design have been discussed in the literature [27 29, 116]. Impact of the cable length and target dv/dt on selection of the filter parameters is given as a general design procedure in [28]. The overall filter accomplishes the objective of limiting the dv/dt applied at the motor terminals because of both PWM rectifier and the drive inverter. Stepby-step design of dv/dt filter is presented in [116].

67 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 33 Figure 2.8: Schematic of grid-connected ASD with LCL filter, dc bus CM filter, and dv/dt filter at inverter terminal for the motor load.

68 Common mode circuit analysis Figure 2.9: Schematic of PWM rectifier with LCL filter The topology for the analysis Fig. 2.8 shows the schematic of a grid-connected ASD. In the shown topology, LCL filter is used at the grid side. Split-capacitor resistive passive damping method is used to damp the resonant oscillations in LCL filter. A three-phase AFE rectifier or PWM rectifier is used to convert ac to dc. A three-phase three-leg power converter is used to convert dc to ac. A dv/dt filter is used at the output of the power converter and it is connected to the motor with the help of 100m cables. This topology is used for the analysis in this chapter. 2.2 Common mode circuit analysis The CM circuit is the representation of power circuit with respect to ground. It helps in understanding the CM current s paths and design of CM filters. The CM circuit for PWM rectifier shown in Fig. 2.9 is obtained in this section. The CM equations are derived by writing KVL for each phase. di ag e ag + L g dt + L di ai i dt + V AO + V Og = 0 (3) e bg + L g di bg dt + L i e cg + L g di cg dt + L i di bi dt + V BO + V Og = 0 (4) di ci dt + V CO + V Og = 0 (5)

69 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 35 Adding (3), (4), and (5) results in (6) d(i ag + i bg + i cg ) (e ag + e bg + e cg ) + L g + dt d(i ai + i bi + i ci ) L i + (V AO + V BO + V CO ) + 3V Og = 0. (6) dt In balance three-phase e ag + e bg + e cg = 0, the equation (6) simplifies to, 0 + L g 3 di comg dt + L i 3 di comi dt + V AF E + V Og = 0 (7) where, I comg = i ag + i bg + i cg I comi = i ai + i bi + i ci V AF E = V AO + V BO + V CO. 3 The KVL from the grid to the LCL capacitors results in, Adding (8), (9), (10) and simplifying it results in (11) e ag + L g di ag dt + V ac + V N g = 0 (8) e bg + L g di bg dt + V bc + V N g = 0 (9) e cg + L g di cg dt + V cc + V N g = 0. (10) L g 3 di comg dt + V comc + V N g = 0 (11) where, V comc = V ac + V bc + V cc. 3 By writing KCL at LCL capacitors nodes we have, i ag i ai = i ac (12) i bg i bi = i bc (13) i cg i ci = i cc. (14)

70 CM analysis of ASD Figure 2.10: CM equivalent circuit of the PWM rectifier shown in Fig Adding the aforementioned three equations results in, I comg I comi = I comc = C d(v ac + V bc + V cc ) dt = 3C V com C dt. (15) With the help of (7), (11), and (15) the CM equivalent circuit is obtained and shown in Fig The capacitors C p1 and C p2 represent the parasitic capacitances of semiconductor collector to base plate of the switch module package. It can be seen from Fig that a standard LCL filter with open capacitor neutral point or with capacitors connected in delta acts as an L filter in CM equivalent circuit. If the capacitors of LCL filter are connected in delta, the CM current cannot flow through them. Hence, the capacitors act as open circuit in CM equivalent circuit. This is also the case when the capacitors are connected in star with floating neutral point, as shown in Fig However, in this case, the path for the CM current can be provided by connecting the neutral point to ground. In that case, the point N, in Fig. 2.10, would be connected to ground. 2.3 CM analysis of ASD CM voltage and CM current of ASD using DBR When a DBR is used in an ASD, the CM voltage seen at the dc bus varies slowly with low magnitude and low dv/dt. As a result, the effect of the diode bridge on ground currents can be neglected. This is not the case for a PWM rectifier, which switches at high frequencies.

71 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 37 The CM voltage applied to the motor terminals by the inverter is represented mathematically by (16) and is shown in Fig. 2.11(a). V inv = (V UO + V V O + V W O ) 3 (16) The CM voltage varies in steps of V dc /3 with frequency the same as switching frequency. Because of motor parasitic capacitance C pm, which is of the order of a few tens of nf (for motor with the power range of the order of tens of kw), current is injected to the ground at each step change in the CM voltage. In the case of motors connected with a long cable, C pm represents the effective parasitic capacitance to ground of motor and cable [28]. The current injection into ground through the parasitic capacitance is given by (17). The waveform of CM current due to CM voltage is as shown in Fig. 2.11(b). dv inv i g = C pm dt (17) V com = V inv + V Og (18) CM voltage and CM current of ASD using PWM rectifier When a PWM rectifier is adopted as an FEC, the CM voltage produced at the dc bus cannot be neglected. The CM voltage due to PWM rectifier and inverter appears at the neutral of the motor, as expressed in (18). This worsens the problems caused by CM voltage on the motor. The PWM rectifier switching frequency is selected such that the grid current ripple is kept within the limits specified by IEEE 519. To reduce the size and cost of grid-side filter, the PWM rectifier is switched at a high frequency (order of 10kHz) [19]. The motor drive inverter switching frequency is related to RMS current ripple and speed ripple caused by torque pulsations. The motor leakage inductance filters the current ripple, and torque pulsations are filtered by the motor and shaft mechanical time constants. Hence, the inverter for high power motor drive is typically switched at a lower switching frequency (order of 1kHz) compared with the PWM rectifier. The CM voltage due to inverter, PWM rectifier, and the combined effect of both are illustrated in Fig. 2.11(a), (c), and (d), respectively. When the combined effect is considered, the CM voltage magnitude transits between ±V dc, ± 2V dc 3, ± V dc 3, and 0.

72 CM analysis of ASD (a) (b) (c) (d) (e) Figure 2.11: Waveforms illustrating (a) CM voltage due to drive inverter alone, (b) resulting CM current due to the presence of parasitic capacitance, (c) CM voltage due to PWM rectifier switching at higher frequency than the inverter, (d) CM voltage due to combined effect of inverter and PWM rectifier, and (e) CM current with PWM rectifier ASD due to the presence of parasitic capacitance.

73 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 39 Compared with the case illustrated in Fig. 2.11(b), the frequency of current injection into ground is increased due to CM voltage appearing at motor neutral when PWM rectifier is used as shown in Fig. 2.11(e). It is important to note that practically the current injected to ground would oscillate due to capacitive and inductive parasitics, which would be damped rapidly. However, a steep change in voltage due to PWM rectifier operation can occur before the ground current goes to zero. As a result, it increases the magnitude of ground current. One of the causes for increase in shaft voltage is high-frequency flux produced due to CM current. Therefore, the problem associated with shaft voltage and bearing currents gets aggravated when a PWM rectifier is used as FEC in an ASD. 2.4 Design of the CM filter The filter design procedure to address the CM voltage is outlined. Analysis of filter with capacitors C y1 and C y2 is discussed based on CM equivalent circuit. The CM filter is shown in Fig It consists of capacitors C y1 and C y2 between positive rail and negative rail of dc bus. Capacitor C Mg is connected between midpoint M and ground. The midpoint M is connected to the star point of the capacitors in LCL filter. The star point of the LCL filter is labelled N. The objectives of the capacitors C y1 and C y2 are to prevent the CM voltage of PWM rectifier from appearing at the load end and to circulate the switching and lower-order frequency currents within the rectifier circuit. This filter arrangement allows advanced PWM techniques, such as CSVPWM, to be adopted for PWM rectifier operation. The design procedure given here leads to third harmonic circulating current, in the filter inductors, to be less than 3% of the rated current. A capacitor C Mg is introduced into the CM filter between the point M and the ground. The role of C Mg is to bring down the potential of the point M as close as possible to ground potential. The parameters of the filter are derived with the help of CM equivalent circuit of the PWM rectifier. Fig shows a grid-connected PWM rectifier along with the CM filter. The CM equivalent circuit of Fig is obtained as follows. Writing KVL for dc bus capacitors C y1 and C y1, V Og V dc 2 + V P M + V Mg = 0 (19) V Og + V dc 2 + V NM + V Mg = 0. (20)

74 Design of the CM filter Figure 2.12: Schematic of grid-connected PWM rectifier with LCL filter and CM filter. Adding (19) and (20) and simplifying it results in, V P M + V NM 2 = V Og V Mg = V OM. (21) Writing KCL for dc bus capacitors C y1 and C y1, I comi = I com = i Cy1 + i Cy2 = C y1 dv P M dt + C y2 dv NM dt = C y d(v P M + V NM ) dt (22) where, C y = C y1 = C y2. Substituting (21) in (22) results in, I comi = 2C y dv OM dt = C b dv OM dt (23)

75 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 41 (a) (b) Figure 2.13: CM equivalent circuits of the PWM rectifier excluding the passive damping resistor, (a) without IGBT module parasitics and (b) with IGBT parasitic capacitors. where, C b = 2C y. Writing KCL at point M results in, I comc + I com = I Mg dv Mg = C Mg. (24) dt Using (23), (24), and the CM equivalent circuit derived in Section 2.2, the CM equivalent circuit of Fig is obtained. The CM equivalent circuit, excluding the damping resistors, of the PWM rectifier shown in Fig is shown in Fig. 2.13(a). Where, V AF E = (V AO +V BO + V CO )/3 is the CM voltage of the PWM rectifier. In Fig. 2.13(b), the parasitic capacitances C p1 and C p2 of the IGBT device to the module base plate are also shown. The values of the parasitic capacitances can be obtained from manufacturer s datasheet [117]. In the CM filter topology, the midpoint M is connected to the star point of the LCL filter N. Through this connection, the switching frequency and the lower-order harmonics will be circulated within the drive system, as can be observed in Fig. 2.13(a). In addition,

76 Design of the CM filter Figure 2.14: Low frequency approximation of CM equivalent circuit of the filter. the impedance of capacitor C Mg limits the injected ground current. If the midpoint M is left floating, the voltage of this point can increase substantially, which is not desirable. If the midpoint is connected to the ground, low frequency current, due to advanced PWM technique, will flow to ground. The selection of C Mg involves a trade-off between the magnitude of the voltage V Mg that occurs between node M and ground and the magnitude of the injected ground current. It can be seen from Section that the required value of C Mg to keep V Mg low is very small. Hence, the injected ground current also has a small magnitude in the filter topology. The filter CM equivalent circuit shown in Fig. 2.13(a) has C a = 3(C + C d ), C b = 2C y, L a = Lg 3, and L b = L i Selection of C y1 and C y2 The capacitor C Mg is very small, of the order of tens of nf. So, at low frequency it acts as an open circuit. The CM circuit at low frequency can be approximated as shown in Fig Hence, the currents through C a and C b are approximately equal. The transfer function of I com(s) V AF E (s) is given in (25) where, C S = CaC b C a+c b. I com (s) V AF E (s) = SC S S 2 L b C S + 1 (25) The admittance magnitude plot of the transfer function given in (25) is plotted in Fig for different values of C y1 and C y2. It can be seen that the third harmonic voltage due to advanced PWM sees an attenuation of approximately -37dB, for C y = 10µF. This keeps the circulating current small. The resonant frequency of the filter, for low frequency approximation circuit, is given by ω com = 1 Lb C S. The resonant frequency is selected such that it is not excited by the low frequency component of the CM PWM spectrum. Additionally, ω com should be kept below the switching frequency with sufficient frequency separation to avoid

77 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives Cy=10uF Cy=40uF Cy=100uF Magnitude Frequency(Hz) Figure 2.15: Admittance magnitude plot of I com(s) V AF E (s) for different values of effective C y. A lower admittance of the filter will lead to smaller internal circulating current. amplification of switching harmonics due to resonance. The resonant oscillations need to be damped with the help of either active or passive damping. The active damping is preferred because of its lossless nature. To achieve active damping, the sampling frequency should be greater than double the frequency that needs to be damped. The sampling frequency is kept same as switching frequency of PWM rectifier, hence ω com < ω SW 2. The following condition is obtained for the CM filter resonant frequency. 1 Lb C a < ω com < ω SW 2 (26) Small capacitance value, of the order of tens of nf, cannot be used for C y1 and C y2 in the filter configuration because of the following: 1) the CM switching frequency voltage of the PWM rectifier would propagate to the load side and 2) the resonant frequency will shift to higher value, and any resonance would need to be passively damped. A filtered dc bus to ground voltage, which is required, can be obtained by keeping the capacitors C y1 and C y2 sufficiently large to meet the frequency constraint in (26).

78 Design of the CM filter 50 0 Cmg=10nF Cmg=50nF Cmg=100nF -50 Magnitude Frequency(Hz) Figure 2.16: Frequency response plot of I Mg (s) V AF E (s) for different values of C Mg Selection of capacitor C Mg The transfer function I Mg(s) V AF E is obtained from Fig. 2.13(a) and is given in (27). The Bode (s) plot of (27) for different values of C Mg is shown in Fig From the Bode plot it can be seen that at high frequency sufficient attenuation is offered by the filter. where, I Mg (s) V AF E (s) = αc a ( S4 L al b α S α = 1 C a C b + 1 C g C b + 1 C g C a β = L a C a + L a C b + L b C b + L b C g. + S2 β α + 1) (27) A second resonance due to C Mg occurs at a frequency higher than switching frequency, which needs to be damped passively. At high frequency, impedance offered by L a and L b is very high. Therefore, they can be approximated with an open circuit. On the contrary, the capacitors C b and C S offer very low impedance and they are approximated with the short circuit. The high frequency approximation of the CM equivalent circuit of Fig. 2.13(b) is given in Fig C Mg will reduce the potential between M and ground. From Fig it can be seen that the voltage is divided between C p1, C p2, and C Mg as given in (28).

79 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 45 Figure 2.17: High frequency approximation of CM equivalent circuit of the filter. V Mg V AF E = C P 2 C P 1 + C Mg + C P 2 (28) By keeping the value of C Mg reasonably high in comparison with C p1 and C p2, the voltage V Mg is reduced. However, a very large value of C Mg will lead to higher ground currents. A C Mg that gives an attenuation of 95% based on (28) is adequate for the design. The values of C y1, C y2, and C Mg are listed in Table Passive damping design The analysis and discussion given below are from the perspective of damping, harmonic performance, and power loss in the filter. A wide range of passive damping circuit topologies are available in the literature [49]. In this study, the passive damping shown in Fig is adopted because of its low power loss and its quality factor while maintaining adequate stability with the grid [22, 118]. In this work the effects of the passive damping circuit in terms of DM and CM damping of the filter are investigated and the corresponding power loss is evaluated DM filter passive damping Fig. 2.8 shows the LCL filter interface between grid and PWM rectifier, which reduces switching current ripple injection into the grid. The design of the LCL filter follows the guidelines suggested in [18]. The advantage of LCL filters over L filters is that they have an

80 Passive damping design Table 2.2: Designed CM dc-bus filter values SL.NO. PARAMETER PER UNIT ACTUAL 1 DC bus voltage V dc V 2 PWM Rectifier Switching kHz Frequency f sw 3 LCL Filter resonant 20 1kHz Frequency f res 4 CM Filter Resonant kHz Frequency f com 5 Filter Inductance L g = L i mH 6 Filter Capacitance C = C d µF 7 DC Bus Filter C y1 = C y µF 8 Filter Capacitor C Mg nF 9 Damping Resistance R d Ω attenuation of -60dB/dec for frequencies higher than the resonant frequency f res. However, they suffer from oscillations between the passive L and C components. These oscillations are due to a pair of undamped complex-conjugate poles on the imaginary axis. To damp these oscillations, the undamped poles should be shifted to the left-hand side of the imaginary axis. This is done by introducing a damping resistor to the filters. Fig shows the LCL filter with damping branch consisting of a capacitor C d and a resistor R d on a DM basis. In this configuration, current is shared between the capacitor C and the damping branch R d -C d. This results in a lower power loss compared with having a damping resistor in series with capacitor C. The transfer function Vc(s) V i (s) is given as follows: V c (s) V i (s) = L g (1 + sr d C d ) (L g + L i )(s 3 L P CC d R d + s 2 L P C P + sc d R d + 1) (29) where, L P = (L g L i )/(L g + L i ) and C P = C + C d. The Bode plot of (29) is shown in Fig for different values of the damping resistance.

81 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 47 Figure 2.18: Passive damping of the oscillation in LCL filter using a split-capacitor parallel R d -C d damping branch. The resonance peak of the transfer function Vc(s) V i decreases with increase in the resistance (s) R d. However, beyond a certain value of the resistance, the resonance peak starts increasing again. This indicates that there exists an optimum value of damping resistance that can be chosen to get better damping CM filter passive damping Fig. 2.8 shows the filter capacitors C y1, C y2, and C Mg introduced at the dc bus. The neutral point of the capacitors C y1 and C y2 is connected to the LCL filter neutral M. The capacitor C Mg acts as a link between M and ground. The addition of C y1, C y2, and C Mg provides CM filtering of the dc-bus output of the PWM rectifier. The filter constraints and design procedure on the CM-based circuit of power converter are explained in Section 2.4. The CM equivalent circuit of the filter, including the damping resistors, is shown in Fig. 2.20(a), where, L a = Lg 3, L b = L i 3, R d cm = R d 3, C a = 3C, C dcm = 3C d, and C b = C y1 + C y2. Because of the small value of capacitor C Mg, the CM circuit for low frequency components can be approximated as shown in Fig. 2.20(b). The inductance L b of inverter-side LCL filter along with the effective filter capacitance C cm acts as a low-pass filter for CM components, where, C cm = ((C a + C dcm )C b )/(C a + C dcm + C b ). This eliminates the need for additional passive elements to realize a low-pass CM filter. By suitably selecting the corner frequency of the filter, the lower-order harmonics due to advanced PWM techniques and switching frequency component will circulate within the system, with a small magnitude. The resonant

82 Passive damping design Magnitude(dB) R d =0 p.u. R d =0.5 p.u. R d =1 p.u. R d =1.5 p.u. R d =2 p.u k 1k 10k Frequency(Hz) Figure 2.19: Frequency response plot of transfer function Vc(s) V i (s) values of damping resistance, where, R b = 3V b 2 P b =17.28Ω. given in (29) for different frequency of the CM filter with zero damping resistance is given as follows: f rescm = 1 2π L b C cm. (30) The filter admittance transfer function for the circulating CM current I comi(s) V com(s) is given in (31). The Bode plot of (31) is shown in Fig It can be observed that by increasing the damping resistance the CM current resonance is reduced and it reaches its minimum value at an optimum value of damping resistance. If the damping resistance is further increased, the CM resonance peak starts increasing. Hence, the value of R d selected in the split-capacitor R d -C d damping network needs to cater to both differential- and common-mode damping of the filter Selection of damping resistance R d To select the value of the damping resistance, its value is increased from zero in small steps. At each step the magnitude of the resonance frequency in the LCL capacitor voltage and the CM current is calculated. Fig. 2.22(a) plots the peak of the magnitude of transfer functions (29) and (31) as a function of the damping resistance value. From Fig. 2.22(a) it

83 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 49 + g (a) (b) Figure 2.20: (a) CM equivalent circuit for the PWM rectifier shown in Fig (b) Low frequency approximation. can be seen that the minimum resonance frequency in capacitor voltage, as well as in the CM current, occurs while having the damping resistance close to 1 p.u. The minimum is numerically observed at 1.1 p.u., which is chosen as the passive damping resistance used in the damping network Power loss calculation in the damping resistor R d To calculate the power loss in the damping resistor R d, the circuit shown in Fig is evaluated at different frequencies. The losses in R d are mainly due to fundamental (50Hz), I comi (s) V = C a C b C dcm R dcm s 2 + (C a C b + C b C dcm )s com(s) C a C b C dcm L b R dcm s 3 + (C a C b L b + C b C dcm L b )s 2 + (C a C dcm R dcm + C b C dcm R dcm )s + (C a + C b + C dcm ) (31)

84 Experimental result R d =0 p.u. R d =0.5 p.u. R d =1 p.u. R d =1.5 p.u. R d =2 p.u. Magnitude k 1k 10k Frequency(Hz) Figure 2.21: Frequency response plot of transfer function I comi(s) V com(s) values of damping resistance. given in (31) for different triplen harmonics (150Hz,...), and switching frequency (10kHz). The third harmonics losses are due to space vector PWM method and switching losses are due to switching of the PWM rectifier. All the calculated losses are added up and the result is plotted in Fig. 2.22(b). The power loss for the value of R d calculated in the previous subsection is marked to be 39.4W for a power converter rated for 10kVA. 2.6 Experimental result A three-phase 10kVA, 415V back-to-back connected power converter prototype is built in the laboratory to demonstrate the effectiveness of the filter. The base values are P base =10kVA, V base =240V, and f base =50Hz. The other base parameters, such as capacitance and inductance, are derived as C base = P base ; L 3 2πf base Vbase 2 base = 3V 2 base 2πf base P base The base capacitance and inductance are C base =185µF and L base =54.8mH, respectively. The

85 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives Magnitude at resonance frequency (db) R d (p.u.) 160 (a) Total Power Loss(W) R d (p.u.) (b) Figure 2.22: Effect of damping resistance on filter magnitude response and power loss. (a) Peak magnitude of response at resonant frequency versus the damping resistance, for the transfer function Vc(s) in db and the transfer function I comi(s) V i (s) V com(s) in db. (b) Power loss in the damping resistors versus damping resistance values due to both differential- and commonmode excitation.

86 Experimental result (a) (b) Figure 2.23: Different variants of filter topology. (a) Case B, where the capacitor C Mg and the connection between N and M are removed, and the star point, N, is connected to the ground directly. (b) Case C, where the capacitor C Mg and the connection between N and M are removed, and the point M is connected to the ground directly.

87 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 53 motor drive inverter is switched at 5kHz and the PWM rectifier is switched at 10kHz. A 100m long PVC coated four-core cable is used to connect a three-phase, 415V, 5.5kW, 50Hz star-connected induction motor to the inverter. The motor is controlled using volts per hertz (V/F) scheme. The PWM rectifier is controlled using vector control method [115]. Altera Cyclone II FPGA platform is used for implementation of the control algorithm. The setup has been tested in multiple configurations out of which the following three cases are of interest. Case A) The CM filter configuration shown in Fig Case B) The capacitor C Mg and the connection between N and M are removed, and the star point, N, is connected to the ground directly, as shown in Fig. 2.23(a). Case C) The capacitor C Mg and the connection between N and M are removed, and the point M is connected to the ground directly, as shown in Fig. 2.23(b). Fig shows the Bode plot of I mg(s) V AF E (s) for cases A, B, and C. From the Bode plot it can be seen that between case A and case B, case B offers better attenuation for low frequency and almost the same attenuation for high frequency. The problem with case B is that the CM voltage due to PWM rectifier can propagate to the load side and increase the CM current in the motor. This happens because the C y1 -C y2 mid point is not filtered effectively. Between case A and case C, case A has much better attenuation for both high and low frequencies. In case A, the lower-order harmonics are circulated within the system through the inductor L i, C y1, C y2, and PWM rectifier. The third harmonic RMS current is calculated to be 0.37A in each inductor. The inductors are designed for 15A RMS current. This is 2.5% of the component s current rating. So, the third harmonic circulating current in the filter topology has minimal effect on sizing of the filter inductors. To estimate the effectiveness of the filter, conducted noise emission test has been carried out by connecting a three-phase LISN, as shown in Fig The LISN prevents noise coming from the mains to setup, which can affect the test results. The LISN has been built in the laboratory and is used with a high frequency oscilloscope (500MHz, 5GSa/s, LeCroy 6050) as a receiver. The data captured by the oscilloscope are processed in MATLAB and the fast Fourier transforms (FFTs) of the waveforms are shown in Fig for the frequency range 100kHz to 25MHz. The objective behind this experimental setup is to compare the

88 Experimental result 50 0 Case a Case b Case c -50 Magnitude Frequency(Hz) Figure 2.24: The Bode plot of admittance I Mg(s) V AF E (s) offered to CM voltage by ground. different filter configurations. The results for the aforementioned cases are presented in Fig The results show that the CM noise in case A and case B is almost the same as expected from the Bode plot shown in Fig In case C, the CM noise between 0.1MHz and 0.3MHz is almost 50 times higher than that of case A. This shows the effectiveness of the CM filter. The use of smaller C y1 and C y2 in case C can help in reducing the CM noise, but this is in conflict with the requirements of (26) explained in Section To examine the advantages of case A over case B, the drive system has been tested and the CM current at the motor load side has been measured using Fluke i400s current probe connected to the oscilloscope. The results are shown in Fig The CM RMS currents corresponding to the aforementioned cases are as follows: I RMSA =121mA, I RMSB =477mA, and I RMSC =135mA. The CM current noise in case A is decreased by 400% compared with case B. Hence, the filter leads to lower CM load current than the traditional approach of connecting capacitors C y1 and C y2 to the dc bus. The system has also been tested with no CM filter at all, corresponding to the waveform in Fig. 2.27(d). The CM RMS current in this condition was measured to be I RMSd =487mA. The result shows negligible improvement in CM current measured at the motor terminals in case B over the case where no CM filter was used in the drive system.

89 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 55 A B C 250 H 50 H a b c 4 F 8 F 250nF EUT E 10Ω 5Ω E Test receiver input 50 Ω Figure 2.25: LISN connected between the grid and EUT. To damp the oscillations due to the addition of C Mg, a 50kΩ resistor is added in parallel to the C Mg. The experiment shows that the maximum power dissipation in the damping resistor is less than 0.1 W. This is because the voltage V Mg based on (28) is less than 20V, leading to low power dissipation in this damping branch. 2.7 Summary The overall filter design procedure to address the CM voltage is outlined for a PWM rectifierbased ASD. Analysis of the filter with capacitors C y1 and C y2 is discussed based on CM equivalent circuit. The CM dc-bus filter restrains the high frequency CM voltage, due to PWM rectifier, from affecting the load. Variants of the filter topology are evaluated to check the effectiveness of the explained method. The filter topology keeps the switching current components, along with third harmonic current components that occur due to advanced PWM techniques, within the power converter. The switching frequency components are effectively filtered on the voltage between dc bus and ground. Additionally, there is no need for large oversizing of the LCL filter inductors, because the third harmonic circulating current is less than 3% of the rated current. Conducted noise emission test has been conducted, which shows the effectiveness of the designed CM filter. Also, the CM current at motor side is reduced by 400% by the filter. The proposed filter needs minimal modification of the LCL filter to meet the above CM performance as it only involves the addition of three capacitors to the circuit. A split-capacitor passive damping method is employed for damping the resonant

90 Summary (a) (b) (c) Figure 2.26: Conducted noise emission test measured on the grid side of the ASD. (a) The CM filter configuration shown in Fig (b) The capacitor C Mg and the connection between N and M are removed, and the star point, N, is connected to the ground directly, as shown in Fig. 2.23(a). (c) The capacitor C Mg and the connection between N and M are removed, and the point M is connected to the ground directly, as shown in Fig. 2.23(b).

91 Chapter 2. Common Mode Filter Design for PWM Rectifier Based Motor Drives 57 (a) (b) (c) (d) Figure 2.27: CM current noise at the motor load side measured by the sum of three phase currents. (a) The CM filter configuration shown in Fig (b) The capacitor C Mg and the connection between N and M are removed, and the star point, N, is connected to the ground directly, as shown in Fig. 2.23(a). (c) The capacitor C Mg and the connection between N and M are removed, and the point M is connected to the ground directly, as shown in Fig. 2.23(a). (d) No CM filter at all.

92 Summary oscillations in DM and CM circuit. The losses in the damping resistors are shown to be less than 40W for a 10kW PWM rectifier.

93 Chapter 3 Control of Three-Phase PWM Rectifier A well-designed control algorithm can improve the performance of the system. The role of power converter control loops is to generate a PWM command signal such that the power converter follows the references [19, 88, ]. In PWM rectifier applications, the control loops can control the dc-bus voltage and the reactive power. The active power, drawn from the grid, is controlled by the dc load that is connected to the PWM rectifier. Output voltage of power converters consists of fundamental component, normally 50Hz, and the switching components of the order of khz. The switching components are filtered with the help of passive L, LC, and LCL filters. The use of LCL filters in grid-connected power converter applications is preferred [18]. This is due to its smaller filter size requirement, for the same level of filtering, as compared with L filter. However, the LCL filters suffer from resonant oscillations. This is due to existence of a pair of complex conjugate poles on imaginary axis. These oscillations can be damped with the help of damping resistors. However, this method increases the losses and reduces the filter performance. Different passive damping methods are proposed, in the literature, to reduce the losses in the damping resistor [18]. A control algorithm that can damp the oscillations without increasing the power losses and degrading the filter performance, called active damping [43 48], can be used to damp the oscillations. In this chapter, the working principle and control of PWM rectifier are explained in Section 3.1. In Section 3.2, DM and CM modelling of higher-order filters is explained. Section 3.3 provides state space control law for DM and CM active damping. Section 3.4 explains the continuous-time (CT) domain to discrete-time (DT) domain transformation. Closed-form analytical expressions are derived for the differential- and common-mode damping controller 59

94 Three-phase PWM rectifier gains in both CT and DT domains. In Section 3.6.2, the effect of active damping gains on the low frequency harmonic distortion of the PWM rectifier is analysed. A measure called energy contained in a signal (E CS ) is explained for comparing the effect of damping in different cases. A test method for loading the setup, by circulating the power in the setup using a doubly fed induction machine (DFIM), is explained in Section 3.5. Analysis of DFIM and the step-by-step procedure for the test are provided. In Section 3.6 the experimental results on a 10kVA laboratory regenerative motor drive prototype are provided. Section 3.7 summarizes the chapter. 3.1 Three-phase PWM rectifier A constant dc voltage is essential for the normal operation of power converters such as UPS, battery chargers, motor drives, voltage source inverters, etc. A DBR is traditionally used to convert ac voltage to dc voltage. In the case of DBR, there is no control over the output dc-bus voltage and it depends on the peak input ac voltage. The disadvantages of the DBRs are that they act as a nonlinear load and inject lower-order harmonics to the grid. They draw narrow peaky current from the grid; hence, they work with very high THD. A PWM rectifier is used to convert ac voltage to dc voltage. Fig. 3.1 shows a PWM rectifier connected to the grid using L filter. Regulated dc-bus voltage, bidirectional power flow, independent control over active and reactive power, and nearly sinusoidal current drawn from the grid are some of the advantages of PWM rectifiers. These features are possible by controlling the phase and magnitude of the pole voltage (V AO, V BO, V CO ). By controlling the phase, the active power flow, and by controlling the voltage magnitude, the reactive power flow, are controlled. The pole voltages of PWM rectifiers consist of the fundamental component (50Hz) and the switching component (order of khz). The switching component is filtered out with the help of passive filter used between the PWM rectifier and the grid. Different modulation schemes, such as sine-triangle PWM and CSVPWM, are used to generate the gate pulses needed for the switches [70 72,75]. PWM rectifiers eliminate the lower-order harmonic current injection to the grid. However, they inject high frequency noise to the grid. These noises span the range from the switching frequency to MHz. Different standards [5,15,16,124] are available that specify the limits for high frequency noise that can be injected to the grid by power converters. Passive or active filters [9,22,37,109] are used to reduce the high frequency noise

95 Chapter 3. Control of Three-Phase PWM Rectifier 61 Figure 3.1: PWM rectifier connected to grid using L filters. injected to the grid to the desired values suggested by the standards PWM rectifier control Vector control is a popular control method for three-phase induction machines. The method controls the speed and torque of the machine to achieve faster dynamic response [125]. The outer control loop controls the speed. The torque is controlled by the inner control loop. This method, with small modifications, can be used for controlling three-phase PWM rectifiers, where the inner loop controls the converter current and the voltage controller is the outer loop, which controls the dc-bus voltage [85, 86, 115, 126] Current control In cascaded two-loop control methods, the inner loop is the current control loop. The current control loop should have ideal tracking over a wide frequency range, high dynamic response, low harmonic content, and the capability to work under nonideal grid conditions. Several control algorithms have been proposed in the literature [ , ]. Different controls such as PI state space controller [127], PR controller base [123], and two current loop control with an outer inductor and an inner capacitor current loop [119,122] have been investigated. Two controllers commonly used are PR-based and PI-based controllers. The PR controllers are used when the references are ac signals. The resonance frequency of the PR controller is

96 Three-phase PWM rectifier Figure 3.2: Current control loop using PI controller in SRF. Figure 3.3: Voltage control loop using PI controller. set to the fundamental frequency of the references. The PR controllers have zero steady-state error at resonance frequency. The PI controller is used when the references are dc signals. This is due to zero steady-state error of the PI controller for dc signals. In this work, PI controller in SRF is used as a current controller. The simplified block diagram of the current control loop, neglecting d and q axis cross-coupling, in SRF is shown in Fig In the diagram, the converter is modelled as gain G and delay T d. R s and T s are the resistance and the time constant of the filter inductors, respectively. k 2 and T 2 are the gain and the time constant of the current sensor, respectively. k c and T c are the gain and the time constant of the PI controller, respectively Voltage control The outer control loop is voltage controller loop. Voltage controller loop is needed to control the dc-bus voltage and regulate it to a desired voltage [81]. A PI controller is used to regulate the dc-bus voltage. The voltage controller loop is shown in Fig In the figure, k v and T v are the gain and the time constant of the PI controller, respectively. k 1 and T 1 are the gain and the time constant of the voltage sensor, respectively. K = 2 3 I dc and i sq as I dc = Ki sq. C dc is the dc-bus capacitance. v sq V dc is the relation between

97 Chapter 3. Control of Three-Phase PWM Rectifier 63 Figure 3.4: SRF-PLL block diagram used for the PWM rectifier control Unit-vector generation Grid voltage phase and frequency information is essential for operation of PWM rectifiers [76, 77,128]. Using unit vector generated by PLL, it is possible to synchronize the inverter voltage phase and frequency with the grid voltage. In this chapter, SRF-PLL is used because of better phase-tracking ability [76, 77]. The block diagram of the SRF-PLL is shown in Fig The quantities sin(θ e ) and cos(θ e ) are required for transforming any vector from stationary reference frame into SRF. To estimate the unit vectors, the three-phase grid voltages are converted to two-phase stationary reference frame (αβ). The stationary reference frame voltages are further converted into SRF (dq). The q-axis quantity is aligned with revolving voltage vector. For a three-phase balanced system, if the q-axis quantity is aligned with revolving voltage vector, the d-axis quantity would be zero. Using this it is possible to estimate the frequency and phase angle as shown in Fig Using the PLL, current control loop, and voltage control loop, it is possible to operate the PWM rectifier using vector control as extensively discussed in the literature [115]. The study on damping of LCL filter resonance on both CM and DM bases is discussed in Section Modelling of higher-order filters Passive filters are used to filter the high frequency components present in the output voltage of power converters. LCL filters are more popular in grid-connected applications. However, LCL filters suffer from resonance between passive components L and C. These resonance oscillations can be damped with the help of passive damping. Passive damping increases

98 Modelling of higher-order filters Figure 3.5: PWM rectifier with combined CM and DM filters. the overall power losses. Additionally, in some damping configurations, it decreases the performance of the filter. Active damping control algorithms damp the oscillations without increasing the power loss and without affecting the performance of the filter [43 48]. Fig. 3.5 shows a PWM rectifier with combined CM and DM filters utilizing LCL filter. The circuit is analysed in terms of DM and CM variables separately. The CM equivalent circuit, obtained in Chapter 2, is used here to analyse the common-mode active damping (CMAD) of the filter using the state feedback approach Differential-mode filter model Single-line representation of the grid, LCL filter, and PWM rectifier shown in Fig. 3.5 is depicted in Fig The PWM rectifier is represented as a pulsed voltage v i with fundamental frequency the same as the grid voltage fundamental frequency. The state variables used to model the DM LCL filter, shown in Fig. 3.6, are x 1 = v C, x 2 = i g, x 3 = i i, and x = [x 1 x 2 x 3 ] and the input vector is u = [v i v g ]. The state space model of the LCL filter is derived as follows. Writing dynamic equations corresponding to Fig. 3.6 is as follows:

99 Chapter 3. Control of Three-Phase PWM Rectifier 65 Figure 3.6: Differential model of the LCL filter shown in Fig The relation between capacitor current and voltage is, Substituting (35) in (34) and simplifying it, v g + L g di i dt + v C = 0 (32) v C + L i di g dt + v i = 0 (33) i i i g i C = 0. (34) i C = dv C dt. (35) x 1 = 1 C x C x 3. (36) Equations (32) and (33) can be represented in terms of state variables as, x 2 = 1 x 1 1 v i (37) L i L i x 3 = 1 x v g. (38) L g L g Using (36), (37), and (38) the state space model is derived as given in (39). ẋ = Ax + Bu y = Cx (39) where, C C A = 1 L i 0 0, B = b 1 b 2 = 1 L i 0 1 L g L g.

100 Modelling of higher-order filters The matrix C is a 3 3 identity matrix as the desired outputs are the inductor currents (i i and i g ) and capacitor voltage (v C ). The eigenvalues of A are determined by setting, si A = 0 s 3 + s 1 L p C = 0 (40) s 1 = 0, s 2,3 = ±jω res where, ω res = 1 and L P = LgL i LpC L g+l i. The input vector is u = [v i v g ] Common-mode filter model The CM equivalent circuit of PWM rectifier shown in Fig. 3.5 is obtained in Chapter 2, and it is shown in Fig The capacitor C Mg is very small, of the order of nf. Hence, at low frequencies it acts as an open circuit. The low frequency approximation of the CM circuit given in Fig. 3.7(a) is shown in Fig. 3.7(b). The dynamic equations describing the circuit shown in Fig. 3.7(b) are as follows: L b d(i comi ) dt C cm dv cm dt = V AF E + V cm (41) = I comi (42) where, i ai, i bi, and i ci are the converter-side phase currents, V cm = V Ca V Cb, C cm = CaC b C a+c b, and I comi = i ai + i bi + i ci. The state variables are x 4 = V cm, x 5 = I comi, and x cm = [x 4 x 5 ] and the input is u cm = V AF E. The state space representation is given in (43). ẋ cm = A cm x cm + B cm u cm (43) where, A cm = [ ] [ ] 0 1 C cm 0, B 1 cm =. L b 0 1 L b The eigenvalues of matrix A cm are located at s 1,2 = ±jω rescm = ± j Lb C cm.

101 Chapter 3. Control of Three-Phase PWM Rectifier 67 (a) (b) Figure 3.7: (a) The CM equivalent circuit of the PWM rectifier shown in Fig (b) Low frequency approximation of CM equivalent circuit. 3.3 State space control law for active damping The purpose of the state feedback control law is to locate poles of the system such that the marginally stable poles are brought to stable region with satisfactory dynamic response. It is advantageous to use state space method when more than one input is involved or more than one output is sensed [127,129]. The control law used is a linear combination of the state variables for DM and CM active damping. The analysis given below provides expressions for the state feedback gain in CT. This is then used to obtain expressions for the damping gain in DT for implementation in a digital controller Differential-mode control law LCL filters have a pair of complex conjugate poles on the imaginary axis. State feedback can be used to shift these poles of the system to the left-hand side of the imaginary axis and

102 State space control law for active damping obtain adequate damping. The control and the gain matrix can be expressed as, u = (K 1 x 1 + K 2 x 2 + K 3 x 3 ) = K x (44) where, K = [K 1 K 2 K 3 ] is the gain matrix. The state space representation of the modified system is, ẋ = (A b 1 K)x. (45) The eigenvalues of the system after state space feedback are located at, si A + b 1 K = det s 1 C (1+K 1) 1 C L i (s K 2 L i ) K 3 L i = 0. 1 L g 0 s Solving the aforementioned determinant leads to characteristic equation given as, s 3 K { 2 (1 + s 2 K1 ) + L i L i C + 1 } { } (K2 + K 3 ) s = 0. (46) L g C L g L i C The original poles of the system are given by (40). Let the desired pole locations be at 0 and σ ± jω d, where σ = ζω res and ω d = ω res 1 ζ2. Then the characteristic equation with new pole locations would be, s{(s + σ jω d )(s + σ + jω d )} = 0 s 3 + 2ζω res s 2 + ω 2 ress = 0. (47) Equating (46) and (47), the gain matrix K to obtain DM damping is, K 1 = 0 K 2 = 2ζω res L i K 3 = +2ζω res L i. (48) Common-mode control law A similar analysis is extended for the CM filter. The control input for CM resonance damping is given by, u cm = (K 1cm x 4 + K 2cm x 5 ). (49)

103 Chapter 3. Control of Three-Phase PWM Rectifier 69 The state space representation is modified as, ẋ cm = (A cm B cm K cm )x cm. (50) The eigenvalues of the system after state space feedback are located at, [ ] si A cm + B cm K cm = det s 1 C cm 1 K 1cm L b s K 2cm L b = 0. Solving the aforementioned determinant leads to characteristic equation given as, s 2 K 2 cm s K 1 cm = 0. (51) L b L b C cm Let the desired pole locations be at σ cm ±jω dcm, where σ cm =ζ cm ω rescm, ω dcm =ω rescm 1 ζ 2 cm, and ω rescm = 1 Lb C cm. Then the characteristic equation with new pole locations would be, s 2 + 2ζ cm ω rescm s + ω 2 res cm = 0. (52) Equating (51) and (52), the state feedback gain matrix K cm for CMAD is given by, K 1cm = 0 K 2cm = 2ζ 3.4 Analysis in discrete-time domain Lb C cm. (53) Analog information from the sensors is converted into digital form using analog-to-digital converters (ADCs). The digital control has to act upon the samples of the sensed signals. The data are sampled by the ADC at a sampling time T, where T = 1 2F sw. Since each sampled value is held constant until the next value is available, compared with continuous signal the average value of the sampled data lags by T/2 [130]. matrix coefficients vary based on the sampling rate. Furthermore, the state The active damping analysis from Section 3.3 is presented in DT domain to facilitate implementation in a digital controller. CT-to-DT transformation based on impulse invariant transform approach is adopted [131]. This approach helps match the frequency response characteristics of the continuous system and the DT domain. Closed-form expressions are derived to understand the dependencies of the state matrices on the filter parameters and the sampling rate and to relate the filter damping factor (ζ) to the state feedback gain.

104 Analysis in discrete-time domain Discrete-time representation The CT state space model can be represented in DT domain with a good match of the poles and zeros of the transfer function using the impulse invariant transformation [132]. This approach is used for transforming CT representation to DT and can be expressed as follows: x[(k + 1)T ] = Φx[kT ] + Γu[kT ] (54) y[kt ] = Hx[kT ] Expressions for Φ and Γ for differential-mode filter modelling The closed-form expressions of Φ and Γ help in designing the active damping controller, which is analytically calculated as follows: Φ = e AT. (55) Consider the function defined as f(at ) = e AT and g(at ) to be a second-order polynomial, because the dimension of A is 3, such that: g(at ) = k 0 I + k 1 (AT ) + k 2 (AT ) 2. (56) The poles of the CT characteristic equation are λ = 0, ± ω res. f(λt ) = e λt (57) g(λt ) = k 0 I + k 1 (λt ) + k 2 (λt ) 2 (58) When λ = 0, f(0) = 1 k 0 = 1. When λ = jω res, e jωrest = 1 + k 1 (jω res T ) + k 2 (jω res T ) 2 Equating the real and imaginary parts k 1 and k 2 can be expressed as, k 1 = sin(ω rest ) ω res T k 2 = 1 cos(ω rest ) (ω res T ) 2. (59)

105 Chapter 3. Control of Three-Phase PWM Rectifier 71 Substituting the value of k 1 and k 2, Substituting for A from (39) in (60), ( 1 α 2 C Φ = Φ = e AT = k 0 I + k 1 (AT ) + k 2 (AT ) 2 = I + sin(ω rest ) ω res A + 1 cos(ω rest ) (ω res ) 2 A 2. (60) ) 1 L g + 1 L i α 1 C α 1 L i 1 α 2 L i C α 1 C α 2 L i C α 1 L g α 2 L gc 1 α 2 L gc (61) where, α 1 = k 1 T = sin(ω rest ) ω res α 2 = k 2 T 2 = 1 cos(ω rest ). ωres 2 The Γ is calculated as follows: Γ = T 0 e Aη dη B = (T + AT 2 It is further simplified, using (60), as 2 + A2 T 3 3! +...)B = K=0 A K T K+1 (K + 1)! = A 1 (Φ I)B. (62) Γ = α 1 B + α 2 AB (63) = γ 1 γ 2 = α 2 L gc L i 0 α 0 1 L g α 2 L i C α Expressions for Φ cm and Γ cm for common-mode filter modelling Consider the following function defined as f(at ) = e AT and g(at ) to be a polynomial such that, g(at ) = k 0 I + k 1 (AT ). (64)

106 Analysis in discrete-time domain The poles of the CT characteristic equation are λ = ± Lb C cm = ±jω rescm. When, j f(λt ) = e λt (65) g(λt ) = k 0 I + k 1 (λt ) (66) λ = jω rescm e jωrescmt = k 0 + k 1 (jω rescm T ). Equating the real and imaginary parts k 0 and k 1 can be expressed as, k 0 = cos(ω rescm T ) k 1 = sin(ω res cm T ). (67) ω rescm T This is used to obtain Φ cm and Γ cm as, [ ] cos(ωrescmt ) sin(ωrescm T ) ω Φ cm = rescm C cm sin(ω rescm T ) ω rescm L b cos(ω rescm T ) (68) [ ] 1 cos(ωrescmt ) Γ cm =. (69) sin(ωrescm T ) ω rescm L b Discrete-time state feedback control law Differential-mode control law in DT The pole location in z-domain can be related to s-domain as z = e st. The desired pole locations are s 1 = 0, s 2,3 = σ ± jω d and their values in z-domain are as follows: z 1 = e 0T = 1 z 2 = e ( σ+jω d)t = e σt (cos(ω d T ) + jsin(ω d T )) z 3 = e ( σ jω d)t = e σt (cos(ω d T ) jsin(ω d T )). (70) The DT model of the DM filter with active damping is given by, ẋ = (Φ γ 1 K D )x (71)

107 Chapter 3. Control of Three-Phase PWM Rectifier 73 where, K D = [K 1D K 2D K 3D ]. The eigenvalues of the system after DT state feedback is given by zi Φ + γ 1 K D = 0. Equating the new characteristics with the desired characteristics, the gain matrix K D can be calculated. zi Φ + γ 1 K D = (z z 1 )(z z 2 )(z z 3 ) (72) The values of the resulting Φ and Γ are given in (61) and (63), respectively. Using (72) and equating the coefficients of z in (72), the following expressions are obtained: 2cos(ω res T ) 2e σt α 2 cos(ω d T ) K 1D L i C + K 2D = 0 L i 1 2e σt cos(ω d T ) e 2σT + 2cos(ω res T ) 2(K 2D + K 3D ) α 1 α 2 L i L g C + 2K 2D α 1 α 1 α 1 L i = 0 e 2σT α 2 K 1D L i C K 2D 1 = 0. (73) L i Solving for K 1D, K 2D, and K 3D the final expressions for DT active damping controller gain are obtained in (74). K 1D = 2cos(ω rest ) 2e σt cos(ω d T ) + e 2σT 1 2α 2 CL i K 2D = 2cos(ω rest ) 2e σt cos(ω d T ) e 2σT + 1 2α 1 L i K 3D = + 2cos(ω rest ) 2e σt cos(ω d T ) e 2σT + 1 2α 1 L i (74) The state feedback gains in (74) are used for the differential-mode active damping (DMAD) in the digital controller.

108 Circulating power test setup for a PWM rectifier motor drive Common-mode control law in DT The desired pole locations are s 1,2 = σ cm ± jω dcm and their values in z-domain are as follows: z 1cm = e ( σcm+jω dcm )T = e σcmt (cos(ω dcm T ) + jsin(ω dcm T )) z 2cm = e ( σcm jω dcm )T = e σcmt (cos(ω dcm T ) jsin(ω dcm T )). (75) The gain matrix K Dcm = [K 1Dcm K 2Dcm ] can be calculated using (76). zi Φ cm + Γ cm K Dcm = (z z 1cm )(z z 2cm ) (76) Using (76) and equating the coefficients of z in (76), the following expressions are obtained. 2cos(ω rescm T ) K 1Dcm 2e σcmt cos(ω dcm T ) + K 1Dcm cos(ω rescm T ) + K 2D cm sin(ω rescm T ) L b ω rescm = 0 1 e 2σcmT K 1Dcm cos(ω rescm T ) + K 1Dcm + K 2D cm sin(ω rescm T ) L b ω rescm = 0 (77) Solving for K 1Dcm and K 2Dcm the final expressions (78) for digital active damping controller gain are obtained. K 1Dcm = 2cos(ω res cm T ) + e 2σcmT 2e σcmt cos(ω dcm T ) 1 2cos(ω rescm T ) 2 K 2Dcm = 2cos(ω res cm T ) e 2σcmT 2e σcmt cos(ω dcm T ) sin(ωrescmt ) L b ω rescm (78) The state feedback gains in (78) are used to implement the CMAD in the digital controller. 3.5 Circulating power test setup for a PWM rectifier motor drive A burn-in test is executed in order to test a product at conditions similar to real-life operating conditions. Burn-in test is normally done at full-load operating condition and for a

109 Chapter 3. Control of Three-Phase PWM Rectifier 75 Equipment Under Test (EUT) VR VY VB 3-Phase grid PWM Rectifier DC Bus Inverter SCIM DFIM CBr Vra Vrb Vrc Vsa Vsb Vsc CBs Machine 1 Machine 2 Figure 3.8: The overall circuit configuration of motor drive coupled to a DFIM, which is used to circulate power back to the grid. sufficiently long period. Hence, a product with faulty manufacturing can be identified and prevented from being passed on to the customer. With the help of burn-in test, the stiffness, reliability, long-term stability, and efficiency can be verified. Normally in low power applications, a resistive bank is used to load the setup. However, in medium and high power applications it is difficult to get a resistive bank capable of dissipating power as a load. Even if the resistive load bank is available, dissipating large amount of power would increase the cost of the test. And, from the energy conservation point of view, energy saving is very important. Different methods to replace the resistive load bank with power electronic equipment have been proposed in the literature [ ]. A method for testing a PWM rectifier induction motor drive using DFIM for burn-in test is discussed in this section. The test configuration makes use of a back-to-back power converter, which is the drive converter that is to be tested. Power circulation back to the grid during testing is achieved by controlling the speed of the induction machine around its synchronous speed. The sequence of steps in the explained method ensures smooth start up of the machines and the power converter and transfer of power to its rated value. This is confirmed by analysis of the DFIM characteristics Circulating power method The overall circuit configuration of the test setup is shown in Fig The PWM rectifier converts three-phase ac to dc at UPF. The dc is converted back to ac using a three-phase inverter. The ac is fed to a squirrel-cage induction machine (SCIM), which is labelled as machine 1. The SCIM is coupled with a DFIM labelled as machine 2. The number of

110 Circulating power test setup for a PWM rectifier motor drive poles of the SCIM and the DFIM are required to be the same in the test setup. Depending on the speed command to the SCIM, for a given shaft speed, it can be made to operate in a sub-synchronous or super-synchronous condition, which corresponds to motoring or regenerative modes of the drive, respectively. During motoring mode, electrical power is converted to mechanical power in the SCIM. The mechanical power is transferred to DFIM through the rotor shaft. Mechanical power is converted back to electrical power in the DFIM and pumped back to the grid. In regenerative mode, the DFIM acts as a motor and the SCIM as a generator. The power is pumped back to grid through the PWM rectifier. The regenerative mode is possible because of bidirectional power transfer capability of the PWM rectifiers and the motor characteristics. In this test configuration, the whole setup can be tested at rated power, while drawing only losses from the grid. This saves a large amount of energy in medium and high power applications. Extra care should be taken while the SCIM is running at its synchronous speed and the DFIM is to be energized to enable power circulation. Speed mismatch between the DFIM and SCIM can cause high current flowing in the setup, which can lead to failure of the components. The worst condition is when one of the machines is rotating in the reverse direction. The method for smooth start up and loading of the test setup is explained in Subsection Analysis of the DFIM operation DFIM with the rotor terminals open acts as an open circuit transformer with air gap. If the stator is connected to three-phase ac, a rotating magnetic field (RMF) will be generated in the stator. The RMF rotates with the speed of 120f revolutions per minute (rpm), where f is P the frequency of the three-phase ac in Hz and P is the number of poles of the machine. The rotor voltage can be calculated analytically as given in [139]. The mathematical expression to calculate DFIM rotor voltage at different rotor speeds is given in (79). R r i r + L r d dt i r + L 0 d dt (i se jɛ ) = u r (79) The equation (79) is in the rotor reference frame, where, R r and L r are resistance and self-inductance of the rotor windings, respectively. ɛ is the angle between stator and rotor axes, L 0 is magnetizing inductance, and i r and u r are space phasors of rotor current and voltage in rotor reference frame, respectively, as shown in Fig i s is space phasor of

111 Chapter 3. Control of Three-Phase PWM Rectifier 77 b r -axis b s -axis q-axis d-axis a r -axis a s -axis c s -axis c r -axis Figure 3.9: Positions of the stator, rotor, and the air gap field reference frames. stator current in stator reference frame. The equation (79) is transferred to the air gap field coordinates frame by multiplying both sides with e j(µ ɛ), where, µ is angle between stator and air gap field axes. The result is given in (80). R r (i rd + ji rq ) + σ l L r d dt (i rd + ji rq )+ j(ω s ω r )σ l L r (i rd + ji rq ) + (1 σ l )L r di ms dt + j(ω s ω r )(1 σ l )L r i ms = (u rd + ju rq ) (80) When the rotor windings are open, the rotor current is zero. Hence, the terms R r (i rd + ji rq ), σ l L r d dt (i rd + ji rq ), and j(ω s ω r )σ l L r (i rd + ji rq ) are equal to zero. At steady state, the stator magnetizing current (i ms ) would be constant and hence (1 σ l )L r di ms dt = 0. The equation (80) simplifies to (81), u rdq = (ω s ω r ) K (81) where, ω s is the angular velocity of the stator RMF in electrical, ω r is the angular velocity of rotor in electrical, σ l is leakage factor, and K= (1 σ l )L r i ms. K can be measured experimentally and was found to be Vs in the experimental setup. The RMF induces a voltage in the rotor windings. This voltage is proportional to the difference between the speed of RMF and the speed of the rotor. Fig shows analytical and experimental rotor voltage versus

112 Circulating power test setup for a PWM rectifier motor drive Halt condition Analytical Experimental Motoring Regenerating Reverse direction V r (V) N RMF - N r (krpm) Figure 3.10: Rotor voltage (V r ) versus speed difference (N RMF -N r ) between RMF and DFIM rotor. The modes of operation of the SCIM are indicated. mechanical speed difference between RMF and the rotor. From Fig it can be seen that when the speed difference is close to zero the rotor voltage is small and is at its minimum value. There is only one minimum, which is at zero speed difference. Synchronization at this point, by closing the rotor circuit breaker, results in minimal electrical transients or mechanical oscillations. As the rotor voltage becomes larger, while closing the rotor circuit breaker higher electrical and mechanical transients will be produced. The maximum rotor voltage range is when the SCIM is rotating in the reverse direction, as shown in Fig and given in (81). Attempting synchronization in this region results in flow of large current in the rotor winding of the DFIM. This is due to high rotor voltage. This produces large mechanical power and transfers it to the SCIM, which can damage the machines or the power converter. The normal tests with the motor drive system in the explained method are conducted near the zero speed difference point shown in Fig The use of DFIM as machine 2 is essential in the test configuration and it cannot be replaced with SCIM. The concern of replacing the DFIM with an SCIM as machine 2 arises at the time of synchronization of the test setup. If machine 1 is to be direct on-line started, then machine 2 cannot be started with speed ramp up with a simple V/F speed control scheme. A second approach may be to start machine 1 with V/F speed control. If machine

113 Chapter 3. Control of Three-Phase PWM Rectifier 79 1 reaches the rated speed, then machine 2 could be connected to the lines. This can have large electrical transients along with mechanical oscillations, which can trip the motor drive system. Additionally, the knowledge of grid frequency and directions of rotation of both machines is necessary. Hence, the use of a DFIM, as machine 2, enables smooth start up and loading of the test configuration as explained in Subsection Procedure for start up of the test circuit The steps for synchronizing and loading the setup are as follows: 1- The DFIM stator is connected to three-phase ac by closing circuit breaker CBs, with rotor terminals kept open by circuit breaker CBr, as shown in Fig The rotor voltage is monitored using a voltmeter. 2- The power converters are turned on and the SCIM starts speeding up from halt condition as a normal motor drive. 3- While SCIM is speeding up, the DFIM rotor voltage should decrease. If the rotor voltage increases, it implies that the SCIM is rotating in the reverse direction, so phase reversal should be performed on either the DFIM or SCIM. 4- The SCIM speed is increased till the minimum rotor voltage is obtained. At this point the difference between the RMF and the rotor speed is very small and close to zero. Now the rotor terminals can be shorted by closing CBr. There will be minimal electrical transients in the rotor of the DFIM. With the aforementioned steps, the DFIM and SCIM can be synchronized close to zero slip of the SCIM. Both the machines will work close to no-load condition, and power is not transferred to either of the sides. This mode of operation is called synchronized operating mode. The steps to load the setup in motoring mode and regenerative mode are given below: 5- In synchronized operating mode, if the speed command to the SCIM (machine 1) is increased, using the motor drive speed command, then machine 1 will work as motor and the DFIM (machine 2) will operate as generator. The power is transferred from SCIM to DFIM and pumped back to the grid through the stator windings of the DFIM.

114 Circulating power test setup for a PWM rectifier motor drive VR VY VB 3-Phase grid Power Meter Equipment Under Test (EUT) PWM Rectifier Inverter DC Bus SCIM Vra Vrb Vrc DFIM CBr Vsa Vsb Vsc Machine 1 Machine 2 S1 CBs S2 Phase Reversal Switch (PRS) PRS Figure 3.11: The circuit configuration to measure the circulating and input power of the PWM rectifier motor drive. 6- In synchronized condition, if the speed command to the SCIM (machine 1) is decreased, using the motor drive speed command, then the DFIM will work as motor and the SCIM as generator. The power is transferred from DFIM to SCIM and pumped back to the grid through PWM rectifier. This would allow two-quadrant testing of the motor drive under both generating and motoring conditions. A phase reversal switch (PRS), as in Fig. 3.11, can be added if four-quadrant static testing is required in regenerative mode Calculating power losses With the configuration given in Fig. 3.8, the setup can be tested in full-load condition, while taking only losses from the grid. The overall efficiency of the setup depends on the efficiency of individual subsystems in the test setup. The power converter efficiencies are approximately 95%; the efficiencies of DFIM and SCIM, which depend on the type and size, are approximately 80% to 85% for medium power levels. Hence, the overall efficiency of the setup would be around 60%. So, 40% of the circulating power would be lost and would need to be supplied by the grid. The losses in the machines are lower for high power machines, and the power drawn from the grid can be reduced to about 25% for higher power levels.

115 Chapter 3. Control of Three-Phase PWM Rectifier Experimental results Experimental setup A three-phase, 10kVA, 415V PWM rectifier prototype has been built in the laboratory with the filter topology as shown in Fig The base and the designed values of the filter parameters are given in Table The PWM rectifier is loaded using a motor drive inverter. The experimental setup consists of the PWM rectifier, a motor drive inverter, and a 5.5kW induction motor whose shaft is coupled to a doubly fed induction generator. This test configuration allows circulation of power and draws only losses from the grid. SRF controller is used to independently control the active and reactive power input to the power converter and regulate the dc-bus voltage of the PWM rectifier using CSVPWM [140]. The control block diagram of the PWM rectifier along with DM and CM active damping loops is shown in Fig The block diagrams within the dashed lines show the active damping parts. Note that K 2D and K 3D are equal in magnitude but with opposite sign. Also, K 1D and K 1Dcm are numerically much smaller than K 3D and K 2Dcm, respectively, in the practical design. The setup has been tested with different damping methods under loaded condition. The control is implemented in a Cyclone II FPGA using 16-bit fixed-point arithmetic. This section consists of two parts. In the first part, the performances of differential- and common-mode damping are evaluated for five cases: case (i) when damping is absent, case (ii) with passive damping, case (iii) with DMAD, case (iv) with CMAD, and case (v) with both DMAD and CMAD. In the second part, the experimental results corresponding to test configuration for circulation of power in motoring and generating modes are presented. The waveforms are measured and captured using a LeCroy 6050, 500MHz oscilloscope.

116 Experimental results Table 3.1: Design values for the filter. SL.NO. PARAMETER PER UNIT ACTUAL 1 Base Power P base 1p.u. 10kVA 2 Base Voltage V base 1p.u. 240V 3 Base Frequency f base 1p.u. 50Hz 4 dc-bus Voltage V dc V PWM Rectifier Switching kHz Frequency F sw LCL Filter Resonance 20 1kHz Frequency f res CM Filter Resonance kHz Frequency f rescm 8 Filter Inductance L g = L i mH 9 Filter Capacitance C L µF 10 dc Bus Filter C y1 = C y µF 11 Filter Capacitance C Mg nF 12 Damping Resistance R d Ω 13 Damping Capacitance C d µF

117 Chapter 3. Control of Three-Phase PWM Rectifier 83 Figure 3.12: Control block diagram of a vector controlled PWM rectifier with DM and CM active damping loops.

118 Experimental results th 7th 11th 13th Weighted Admittance 100 Admittance (mho%) Damping Factor ( ) Figure 3.13: Admittance offered by the PWM rectifier to different harmonics and weighted admittance, evaluated for different DMAD gain given in (48) Distortions at low frequency and resonance frequency Effects of active damping gain on grid current lower-order harmonics Because of the presence of lower-order harmonics in the line voltage, the input current to the PWM rectifier contains lower harmonics. Although introduction of active damping reduces the resonant oscillations, it is expected to increase the lower-order harmonics in the input current as reported in the literature [141]. The increase in lower-order harmonics in the input current is due to the active damping state feedback, which feeds the sensed lowerorder harmonics, as well, in the controller. This can be seen from state feedback law given in Section Higher active damping gains amplify the harmonics which are fed back, hence increasing the low frequency THD observed in the input current to the converter. To analyse the effect of damping on line current distortion, the current controller and active damping control loops have been modelled in CT domain. Simulation using MATLAB is used to calculate the input admittance of the power converter at the harmonic frequencies. The admittance Y n = In V n for 5 th, 7 th, 11 th, and 13 th harmonics was calculated and is shown in Fig along with the weighted admittance using (82),

119 Chapter 3. Control of Three-Phase PWM Rectifier 85 W Y = n Y n 2 n 2 (82) where, I n is the input current harmonics drawn by PWM rectifier, V n is line voltage harmonics, and n =5, 7, 11, and 13. The admittance of the power converter is evaluated using the method from [142] by superimposing the harmonic excitation over the fundamental nominal operation of the converter for different active damping factors. It is assumed that the amount of line voltage even harmonics is small and negligible. The third harmonic and its multiples cannot flow in the line current of the three-phase converter. So, the system has been evaluated for 5 th, 7 th, 11 th, and 13 th harmonics. It is also assumed that the magnitude of the harmonic components in the line voltage is inversely proportional to the harmonic number. As it can be seen from Fig. 3.13, by increasing the active damping gain K D, which is proportional to damping factor ζ, the admittance offered by the PWM rectifier is increased. The input current harmonic to the power converter depends on the input admittance offered to each harmonic by the power converter. Hence, the THD of line current depends on the active damping gain when there are harmonics in the inverter and the grid voltage Energy contained in signal. The waveforms of the power converter contain many signal frequencies because of fundamental excitation, low frequency distortion, and triplens, which are due to space vector modulation, in addition to switching frequencies and its side bands. The strength of the signal in the LCL filter is evaluated at the resonance frequency using (83). This is used to evaluate the filter damping performance for different damping gains. The objective of the E CS definition is to quantify the damping provided for the resonance frequency. Based on Parseval s theorem provided in Appendix A, the total energy contained in the waveforms around resonance frequency is calculated using (83). The expression for E CS between frequency range F 1 and F 2 is: E CS = F 2 1 x(f ) 2 (83) F 2 F 1 F =F 1 where, F 1 < F 2. The E CS value is used to compare the energy contained in the LCL filter capacitor line to line voltage for DM resonance and dc-bus midpoint to ground voltage for

120 Experimental results CM resonance. The comparisons are done for different cases of active damping and passive damping Passive damping and active damping control algorithms Passive damping The setup has been tested under loaded condition (5.5kW) with and without passive damping. The value of the damping resistance calculated in Section is used for the passive damping branches. The test results for the case with and without passive damping are shown in Fig. 3.14(a) and (b), respectively. The power loss in the damping resistors was measured, using YOKOGAWA WT1600 digital power meter, to be 40W. It is observed from Fig that the resonant oscillations in the LCL capacitor line to line voltage, grid-side current, and in the dc-bus capacitor midpoint to ground voltage are reduced in the case of passive damping as compared with the case of no damping. It is seen that the performance difference between the cases is better captured by the spectra of the waveforms, which is obtained using FFT of the captured time domain waveforms. The passive damping network is effective in attenuating both differential- and common-mode resonant oscillations Active damping To study the effectiveness of active damping, the passive damping resistors are shorted and the active damping loop is activated. Fig shows the filter capacitor line to line voltage, the grid phase current, the dc-bus capacitor midpoint to ground voltage and their spectra, corresponding to cases (i), (ii), and (v) mentioned in Section 3.6. The reduction in the resonant oscillations due to active damping case can be observed from Fig However, it can also be seen that the lower frequency distortion in this case is increased. The LCL capacitor line to line voltage and dc-bus midpoint to ground voltage are also measured to study the effects of separately enabling differential- and common-mode active damping. The spectra of these voltages are shown in Fig The three cases considered here are case (iii) activating only DMAD, case (iv) activating only CMAD, and case (v) activating both DMAD and CMAD. The damping gains are given in Table 3.2. The actual values of the active damping gains using (48) and (53) are represented in column 4. Column 3 represents the gain normalized by R b. Column 5 represents the DT gains, used in the experimental

121 Chapter 3. Control of Three-Phase PWM Rectifier Voltage Current Voltage Current Voltage Current Voltage(V) Current(A) Voltage(V) Current(A) Voltage(V) Current(A) Time(ms) Time(ms) Time(ms) Voltage(V) 0 Voltage(V) 0 Voltage(V) Time(ms) Time(ms) Time(ms) F1, F3 F V/div 100mA/div 400Hz/div 400Hz/div F1, F3 F V/div 100mA/div 400Hz/div 400Hz/div F1, F3 F V/div 100mA/div 400Hz/div 400Hz/div Voltage(V) / Current(A) F3> F2> Voltage(V) / Current(A) F3> F2> Voltage(V) / Current(A) F3> F2> F1> F1> F1> Frequency(Hz) Frequency(Hz) Frequency(Hz) (a) (b) (c) Figure 3.14: Filter capacitor line to line voltage and grid-side phase current (top); CM dcbus capacitor midpoint to ground voltage (middle); and FFT of line to line voltage (F1), FFT of grid current (F2), and FFT of CM voltage (F3) (bottom). (a) Case (i)-no damping, (b) case (ii)-passive damping, and (c) case (v)-with active damping. With load of 5.5kW and active damping gain corresponding to ζ =0.7. setup, using (74) and (78). It can be observed from Fig that simultaneous activation of both DMAD and CMAD effectively suppresses oscillations at the corresponding resonance frequencies.

122 Experimental results (a) (b) (c) Figure 3.15: Spectrum of LCL capacitor line to line voltage (F1) and spectrum of dc-bus capacitor midpoint to ground voltage (F2). (a) Case (iii)-with only DMAD, (b) case (iv)- with only CMAD, and (c) case (v)-with both DMAD and CMAD. With active damping gain of ζ =0.7. Table 3.2: State space gain for damping coefficient ζ =0.7. SL.NO. Controller Per Unit Value in Value in Parameter p.u. CT domain DT domain 1 k k k k cm k cm

123 Chapter 3. Control of Three-Phase PWM Rectifier Analysis of the experimental results A set of experiments consisting of testing the setup with no damping, with passive damping, and with active damping activated is performed under loaded conditions. The active damping tests are repeated for different values of damping factors of ζ =0.5, 0.7, 0.9, and 1.0. The calculated E CS is used to evaluate the performance change with gain settings. The E CS for the DM resonance is evaluated for frequencies from 0.75kHz to 2kHz in the filter capacitor line to line voltage signal. CM resonance performance is evaluated by calculating the E CS for frequencies from 1.0kHz to 3kHz for the dc-bus midpoint to ground voltage. Five measurements were made for each operating condition and the average values are tabulated in Table 3.3. The comparison between different tests is as follows: No Damping and Passive Damping The energy contained in signals for differential- and common-mode resonances with no damping is V 2 s and 685V 2 s, respectively. By introducing the damping resistors to the LCL filter, they have been reduced to 711.2V 2 s (65%) and 402.9V 2 s (59%), respectively. It is clearly seen that with passive damping the differential- and common-mode resonances are damped to some extent. Activating only DMAD By activating only DMAD, the DM resonance is reduced. By increasing the damping factor, the DM resonance is effectively damped as can be seen from Table 3.3. However, it is not so effective in damping the CM resonance. Activating only CMAD By activating only CMAD, the CM resonance is reduced. By increasing the damping factor, the CM resonance is effectively damped. The CMAD has almost no damping effect on the measured DM resonance.

124 Experimental results Activating both DMAD and CMAD In comparison with passive damping with ζ =0.2, active damping with ζ =0.5 has slightly higher DM resonance. Whereas, the CM resonance is better damped in active damping. As the damping factor is increased, both the differential- and common-mode resonances are damped more effectively. Activating both DMAD and CMAD simultaneously, in case (v), has better damping compared with cases (iii) and (iv) at the same damping factor. Table 3.3: Energy contained in signals (V 2 s) near the filter resonance frequency. Damping Only DMAD Only CMAD DMAD & CMAD Methods DM CM DM CM DM CM No Damping (100%) (100%) PD R d = 19Ω, ζ =0.2 (65%) (59%) AD ζ = AD ζ = AD ζ = AD ζ = (66%) (50%) (60%) (45%) (56%) (39%) (54%) (37%) Transient performance of the damping methods To test the effects of active damping on transient response, the setup has been tested under step load change from 1kW to 5.5kW on the induction motor. The filter capacitor line to line voltage and phase current corresponding to cases (i), (ii), and (v) are shown in Fig From Fig it can be seen that introduction of active damping does not affect the transient response of the system and it remains stable during the transients of load change.

125 Chapter 3. Control of Three-Phase PWM Rectifier 91 Voltage(V) Current(A) Voltage(V) Current(A) Voltage(V) Current(A) Time(s) (a) Time(s) (b) Time(s) (c) Figure 3.16: Filter capacitor line to line voltage and grid-side phase current for step load change from 1kW to 5.5kW at t =0.1s. (a) Case (i) with no damping, (b) case (ii) with passive damping, and (c) case (v) with active damping with ζ =0.7.

126 Experimental results Experiment Curve Fitting THD% Damping Factor ( ) 1 Figure 3.17: Grid-side current low frequency THD for different settings of the DMAD gains Active damping effects on low frequency THD To evaluate the effects of DMAD on low frequency distortion in the grid current, the grid current spectrum was evaluated between the 3 rd harmonic (150Hz) and the 13 th harmonic (650Hz), while varying the damping factor from ζ =0.1 to ζ =1.0. Frequencies up to the 13 th harmonic were evaluated to check the grid current distortion away from the differentialand common-mode resonances of the filter in power converter. It can be seen from Fig that the introduction of active damping increases the low frequency distortion in the grid current. This is because the active damping feedback effectively multiplies the capacitive current using the state feedback law given in Section This is included in the modulation signal of the power converter. Based on the simulation in Section 3.6.2, this effectively causes an increased admittance of the converter at harmonic frequencies for higher values of the damping gain. If any lower-order harmonics are present in the grid, lower-order currents will flow through the filter. This increases the low frequency THD of line current. Hence, the damping gain of active damping cannot be chosen with resonance damping as the sole objective, and the amount of grid lower-order harmonics must be taken into consideration. The measured results are shown in Fig Comparing the analysis of the converter input admittance, shown in Fig. 3.13, with the experimental results, shown in Fig. 3.17, it

127 Chapter 3. Control of Three-Phase PWM Rectifier 93 can be seen that both follow a similar trend. The increase in DMAD gain increases the admittance of the converter to the harmonics in the grid voltage and distortions in the inverter output voltage. Hence, increase in the DMAD gain increases the low frequency THD of the grid current of the PWM rectifier under practical operating conditions Recommended damping settings Based on the analysis and the evaluation of experimental performance, the following damping settings are recommended: 1) Active damping is preferred over passive damping because of reduction of losses and retention of the effectiveness of the LCL filter. 2) It has been found that a DM damping factor of 0.5 is preferable, as it reduces the energy content near the resonance frequency by about 34%. A damping factor of 0.5 is recommended as long as the line current THD is not excessive. If the line current THD is small, the damping factor can be increased further. 3) CM damping factor of 0.9 provides acceptable performance, as it reduces the energy content near the resonance frequency by around 55%. 4) Simultaneous activation of both differential- and common-mode active damping with these gains provides good overall performance Circulating power test A three-phase, 10kVA, 415V, back-to-back connected power converter is built in the laboratory to validate the test method. The inverter is switched at 5kHz and the PWM rectifier is switched at 10kHz. The inverter is connected to a three-phase, 415V, 5.5kW, star-connected, four-pole SCIM. The SCIM is controlled using V/F speed control scheme. The PWM rectifier is controlled using vector control method [115]. An Altera Cyclone II FPGA platform is used for implementation of the control algorithms of the PWM rectifier and the inverter DFIM rotor voltage The setup has been tested to obtain the rotor voltage at different rotor speeds. To do so, the stator of DFIM is connected to three-phase ac supply and the rotor is rotated by SCIM.

128 Experimental results While monitoring the rotor voltage, the speed of the SCIM is increased from zero to rated speed in the same direction as well as reverse direction. The plot is shown in Fig. 3.10, which compares both analytical rotor voltage based on (81) and experimental measurements. From Fig it can be seen that rotor voltage is minimum when the rotor speed and stator RMF speed are the same and in the same direction. When the speed difference (N RMF N r ) is negative, the DFIM works in the generation mode. At positive speed difference, the DFIM acts as a motor, and regenerative action takes place in the motor drive system Synchronization of DFIM with SCIM To synchronize the DFIM with SCIM, the stator of the DFIM is energized and the rotor is rotated by SCIM. To study the impact of the transient caused by speed mismatch, the rotor terminals are shorted by closing CBr under conditions of different speed mismatch between the stator RMF and the rotor speed. Three different cases have been tested and the results are given below. Case (a) Synchronization at minimum rotor voltage In this case the rotor terminals are shorted when the rotor voltage is at its minimum. The result is shown in Fig. 3.18(a). The dotted line in the figure shows the time when the rotor terminals are shorted. It can be seen that there is no increase in current, and the DFIM and SCIM are synchronized without any transients in the SCIM current. Case (b) 90rpm speed mismatch between RMF and rotor speed In this case the RMF speed is 1500rpm and the rotor is rotating at 1590rpm. The SCIM current is measured and is plotted in Fig. 3.18(b). The SCIM no-load current is 2A peak. The current is increased to 6A peak while shorting the rotor terminals. In this case, the setup can withstand the transients and continues to operate. Case (c) 185rpm speed mismatch between RMF and rotor In this case the RMF speed is 1500rpm and the rotor is rotating at 1685rpm. No-load SCIM current is 2A peak, which is increased to 10A peak after shorting the rotor terminals. The setup cannot withstand the transients; the motor drive protection detects the overload and shuts the inverter off. The result is shown in Fig. 3.18(c).

129 Chapter 3. Control of Three-Phase PWM Rectifier 95 SCIM Current (A) SCIM Current (A) SCIM Current (A) Time (sec) (a) Time (sec) (b) Time (sec) (c) Figure 3.18: The SCIM line current while shorting the DFIM rotor terminals at different speed mismatch between RMF and rotor. The solid lines are SCIM current and the dotted lines show the time when the rotor terminals are shorted. (a) Synchronization at minimum rotor voltage, (b) with 90rpm speed mismatch between RMF and rotor speed, and (c) with 185rpm speed mismatch between RMF and rotor speed.

130 Experimental results 12 SCIM Current (A) Time (Sec) (a) SCIM Current (A) Time (Sec) (b) Figure 3.19: Loading of the motor drive in (a) motoring mode and (b) regenerative mode Loading of the setup To load the setup, the DFIM and SCIM are synchronized as explained in Subsection By changing the speed command to the SCIM, the motoring or regenerative mode can be obtained. The results are shown in Fig The instants of changes in speed command given to the SCIM are shown with the dotted lines. In case (a) the speed command has been increased from 1500rpm to 1685rpm corresponding to 50Hz and 56 Hz input voltage to the SCIM, respectively. The frequency ramps up slowly; hence, the setup goes to fullload condition slowly without any transient overshoot as shown in Fig. 3.19(a). To load

131 Chapter 3. Control of Three-Phase PWM Rectifier 97 the setup in regenerative mode, the speed command is decreased from 1500rpm to 1335rpm corresponding to 50Hz and 44.5Hz input voltage to the SCIM, respectively. The SCIM goes to generating mode and the power is pumped back to the grid through the power converters. The result is shown in Fig. 3.19(b). The measured power in the induction motor drive is used to adjust its speed command so as to ensure constant loading during grid frequency variation Power losses and efficiency The setup has been experimentally loaded to measure the efficiency of the test configuration. A YOKOGAWA WT1600 digital power meter is used to measure the circulating and input powers to the setup. The setup configuration to measure the circulating and input powers is shown in Fig To measure the circulating power in the setup, S 1 should be open and S 2 should be closed. To measure the input power to the setup, S 1 should be closed and S 2 should be open. With this configuration the setup can be tested under two-quadrant condition. The PRS can be used to test the setup under four-quadrant conditions. The setup has been tested under full-load condition. The input power to the setup, which is same as losses in the whole setup, was measured to be 2.15kW, for the circulating power of 5.01kW. The efficiency of the setup can be calculated as follows: 3.7 Summary η% = P cir P in 100 P cir = 100 = 57% (84) 5.01 This chapter focuses on the control issues related to LCL filter damping on CM and DM bases. Also, operation of a test setup where such a PWM rectifier-based motor drive along with a DFIM can be used to evaluate the performance of the power converter is explained. The comparison of passive damping along with the need for active damping for CM and DM LCL filter is presented. A state space approach is used to calculate the active damping gains for the CT and DT models of the filter and to obtain state feedback controller gains in both CT and DT. The analytically derived controller gains are used to implement active

132 Summary damping for different damping factors on a digital controller. The laboratory PWM rectifier with LCL differential- and common-mode filter is tested with different damping methods and different damping conditions. The damping performance is correlated with measurement in terms of the energy contained in signal for both differential- and common-mode damping. The comparison of the results shows the effectiveness of active damping of oscillations in the dc-bus midpoint to ground voltage and LCL capacitor line to line voltage. However, it is also shown that the state feedback based approach for active damping increases the lower-order harmonics in the line currents for high values of DMAD gain. This is shown by correlating the admittance of the power converter at harmonic frequencies and using a weighted admittance function (WY) and the measured line harmonics in the line current. This is due to the presence of lower-order harmonics during practical operation of the power converter and in the grid voltage. The analysis of DMAD and CMAD performances is validated by the results from a 10kVA laboratory power converter. A circuit configuration to test and load the power converter is analysed. The test configuration makes use of only one power converter, which is the motor drive converter to be tested. A simple V/F control of the motor drive inverter is sufficient for SCIM control. The method for smooth start up and loading of the test setup is explained in detail. This has been validated experimentally, and it is shown that using the explained method the DFIM and SCIM were synchronized without any electrical transients or mechanical oscillations. The sequence of steps to perform such a test has been explained. The efficiency of the test setup configuration at full-load test was measured to be about 57%, which is in line with the analytical expected value of 60%. The circulating power test has been validated in both motoring and regenerative operating modes.

133 Chapter 4 EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier Ground leakage current and EMI filtering are important design aspects of power electronic converters. The use of grid-connected power converters is increasing in applications such as battery chargers, regenerative drives, FECs for renewables, PWM rectifiers, active filters, and PFC [ ]. One reason for the popularity of power converters is that they work very efficiently. As the technology of IGBTs and other switches advances, it is possible to operate power converters at a higher frequency and with high efficiency. However, very fast switching action generates high dv/dt. This will excite the parasitic capacitances and increase the challenge in designing power converters with low ground leakage current and minimal EMI/EMC issues [39, 40, 147]. In the case of motor drive applications, high dv/dt due to switching action can cause problems like high EMI noise level, motor terminal voltage doubling, leakage current, and bearing current [95, ]. These problems are especially severe when long cables are used to connect the power converters to the motors. Standards like CISPR 11 and IEC specify the disturbance limits that power converters can have on the grid [5, 124]. The ground leakage current has a tight limit. Because of safety reasons, this limit is even more stringent for domestic applications. One of the standards for the leakage current is VDE V for PV systems. It recommends that if the leakage current is higher than 300mA, the system must be disconnected within 0.3 seconds [6]. High dv/dt caused by the switching action injects narrow peaky current to ground. The leakage current has harmonics from switching frequency to very high frequencies. One of the major challenges faced while designing a power converter is to meet the respective standards for EMI/EMC and ground leakage current. Often a bulky EMI filter is needed to meet the 99

134 100 specifications of the standards. This increases the cost and size of the overall system and reduces the overall system efficiency. However, if EMI/EMC and leakage current issues are taken into account while designing the power converter, it is possible to eliminate or reduce the size of EMI filters. In this chapter, a CM filter is explained along with PWM modulation techniques for single-phase grid-connected power converters to reduce the EMI/EMC noise level and ground leakage current. In Section 4.1, derivation of grid-side CM circuit equations for a single-phase PWM rectifier is provided. Section 4.2 analyses the effects of bipolar and unipolar PWM methods on dc-bus CM voltage. The CM circuit design is detailed in Section 4.3. Section 4.4 provides derivation of CM equations of a single-phase parallel PWM rectifier. The effects of bipolar and unipolar PWM methods on dc-bus CM voltage are analysed. The CM circuit design is detailed. Experimental results, on single-phase PWM rectifier motor drive and single-phase parallel PWM rectifier, are provided, in Section 4.5, to support the analytical predictions. Section 4.6 summarizes the chapter.

135 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 101 PWM Rectifier PWM Inverter MOTOR Figure 4.1: Conventional single-phase PWM rectifier with symmetrical LCL filter [1] connected to a three-phase motor drive inverter with LC filter.

136 Grid-side common-mode voltage analysis 4.1 Grid-side common-mode voltage analysis The circuit in Fig. 4.1 shows a conventional single-phase PWM rectifier with symmetrical LCL filter as suggested in [1]. The PWM rectifier is connected to a three-phase motor drive inverter with LC filter. In the shown topology, the filter inductors are split into two and placed in the line and neutral. The dc-bus CM voltage, v Og, of the conventional single-phase PWM rectifier shown in Fig. 4.1 is defined as, v Og = v P g + v ng. (85) 2 From Fig. 4.1 it can be seen that v P g = V dc + v ng. By substituting v P g in (85) we get: v Og = 0.5V dc + v ng. (86) The voltages v Ag and v Bg can be written in terms of switching states as, Similarly, v Ag = S + a v P g + (1 S + a )v ng By writing KVL equations for the LCL filter circuit we have: = S + a V dc + v ng (87) v Bg = S + b V dc + v ng (88) v Ag = L i di i dt + v cag (89) v Bg = L i di i dt + v cbg (90) v cag = L g di g dt + e g (91) v cbg = L g di g dt Substituting (91) in (89) and (92) in (90) results in, di i v Ag = L i dt + L di g g v Bg = L i di i dt + L g (92) dt + e g (93) di g dt (94)

137 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 103 By equating (87) and (88) with (93) and (94), respectively, di i L i dt + L di g g L i di i dt + L g Adding (95) and (96) and simplifying it results in (97), where, i comi = i i + i i, v ng = 0.5L i di comi dt v Og = 0.5L i di comi dt dt + e g = S a + V dc + v ng (95) di g dt = S+ b V dc + v ng (96) + 0.5L g di comg dt 0.5V dc (S + a + S + b ) + 0.5e g (97) i comg = i g + i g. Substituting (97) in (86) we get, + 0.5L g di comg dt As i g = i g and i c = i c, (98) is simplified as, + 0.5V dc (1 S + a S + b ) + 0.5e g (98) v Og = 0.5V dc (1 S + a S + b ) + 0.5e g (99) The dc-bus CM voltage derived for the circuit configuration shown in Fig. 4.1 is given in (99). It depends on the dc-bus voltage, switching states, and the grid voltage. It can be observed that for different PWM methods, different CM voltage would appear at the dc-bus midpoint with respect to ground. 4.2 PWM methods analysis The high dv/dt in the CM voltage excites the parasitic capacitances, which results in current injection to ground. In this section it is shown that the use of bipolar PWM method can eliminate switching dv/dt in the CM dc-bus voltage. The CM voltage given in (99) consists of two components, the sinusoidal component, which is half the grid voltage, and the PWM voltage, which depends on the switching states. If the switching states are such that the coefficient of the V dc in (99) is constant, then the effect of switching is eliminated in the CM voltage Unipolar PWM method In the case of unipolar PWM method, the modulation signals used to obtain the PWM pulses are d a = Msin(ωt), d b = d a. M is the modulation index. d a and d b are compared with

138 PWM methods analysis (a) (b) Figure 4.2: Switching states of a single-phase H-bridge converter using (a) unipolar PWM method and (b) bipolar PWM method. carrier and fed to the switches. From the switching states within a switching cycle, the value of (1 S a + S + b ) in (99) can be shown to be 1, 0, -1, 0, and 1. This is depicted in Fig. 4.2(a). With this PWM method the CM voltage would have a pulsed voltage superimposed on a sinusoidal voltage. The δv value of the pulses is 0.5V dc and the δt depends on how fast the switching action is taking place in the IGBT legs Bipolar PWM method In bipolar PWM method, the modulation signal is d = Msin(ωt). S a + is calculated by comparing the modulation signal with the carrier. The S + b is equal to (1 S a + ). Hence, the term (1 S a + S + b ) is always equal to zero in (99), which makes the coefficient of the V dc equal to zero. This is shown in Fig. 4.2(b). So, the high dv/dt due to switching actions is eliminated in the dc-bus CM voltage based on (99) and it consists of only sinusoidal waveform with amplitude of half the ac voltage. The use of bipolar PWM method for single-phase grid-connected converters is suggested in [1] to reduce the ground leakage current. However, the circuit is sensitive to the nonidealities. In the case of nonidealities, like dead time mismatch, mismatch in converter-side

139 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 105 Figure 4.3: Switching states of a single-phase H-bridge converter using bipolar PWM method with unequal dead time. inductors, unequal turn on and turn off of the switches, and propagation delays, high frequency pulses with high dv/dt are generated in CM voltage. Fig. 4.3 shows the case of bipolar PWM method with the presence of unequal dead time. The high frequency pulses can be observed in the term (1 S a + S + b ). To obtain the same effective switching frequency, the bipolar PWM switching frequency should be twice the unipolar PWM switching frequency. This causes higher switching losses and lower efficiency in the power converter. However, it is expected that in this case a smaller EMI filter is needed, which has less losses. 4.3 Common-mode circuit design It is shown, in Section 4.2, that if unipolar PWM method is used as the modulation technique for the PWM rectifier, shown in Fig. 4.1, then the dc-bus CM voltage (V Og ) is equal to half the grid voltage and it is free of high frequency noise. However, this is in the case of ideal situations. In the case where the nonidealities like dead time mismatch, mismatch in converter-side inductors, unequal turn on and turn off of the switches, and propagation delays are present, finite pulses are generated in the dc-bus CM voltage. The circuit topology given in Fig. 4.1 is modified such that the system is insensitive to these nonidealities.

140 Common-mode circuit design The condition derived in Section 4.2 shows that the dc-bus midpoint O with respect to ground has a voltage equal to V Og = 0.5e g. In the topology shown in Fig. 4.1, the inductors L g and the capacitors C act as a voltage divider. The voltage V Mg can be obtained as, V Mg = x 1 x 1 + x 2 e g = 0.5e g (100) where, x 1 = x 2 = jωl g + 1 and ω = 2πf. It is observed that both the voltages V jωc Mg and V Og are equal to 0.5e g. Hence, the points M and O can be connected together without current circulation within the circuit. A capacitor is added between points M and g. The capacitor C Mg filters out the dc-bus high frequency noise and prevents the high frequency noise from propagating to the load side. The design of C Mg is done in the manner suggested in Section The value of capacitor C Mg is chosen such that it is reasonably high compared with the parasitic capacitances C p1 and C p2. However, it should be noted that a large value of C Mg leads to large fundamental ground leakage current. Fig. 4.4 shows the circuit configuration given in Fig. 4.1 along with OM connection and capacitor C Mg as CM filter Common-mode equivalent circuit derivation The CM equivalent circuit of Fig. 4.4 is derived as follows. The voltages v AO and v BO can be written in terms of switching states as, v AO = S + a v P O + (1 S + a )v no where, v P O = v no = V dc 2. Similarly for v BO we have, = S a + V dc 2 V dc 2 + V dc S+ a 2 = V dc (S a + 0.5) (101) v BO = V dc (S + b 0.5) (102) By writing KVL from O to M, v AO = L i di i dt + v cam (103) v BO = L i di i dt + v cbm (104)

141 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 107 By equating (101) and (102) with (103) and (104), respectively, Adding (105) and (106) and simplifying it results in (107), V dc (S a + di i 0.5) = L i dt + v cam (105) V dc (S + b 0.5) = L di i i dt + v cbm (106) V dc 2 (S+ a + S + b 1) = 0.5L di comi i + v cam + v cbm dt 2 (107) By writing KVL from M to g, Adding (108) and (109) and dividing by two, v cam = L g di g dt + e g v Mg (108) v cbm = L g di g dt v Mg (109) Writing KCL at node M, v cam + v cbm 2 = 0.5L g di comg dt + 0.5e g v Mg (110) i mid = (i i i g ) + (i i i g) = i c + i c = i comi i comg = i c + i c = C dv cam dt + C dv cbm dt = 2C d dt (v cam + dv cbm 2 i mid i MO = i Mg = C Mg dv Mg dt ) (111) (112) With the help of (107), (110), (111), and (112) the CM equivalent circuit is drawn and is depicted in Fig. 4.5, where, v con = v AO + v BO 2 = 0.5V dc (1 S a + S + b ). (113)

142 Common-mode circuit design PWM Rectifier PWM Inverter MOTOR Figure 4.4: Conventional single-phase PWM rectifier with combined symmetrical LCL filter with CM filter, connected to a three-phase motor drive inverter with LC filter. Figure 4.5: CM equivalent circuit of the single-phase to three-phase motor drive shown in Fig Common-mode circuit analysis With bipolar PWM technique v con is zero. Hence, there is no high dv/dt to excite the parasitic capacitances C p1 and C p2. However, finite v con is generated in practice because of the mentioned nonidealities. If the dead-time circuit is made of analog components, because of tolerances of the capacitances and resistances used in the dead-time circuit, different values of dead-time can be offered to the legs. This causes glitches to appear in the CM voltage. To make sure these glitches do not excite the parasitic capacitances, a path is provided within the filter circuit. This path is recognized by connecting the points O and M together,

143 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 109 (a) (b) Figure 4.6: Grid-side CM equivalent circuit of the filter with (a) low-frequency approximation and (b) high-frequency approximation. as shown in Fig With this connection, if there are any glitches in the CM voltage due to factors such as mismatches in dead time, switching timing delay, mismatch between the legs of the converter, etc., the CM current will circulate inside the filter and will not pollute the grid. A capacitor C Mg is connected to ground, which reduces the high frequency voltage on the dc side of the power converter. The capacitor C Mg is small, of the order of tens of nanofarads. So, at low frequencies it acts as an open circuit. The grid-side CM circuit at low frequency can be approximated as shown in Fig. 4.6(a). The resonance frequency of 1 the filter, for low frequency approximation circuit, is given by f res = 2π L i. As mentioned C before, the v con = 0 for bipolar PWM method. Hence, the resonance frequency is not excited and there is no need for additional CM damping. High frequency equivalent circuit of the CM circuit shown in Fig. 4.5 is depicted in Fig. 4.6(b). The capacitor C Mg will reduce the high frequency voltage between point M and g. The voltage is divided between C p1, C p2, and C Mg as given in (114). C p1 and C p2 represent the parasitic capacitances of semiconductor chips to base plate of the switch module packages. These capacitances are obtained from the device datasheet [117]. By keeping the value of C Mg reasonably high in comparison with C p1 and C p2, the voltage v Mg is reduced. However, a very large value of C Mg will lead to higher fundamental ground leakage currents. C Mg that gives an attenuation of 95% based on (114) is used in the design. The use of C Mg

144 Parallel single-phase PWM rectifier ensures that any subsystem connected to the dc bus will see a reduced CM voltage at high frequencies and with circuit nonidealities. v Mg v con = C p2 C p1 + C p2 + C Mg (114) Addition of capacitor C Mg can cause resonance oscillations in the CM circuit. Because of the value of the C Mg, which is small, the resonance frequency is much higher than the switching frequency. These oscillations need to be damped passively. RC branch passive damping is used in parallel with the capacitor C Mg to damp the resonance oscillations. The LCL filter components are selected using the method suggested in [18]. In the case of unipolar PWM, v con is nonzero. The pulsed shape would be as shown in Fig. 4.2(a). This pulsed voltage will cause high current to circulate in the setup and it also excites the resonance frequency of the filter. Also, the benefits of reduced output ripple in the filter inductors, due to unipolar PWM, are lost. Hence, the use of unipolar PWM is not beneficial for the circuit topology, whereas bipolar PWM has the advantage of reduced CM voltage and ground leakage current. 4.4 Parallel single-phase PWM rectifier Paralleling of power converters increases the overall power rating. It also increases the reliability by achieving higher system redundancy and availability [148]. In high power applications, normally paralleling is used to boost up the power rating of the overall system. This can be done either by direct paralleling of the power switches or by paralleling smaller sized power converter modules. Paralleling power converter modules has the additional advantage of possible use of interleaving carrier for the power converters. Interleaving the carrier shifts the harmonics generated by the power converters. By appropriate selection of interleaving angle it is possible to cancel some of the harmonics [149]. However, carrier interleaving can cause circulation of current between the converters. The current circulation is normally limited by the use of an inter-phase inductor. The circuit in Fig. 4.7 shows a conventional parallel single-phase PWM rectifier with LCL filter. In the shown topology, the filter inductors are split into two and placed in the line and neutral. The LCL capacitor is also split into two series-connected capacitors. L int is the inter-phase inductor between the power converters. If the same carrier is used for both

145 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 111 power converters then the inter-phase inductors are not needed. This case is equivalent to the case where the switching devices are directly connected in parallel. Figure 4.7: Parallel single-phase PWM rectifier with symmetrical LCL filter.

146 Parallel single-phase PWM rectifier CM voltage analysis of parallel PWM rectifier The dc-bus CM voltage v Og, of the topology shown in Fig. 4.7, is defined as, v Og = v P g + v Ng 2 (115) From Fig. 4.7 it can be seen that v P g = V dc + v Ng. By substituting v P g in (115) we get: v Og = 0.5V dc + v Ng (116) The voltages v A1 g, v B1 g, v A2 g, and v B2 g can be written in terms of switching states as, v A1 g = S + a1v P g + (1 S + a1)v Ng = S + a1v dc + v Ng (117) Similarly, v B1 g = S + b1 V dc + v Ng (118) v A2 g = S + a2v dc + v Ng (119) v B2 g = S + b2 V dc + v Ng (120) The interface inductors L int offer low impedance to CM output and high impedance to DM output. Hence, the voltages v Ag and v Bg can be written as, v Ag = v A 1 g + v A2 g 2 v Bg = v B 1 g + v B2 g 2 By writing KVL at the output of the inverter we have: = 0.5V dc (S + a1 + S + a2) + v Ng (121) = 0.5V dc (S + b1 + S+ b2 ) + v Ng (122) v Ag = L i di i dt + v cag (123) v Bg = L i di i dt + v cbg (124) v cag = L g di g dt + e g (125) v cbg = L g di g dt (126)

147 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 113 Substituting (125) in (123) and (126) in (124) results in, di i v Ag = L i dt + L di g g v Bg = L i di i dt + L g By equating (121) and (122) with (127) and (128), respectively, di i L i dt + L di g g L i di i dt + L g Adding (129) and (130) and simplifying results in (131), v Ng = 0.5L i di comi dt where, i comi = i i + i i, v Og = 0.5L i di comi dt + 0.5L g di comg dt dt + e g (127) di g dt (128) dt + e g = 0.5V dc (S a1 + + S a2) + + v Ng (129) di g dt = 0.5V dc(s + b1 + S+ b2 ) + v Ng (130) 0.25V dc (S + a1 + S + a2 + S + b1 + S+ b2 ) + 0.5e g (131) i comg = i g + i g. Substituting (131) in (116) we get, + 0.5L i di comg dt V dc (2 S + a1 S + a2 S + b1 S+ b2 ) + 0.5e g (132) Neglecting device parasitic capacitors, C p1 and C p2, the grid-side and converter-side currents are i i = i i and i g = i g. Hence, (132) can be simplified as, v Og = 0.25V dc (2 S + a1 S + a2 S + b1 S+ b2 ) + 0.5e g (133) The dc-bus CM voltage derived for circuit configuration, shown in Fig. 4.7, is given in (133). It depends on the dc-bus voltage, switching states, and the grid voltage. It can be observed that for different PWM methods, different CM voltage would appear between the dc-bus midpoint O and ground PWM method for parallel PWM rectifier From the CM voltage equation derived in Section 4.4.1, it is evident that if the switching pattern changes, the CM voltage will change. The CM voltage consists of a sinusoidal voltage with magnitude equal to half that of the grid voltage and high frequency pulses superimposed on the sinusoidal voltage. The magnitude of the pulses are ± V dc 2 or ± V dc 4 depending on the switching state. These pulses have very high dv/dt of the order of 1kV/µs depending on the IGBT characteristics. This high dv/dt, which occurs at every instant of switching, excites

148 Parallel single-phase PWM rectifier the parasitic capacitances and injects a peaky current to ground. This causes increased EMI/EMC noise level and also leakage current to ground to be high. From (133) it can be observed that if two of the states are equal to 1 and the rest are equal to 0, then the coefficient of the 0.25V dc would be zero. Hence, no pulses are generated in the CM voltage waveform. In that case, the CM voltage would be equal to half the grid voltage with no high frequency noises. This method ensures that at any instant of time only two states are equal to one. This is done by keeping S a1 + = 1 S + b2 and S+ b1 = 1 S+ a2. So, the CM voltage given in (133) would be, v Og = 0.25V dc (2 (1 S + b2 ) S+ a2 (1 S + a2) S + b2 ) + 0.5e g = 0.5e g (134) The dc-bus CM voltage given in (134) is equal to half the grid voltage and it is high frequency pulse free. In practice, such PWM pulses can be realized by using unipolar PWM method and interleaving the second converter carrier by 180. Fig. 4.8 shows the carriers (Carr1, Carr2), modulation signals (d a, d b ), and the switching states (S a1, + S + b1, S+ a2, S + b2 ). The modulation signals are the same for both converters. For converter 1, the modulation signals d a and d b are compared with Carr1 to generate the switching states S a1 + and S + b1, respectively. The switching states S a2 + and S + b2 for the second converter are obtained by comparing the modulation signals d a and d b with Carr2, respectively. It can be seen from Fig. 4.8 that at any instant of time only two states are in active high condition Common-mode circuit design It has been shown that using unipolar PWM method with 180 interleaved carriers makes the CM voltage sinusoidal. Practically, this may be altered due to nonidealities like dead time mismatch, mismatch in gate drive delays, different switching characteristics of the devices, and error in interleaving angle. In these cases small glitches would appear in CM voltage. These glitches excite the parasitic capacitances and increase the leakage current. To make the circuit insensitive to the aforementioned nonidealities, a connection is made between O and M. In this configuration, inductors L g and capacitors C act as a voltage divider. The voltage V Mg can be obtained using (100). Both voltages V Mg and V Og are equal to half the grid voltage based on (100) and (134), respectively. So the connection OM does not

149 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 115 Figure 4.8: Switching states for a parallel single-phase inverter with 180 carrier interleaving. cause any circulating current to flow within the circuit. A capacitor is added between points M and g as suggested in Section The capacitor C Mg filters out the dc-bus high frequency noise and prevents the high frequency noise from propagating to the load side or grid side. The value of capacitor C Mg is chosen such that it is reasonably high compared with the parasitic capacitances. However, it should be noted that a large value of C Mg leads to large fundamental ground leakage current. Fig. 4.9 shows a parallel single-phase PWM rectifier with symmetrical LCL filter along with the CM filter. The CM equations for the topology shown in Fig. 4.9 are derived as follows.

150 Parallel single-phase PWM rectifier Figure 4.9: Parallel single-phase PWM rectifier with symmetrical LCL filter along with the CM filter. The voltage v A1 O can be written in terms of switching states as, v A1 O = S + a1v P O + (1 S + a1)v NO = S a1 + V dc 2 V dc 2 + V dc S+ a1 2 = V dc (S a ) (135) where, v P O = v NO = V dc 2. Similarly for v B 1 O, v A2 O, and v B2 O we have, v B1 O = V dc (S + b1 0.5) (136) v A2 O = V dc (S a ) (137) v B2 O = V dc (S + b2 0.5) (138)

151 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 117 The voltages v Ag and v Bg can be written as, v AO = v A 1 O + v A2 O 2 v BO = v B 1 O + v B2 O 2 By writing KVL from O to M, By equating (139) and (140) with (141) and (142), respectively, = 0.5V dc (S + a1 + S + a2 1) (139) = 0.5V dc (S + b1 + S+ b2 1) (140) v AO = L i di i dt + v cam (141) v BO = L i di i dt + v cbm (142) 0.5V dc (S a1 + + S a2 + di i 1) = L i dt + v cam (143) 0.5V dc (S + b1 + S+ b2 1) = L di i i dt + v cbm (144) Adding (143) and (144) and simplifying it results in (145), 0.25V dc (S a1 + + S a2 + + S + b1 + S+ b2 2) = 0.5L di comi i + v cam + v cbm dt 2 By writing KVL from M to g, (145) Adding (146) and (147) and dividing by two, v cam = L g di g dt + e g v Mg (146) v cbm = L g di g dt v Mg (147) Writing KCL at node M, v cam + v cbm 2 = 0.5L g di comg dt + 0.5e g v Mg (148) i mid = (i i i g ) + (i i i g) = i c + i c = i comi i comg = i c + i c = C dv cam dt + C dv cbm dt = 2C d dt (v cam + dv cbm 2 i mid i MO = i Mg = C Mg dv Mg dt ) (149) (150)

152 Parallel single-phase PWM rectifier Figure 4.10: CM equivalent circuit of parallel single-phase inverter along with the modifications to the topology. With the help of (145), (148), (149), and (150), the CM equivalent circuit is drawn and is depicted in Fig. 4.10, where, v inv = v AO + v BO 2 = 0.25V dc (2 S + a1 S + a2 S + b1 S+ b2 ) (151) This can be used to study the impact of change in interleaving angle, tolerance in switch switching delay time, and dead time. From Fig. 4.10, it can be seen that the loop consisting of v inv, 0.5L i, and 2C acts as an LC filter. As mentioned before, using unipolar PWM with carrier interleaving angle of 180 results in v inv = 0. In this case the circulating current in this loop is zero. So, the resonant frequency of the loop is not excited; hence, additional CM damping resistor is not needed. In the case of generation of finite glitches in v inv due to nonidealities, it is circulated within the circuit. This prevents propagation of the noise to either load or grid. The loop consisting of 0.5e g, 0.5L g, 2C, and C Mg also acts as an LC filter. The fundamental current circulation in this loop is mainly limited by capacitor C Mg, as the value of C Mg is very small and is of the order of nf. The resonant frequency in this loop could be excited by the grid. Passive damping can be used in this loop to damp the oscillations Insensitivity to nonidealities The CM filter shown in Fig is analysed and the transfer function Icomg v inv is obtained for cases with and without the CM filter. The Bode magnitude plot of the admittance

153 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 119 Table 4.1: Single-phase grid-connected inverter parameter values shown in Fig SL.NO. PARAMETER PER UNIT ACTUAL 1 DC bus voltage V dc V 2 Filter Inductance L i = L g 24.5e 3 900µH 3 Filter Inductance L f 49e 3 1.8mH 4 Filter Capacitance C 72e 3 20µF 5 Filter Capacitance C f 72e 3 20µF 6 Filter Capacitance C y 36e 3 10µF 7 Filter Capacitor C Mg 272e 6 75nF transfer function Icomg v inv is plotted in Fig It can be seen that the admittance of the CM circuit offered to CM current for high frequencies is higher in the case when no CM filter is used. Nonidealities like unequal dead time, interleaving angle error, switching delays, and deviation in value of L i from nominal can generate pulses in v inv. Fig shows that the high frequency noises present in v inv, in the case without the CM filter, find a path with high admittance to ground. This results in the flow of high CM current (I comg ) to ground. The admittance of this path is reduced effectively by introducing the proposed CM filter to the circuit topology. For instance, at switching frequency of 10kHz, the admittance is reduced from -57.7dB to -70dB, and at 100kHz it is reduced from -46.1dB to dB. Hence, the CM filter can provide significant attenuation to ground current even under the nonideal condition of deviation of interleaving angle from 180. This corresponds to condition of finite non-zero value of v inv in the CM equivalent circuit. 4.5 Experimental results Single-phase PWM rectifier connected to a motor drive A 5kW single-phase active rectifier connected to a three-phase motor drive prototype is built in the laboratory to demonstrate the effectiveness of the explained method. The IGBT-based PWM rectifier has a switching frequency of 10kHz for the active rectifier when using bipolar

154 Experimental results No CM Filter With Proposed CM Filter 0 Admittance Frequency (Hz) Figure 4.11: Bode magnitude plot of admittance transfer function I com2 v inv with and without the proposed CM filter. for the CM circuit PWM and 5kHz for the case of unipolar PWM. The switching frequency of the motor-side inverter is 10kHz. The base values are P base =5kVA, V base =240V, and f base =50Hz. The base capacitance and inductance are derived as, P base C base = 2πf base Vbase 2 Vbase 2 L base =. (152) 2πf base P base The values are calculated to be C base = 276µF and L base = 36.7mH. The designed parameter values are given in Table 4.1. A three-phase, 415V, 5kW, 50Hz induction motor is connected to the inverter. The motor is controlled using V/F scheme. For loading purpose the shaft of the induction motor is coupled with a doubly fed induction generator. This configuration for testing and loading the motor drive, given in Section 3.5, allows circulation of power and draws only losses from the grid. The PWM rectifier is controlled using an outer voltage control loop, using PI controller, and an inner current controller loop using PR controller. An Altera Cyclone II FPGA platform is used for the implementation of the control algorithm. The power converter is tested at 3.5kW to validate its normal operation as a grid-connected PWM rectifier. The results are depicted in Fig It can be seen that the current is in-phase with the voltage, indicating the UPF operation. The grid current is almost free of high frequency switching ripple, indicating the effectiveness of the LCL

155 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 121 Current Voltage C1 C2 C1 DC1M 100V/div 0.0V offset C2 DC1M 10.0A/div 0.0V offset Timebase 0.0 ms 5.0ms/div 100kS 2.0MS/s Figure 4.12: Grid voltage and grid current of the power converter operating at 3.5kW as a UPF, 200V/div, 20A/div, 5ms/div. filter. However, it can be observed that finite amount of lower-order harmonics are present in the grid current. This is due to the presence of the lower-order harmonics in the grid voltage. This can be verified by looking at the grid voltage. A flat peak is an indication of the presence of harmonics of the fifth, seventh, eleventh,., order in the grid voltage. The rectifier was tested with both unipolar and bipolar PWM methods and the CM voltage, dc-bus midpoint to ground voltage V Og, is captured. In the case of unipolar PWM shown in Fig. 4.13(a), it can be seen that a high frequency pulsed voltage at 5kHz is superimposed on a 50Hz sinusoidal voltage. These pulses have a high dv/dt of the order of 1kV/µs depending on IGBT characteristics. This high dv/dt, which occurs at every instant of switching, excites the parasitic capacitances and injects a peaky current to ground. On the other hand, CM voltage of the bipolar PWM shown in Fig.4.13(b) is sinusoidal with magnitude of half the grid voltage. Comparing Fig. 4.13(a) and Fig.4.13(b), the high frequency noises in the CM voltage are eliminated in the case where the bipolar PWM method is used. With unipolar PWM method, the effective switching frequency is double the switching frequency. In the case of bipolar PWM method, the current ripple frequency is same as the switching frequency. Hence, with unipolar PWM the ripple current in L i is effectively reduced by half. Comparing bipolar with unipolar PWM method, the bipolar PWM needs to operate its legs at twice the switching frequency to obtain the same level of ripple current in inductor L i as in the case of unipolar PWM.

156 Experimental results C1 C1 DC1M 200V/div 0.0V offset Timebase 0.0 ms 5.0ms/div 100kS 2.0MS/s (a) C1 C1 DC1M 200V/div 0.0V offset Timebase 10.0 ms 5.0ms/div 100kS 2.0MS/s (b) Figure 4.13: CM voltage v Og (i.e., dc-bus midpoint to ground voltage) in the single-phase PWM rectifier, 200V/div, 5ms/div. (a) Case A, no CM filter with unipolar PWM and (b) case B, no CM filter with bipolar PWM. The setup has been tested in a large number of configurations, out of which the following four cases are of interest. Case A no CM filter, as shown in Fig. 4.1, with unipolar PWM. Case B no CM filter, as shown in Fig. 4.1, with bipolar PWM. Case C with only OM connection added to the circuit configuration shown in Fig. 4.1 and with bipolar PWM.

157 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 123 Table 4.2: Power losses and efficiency with bipolar and unipolar PWM. Case Losses (W) Efficiency A % B % C & D % Measurement made at 3.5kW load. Case D with CM filter, as shown in Fig. 4.4, with bipolar PWM. The setup has been tested, with unipolar PWM, and bipolar PWM with and without the filter circuit configuration. Power losses and the efficiency have been measured with the help of YOKOGAWA WT1600 and the results are tabulated in Table 4.2. The switching frequency of bipolar PWM is twice that of unipolar PWM. This causes higher switching losses and lower efficiency. It can be seen that the efficiency is reduced by 2.88% while using bipolar PWM method. The losses and the efficiency of the setup using bipolar PWM with CM filter configuration have been measured. It is seen that addition of the CM circuit topology does not further reduce the efficiency of the power converter. To estimate the effectiveness of the CM filter, conducted noise emission tests have been carried out by connecting a single-phase LISN. The LISN is used with a high-frequency oscilloscope (500MHz, 5 GSa/s, LeCroy 6050) as a receiver. The data captured are processed by the oscilloscope and the FFT of the waveforms is shown in Fig for the frequency range up to 10MHz. Fig. 4.14(a) shows the EMI noise level with unipolar PWM and switching frequency of F sw =5kHz (case A). The EMI noise level with bipolar PWM and F sw =10kHz is shown in Fig.4.14(b) (case B). It can be seen that just by using bipolar PWM method with double switching frequency we can reduce the EMI peak around 0.2MHz by about 20dB. However, because of switching nonidealities this situation is altered. The results for cases C and D are shown in Fig It can be seen that the least EMI noise level corresponds to case D (with OM connection and the capacitor C Mg ). Comparing cases C and D, the peak at 0.2MHz is eliminated and the peak at 3.4MHz is reduced by about 10dB. Comparing cases A and D, it can be seen that in case D the peak at 0.2MHz is reduced by about 40dB, peak

158 Experimental results F1 F1 FFT(C1) 20dB/div 1.00MHz/div Timebase 0.0 ms 1.0ms/div 1MS 100MS/s (a) F1 F1 FFT(C1) 20dB/div 1.00MHz/div Timebase 0.0 ms 1.0ms/div 1MS 100MS/s (b) Figure 4.14: EMI noise level comparison: (a) case A, no CM filter with unipolar PWM and (b) case B, no CM filter with bipolar PWM. 20dBV/div, 1MHz/div. at 0.9MHz is eliminated, and peak around 3MHz is reduced by about 5dB. To see the effectiveness of the CM filter, the setup has been tested with unequal dead times. In the ideal case, both legs of the PWM rectifier use dead time of 3µs. Mismatch in the dead time and different delays in the circuit are simulated by reducing the dead time in one of the legs by 1µs. The results are shown in Fig Fig. 4.16(a) shows the CM voltage, with the circuit as suggested in [1]. It can be seen that the high frequency pulses with magnitude of V dc /2 are superimposed on the sinusoidal voltage. This can inject high peaky current to ground. Fig. 4.16(b) shows the CM voltage with CM filter. It can be

159 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 125 F1 F2 F1 FFT(C1) F2 FFT(C2) 20dB/div 20dB/div 1.00MHz/div 1.00MHz/div Timebase 0.0 ms 1.0ms/div 1MS 100MS/s Figure 4.15: EMI noise level comparison with different filter configurations and with bipolar PWM. Top, case C with OM connection (F 1 ). Bottom (F 2 ), case D with OM connection and with capacitor C Mg. 20dBV/div, 1MHz/div. Table 4.3: Case studies of grid-side and motor-side CM current values with equal dead time of 3µs and with unequal dead time of 3µs and 2µs. Case Grid Side CM Current (ma) Motor Side CM Current (ma) Equal DT Unequal DT Equal DT Unequal DT A B C D seen that with the CM filter the CM voltage stays sinusoidal even when the dead times are not equal. Fig shows the EMI noise level, when unequal dead time is introduced to the system. By comparing Fig. 4.17(a) and Fig. 4.17(b), it can be seen that the amount of current injected to the ground is reduced and the EMI noise level is reduced by about 20dB at 200kHz and 10dB at 900kHz with the CM filter. The grid-side and the motor-side CM currents have been measured in all the tests and the results are tabulated in Table 4.3. Comparing case D with case A, it can be seen that the CM current is reduced by more than four times at the grid side and about 21 times at

160 Experimental results C1 C1 DC1M 200V/div 0.0V offset Timebase 10.0 ms 5.0ms/div 100kS 2.0MS/s (a) C1 C1 DC1M 200V/div 0.0V offset Timebase 10.0 ms 5.0ms/div 100kS 2.0MS/s (b) Figure 4.16: CM voltage with unequal dead time (a) without the CM filter and (b) with the CM filter. 200V/div, 5ms/div. the motor side in case D. However, the grid-side CM current in case D is slightly higher than in case B. This is not a problem as long as the difference is small and the value is within the acceptable standard limits. For instance, standard VDE V indicates that the PV system leakage currents should not be higher than 300mA, and in the case of violations the system must be disconnected within 0.3 seconds [6]. The motor-side ground leakage current with the CM filter configuration is the least among all the cases. It can be observed that with the filter configuration, given in case D and shown in Fig. 4.4, the system is insensitive to the dead time mismatch. The grid-side and the motor-side ground leakage currents remain

161 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 127 F1 F1 FFT(C1) 20dB/div 1.00MHz/div Timebase 0.0 ms 1.0ms/div 1MS 100MS/s (a) F1 F1 FFT(C1) 20dB/div 1.00MHz/div Timebase 0.0 ms 1.0ms/div 1MS 100MS/s (b) Figure 4.17: EMI noise level with unequal dead time (a) without the CM filter and (b) with the CM filter. 20dBV/div, 1MHz/div. almost the same with and without the nonidealities Single-phase parallel PWM rectifier A 7.5kW parallel single-phase PWM rectifier prototype is built in the laboratory to evaluate the effectiveness of the topology. The base values and the designed parameter values are tabulated in Table 4.4. The switching frequency chosen for the converters is 10kHz with unipolar PWM technique. Hence, the effective switching frequency would be equal to 20kHz.

162 Experimental results Table 4.4: Single-phase parallel PWM rectifier circuit parameter values shown in Fig SL.NO. PARAMETER PER UNIT ACTUAL 1 DC bus voltage V dc V 2 Filter Inductance L i = L g µH 3 Inter-phase Inductance L int mH 4 Filter Capacitance C µF 5 Filter Capacitor C Mg nF 6 Switching Frequency f sw kHz 7 P base 1 7.5kVA 8 V base 1 240V 9 f base 1 50Hz 10 C base µF 11 L base mH For loading purpose a 7.5kW variable resistor bank is connected to the dc bus. The PWM rectifier is controlled by an inner current loop using PR controller and an outer voltage loop using PI controller. The digital platform used in the system is an Altera Cyclone II FPGA. The setup is tested at full-rated power to evaluate the normal operation of the PWM rectifier. The results are shown in Fig It can be seen that although the grid voltage has lower-order harmonics, the current is almost free of harmonics. The grid current peak to peak switching ripple current is about 20mA. The THD of the grid current is measured to be 1.23%; this indicates the effectiveness of the LCL filter and the wide bandwidth current controller of the system. The CM voltage of parallel single-phase PWM rectifier was derived and given in (133); here the CM voltage of PWM rectifier is measured with different interleaving angles. The following four cases are considered. Case A with zero interleaving angle. This method is used to just boost the power rating and increase the circuit redundancy.

163 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 129 Current Voltage C1 C2 C1 DC1M 100V/div 0.0V offset C2 DC1M 20.0A/div 0.0V offset Timebase 0.0 ms 5.0ms/div 25kS 500kS/s Figure 4.18: Grid voltage and grid current of the PWM rectifier operating at 7.5kW. Case B with 90 interleaving angle. In addition to the reasons given in case A, this method is used to reduce the ripple current, hence reducing the size of the passive components. Case C with 180 interleaving angle. This is the method that has less ground leakage current and low EMI/EMC noise level when compared with case A and case B. Case D with 180 interleaving angle and with modifications shown in Fig In the case where the interleaving angle is not 180, the OM connection cannot be made. This is due to the CM voltage, which consists of high frequency pulses. In such a case, the OM connection will cause high circulating current to flow within the system. This can be seen from Fig. 4.10, where only the series impedance corresponding to 0.5L i and 2C will limit the circulating current. The leakage rms current is measured for the interleaving angles from 0 to 360. The results are shown in Fig From Fig. 4.19(a) it can be seen that there are several local minima, but the minimum at 180 is the global minimum. The leakage current is reduced from 570mA with 0 interleaving angle to 18mA with 180 interleaving angle corresponding to case C. Fig. 4.19(b) shows the magnified version from 175 to 185, with and without the modifications shown in Fig It can be seen from Fig. 4.19(b) that, without the modifications, the leakage current would be very sensitive to the error in the interleaving angle. For instance, if there is a 1 error in the interleaving angle, the leakage current is increased to twice the value. By adding the circuit modifications explained in Section 4.4.3,

164 Experimental results the leakage current becomes almost insensitive to the interleaving angle error and other nonidealities. It is observed that the modifications further reduce the leakage current by about 50% to 90% for interleaving carrier angles in the range of 175 to 185. The PWM rectifier is tested with the mentioned cases A to D and the CM voltage (dc-bus midpoint to ground voltage V Og ) is captured. The results are shown in Fig Comparing these cases, it can be observed that case A and case B, shown in Fig. 4.20(a) and Fig. 4.20(c), respectively, have high frequency noise superimposed on sinusoidal voltage. However, although the magnitude of the pulses is smaller in case B, high dv/dt that can excite the parasitic capacitances does exist. Whereas, in case C and case D shown in Fig. 4.20(e) and Fig. 4.20(g), respectively, the CM voltage is free of high frequency pulses and it is equal to half the grid voltage. If the CM voltage is free of high frequency pulses with high dv/dt, then the leakage current injected to ground would be minimized. To evaluate the leakage current for these cases, the CM current i comg is measured by measuring the grid-side current of phase and neutral together. FFT is performed on the measured CM currents and the results are shown in Fig It can be seen that the leakage current frequency is same as the switching frequency and its odd harmonics in case A and case B shown in Fig. 4.20(b) and Fig. 4.20(d), respectively. However, although the leakage current in case B is less than in case A, as was expected from CM voltage shown in Fig. 4.20, the total leakage current is high in these two cases. In case C shown in Fig. 4.20(f), the leakage current is reduced drastically due to removal of the high frequency pulses from the CM voltage. In case D depicted in Fig. 4.20(h), the leakage current is further reduced due to addition of OM connection and capacitor C Mg. Note that the division in Fig. 4.20(f) and Fig. 4.20(h) is 2.0mA/div, whereas in Fig. 4.20(b) and Fig. 4.20(d) it is 40mA/div.

165 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier Leakage Current (ma) Interleaving Angle (Degree) (a) Leakage Current (ma) No CM Filter With Proposed CM Filter Interleaving Angle (Degree) (b) Figure 4.19: Measured leakage current of parallel single-phase PWM rectifier as a function of PWM interleaving angles, (a) without the modifications to the circuit topology, as shown in Fig. 4.7, and (b) with and without modifications to the circuit topology.

166 Experimental results C1 C1 C1 C1 DC1M Timebase 200V/div 5.0ms/div 0.0V offset 25kS 500kS/s 0.0 ms (a) DC1M Timebase 200V/div 5.0ms/div 0.0V offset 25kS 500kS/s 0.0 ms (c) F1 F1 F1 F1 FFT(C1) 40mA/div 10.0kHz/div FFT(C1) 40mA/div 10.0kHz/div (b) (d) Timebase 0.0 ms 2.0ms/div 20kS 1.0MS/s Timebase 0.0 ms 2.0ms/div 20kS 1.0MS/s

167 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 133 C1 C1 DC1M Timebase 200V/div 5.0ms/div 0.0V offset 25kS 500kS/s 0.0 ms F1 F1 FFT(C1) 2.0mA/div 10.0kHz/div Timebase 0.0 ms 2.0ms/div 20kS 1.0MS/s (e) (f) C1 C1 DC1M Timebase 200V/div 5.0ms/div 0.0V offset 25kS 500kS/s 0.0 ms F1 F1 FFT(C1) 2.0mA/div 10.0kHz/div Timebase 0.0 ms 2.0ms/div 20kS 1.0MS/s (g) (h) Figure 4.20: CM voltage (dc-bus midpoint to ground voltage VOg) and FFT of CM current icomg (summation of line and neutral currents) of a parallel single-phase PWM rectifier. (a) and (b) the case A with 0 carrier interleaving, (c) and (d) the case B with 90 carrier interleaving, (e) and (f) the case C with 180 carrier interleaving, (g) and (h) the case D with 180 carrier interleaving angle and with modifications to the circuit shown in Fig Note that the ampere per division in (f) and (h) is 2.0mA/div, whereas in (b) and (d) it is 40mA/div. The center frequency in (b), (d), (f), and (h) is 50kHz.

168 Experimental results F1 F1 FFT(C1) 20dB/div 1.00MHz/div (a) Timebase 0.0 ms 1.0ms/div 1MS 100MS/s F1 F1 FFT(C1) 20dB/div 1.00MHz/div (b) Timebase 0.0 ms 1.0ms/div 1MS 100MS/s Figure 4.21: EMI noise level comparison, (a) case A with 0 carrier interleaving and (b) case B with 90 carrier interleaving The EMI tests are carried out, for the four cases described previously, by connecting a single-phase LISN between the PWM rectifier and the grid. A 500MHz, 5GSa/s LeCroy 6050 oscilloscope is used as a receiver. The results are shown in Fig It can be seen that case D, shown in Fig. 4.21(d), has the least EMI noise level. The peaks at 0.1MHz, 0.7MHz, and 2MHz are eliminated in this case. However, although the peak at 4.5MHz is slightly increased, the overall peak reduction is about 30dB.

169 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 135 F1 F1 FFT(C1) 20dB/div 1.00MHz/div (c) Timebase 0.0 ms 1.0ms/div 1MS 100MS/s F1 F1 FFT(C1) 20dB/div 1.00MHz/div (d) Timebase 0.0 ms 1.0ms/div 1MS 100MS/s Figure 4.21: EMI noise level comparison, (c) case C with 180 carrier interleaving and (d) case D with 180 interleaving angle along with modifications to the circuit shown in Fig To evaluate the impact of the method on the efficiency of PWM rectifier, the overall efficiency test is carried out, at 4kW, for the interleaving angles from 0 to 360. The result is shown in Fig. 4.22(a). Fig. 4.22(b) shows the total efficiency of the power converter with 180 interleaving angle along with the modifications as a function of input power. It can be seen from Fig. 4.22(a) that the maximum efficiency is obtained with the interleaving angle of 90, which is 92.7%. This is due to ripple current reduction in the filter inductance. The presented method has an efficiency of 92%, which is 0.7% less than the maximum efficiency. This corresponds to 28W of additional power loss. However, it is expected that a smaller EMI filter is needed for the explained method, which can benefit system efficiency.

170 Summary Total Efficiency (%) Interleaving Angle (Degree) (a) Total Efficiency (%) Input Power (kw) (b) Figure 4.22: Efficiency of parallel single-phase PWM rectifier, (a) as a function of interleaving angles at 4kW and (b) with 180 interleaving angle along with the modifications as a function of input power. 4.6 Summary An LCL filter configuration that can be used with a single-phase grid-connected inverter, which leads to reduced CM current and EMI noise, is explained. The CM voltage for the topology is derived and it is shown that the CM voltage depends not only on the circuit configuration but also on the PWM method that is utilized. Unipolar and bipolar PWM methods have been analysed. Using switching function analysis, it is shown for the filter

171 Chapter 4. EMI and Ground Leakage Reduction in Single-Phase PWM Rectifier 137 configuration in Fig. 4.1 that the CM voltage at the dc bus will be sinusoidal if bipolar PWM is used. The circuit is modified to make the system insensitive to the nonidealities of the inverter. The modification of connecting the LCL filter midpoint to the dc-bus midpoint ensures that there is no high frequency CM excitation of the power converter parasitics, even under nonideal conditions of the inverter. The capacitor C Mg ensures that subsystems connected to the dc bus experience low high-frequency CM voltage. The experiments on the laboratory prototype show that the CM voltage with bipolar PWM is sinusoidal. The conducted noise emission test has been carried out, which confirms the effectiveness of the explained method, by which the peak noise in the EMI spectrum was reduced by 35dB. CM current measurement on a 5kW laboratory prototype indicates that the CM filter configuration using bipolar PWM method will reduce the grid-side CM current by more than four times and the motor-side CM current by 21 times when compared with a baseline case that utilizes unipolar PWM method and without such a filter. An expression for CM voltage is derived for parallel single-phase grid-connected converter. It is shown that, in the parallel single-phase inverter configuration, the CM voltage depends on the employed PWM technique. Unipolar PWM with 180 carrier interleaving angle is shown to provide superior performance from the perspective of ground leakage current and EMI. The explained method made the CM voltage sinusoidal and free of high frequency pulses. The method is able to reduce the ground leakage current from 570mA to 18mA. The ground leakage current is measured with different carrier interleaving angles. It is found that an interleaving angle of 180 has the least leakage current. A modification to the circuit topology, which made the system insensitive to the nonidealities of the power converters, is detailed. The modification is able to further reduce the leakage current by about 48%. EMI test carried out shows that the explained method with the circuit modifications results in improvement of greater than 30dB in the EMI spectrum. Efficiency test was performed for different carrier interleaving angles and with the explained method. It is shown that, without considering the losses in the EMI filter, the efficiency of the explained method is just 0.7% less than the maximum efficiency, which is obtained with 90 interleaving angle.

172 Summary

173 Chapter 5 Ground Current and EMI Measurement for Grid-Tied Power Converter Electromagnetic interference noise is defined as unwanted electrical signal that produces undesirable effects on the equipment itself or on other neighbouring equipment [95]. Standards such as CISPR, IEC, and VDE [5, 6, 124] specify the limits of high frequency noise that equipment can produce. These high frequency noises are more severe in power electronic equipment where the current is switched by fast switches like MOSFETs and IGBTs. Because of switching action of these devices, transients with high dv/dt are generated. Voltage change with high dv/dt transition causes problems such as high EMI noise level and high ground leakage current. Other factors such as higher voltage rating, greater cable length, and higher switching frequency worsen these issues. EMI emission and leakage current reduction in applications, such as battery charger, UPS, renewables, ASD, and PWM rectifier, where the power converters are connected to the grid is vital for ensuring safe operation of the power converter and for not interfering with normal operation of neighbouring equipment. The common practice in industry is to use bulky EMI filters to meet respective standards [5, 6, 124]. However, if the power converter is well designed and the EMI design aspects are taken into consideration, it can either eliminate the need for EMI filters or reduce its size significantly. In this chapter, the EMI generation is explained in Section 5.1. In Section 5.2, a typical EMI filter and its working principle are provided. EMI standards and EMI noise levels are summarized in Section 5.3. CE test equipment and configurations are given in Section 5.4. In Section 5.5, a low-cost LISN design is discussed. The difference between single- and 139

174 EMI generation three-phase LISNs is explained in Section 5.6. Ground leakage current measurement for different grid-connected power converter applications is detailed in Section 5.7. In Section 5.8, experimental results on the fabricated LISN are provided. 5.1 EMI generation The primary reason for generation of conducted EMI emission is the CM current passing through the circuit [95]. The CM current closes its path through the ground, and hence it is also called ground leakage current. The reasons for flow of CM current are the presence of high frequency voltage and the presence of parasitic capacitances. To reduce the CM current, the parasitic capacitances and the high frequency voltage must be reduced. The parasitic capacitances can be reduced by properly arranging the components and shielding [9]. The high frequency voltage can be reduced by choosing a proper circuit topology and PWM method [10]. Fig. 5.1 shows a voltage transient due to semiconductor switching. The dv/dt is about 2.8kV/s. If a parasitic capacitance of 100pF is present, it results in CM current of 280mA. Power circuit wiring acts as a large antenna for the conducted CM current, in which case the CM current may radiate out. Hence, the conducted CM current can become radiated EMI emission. The RE interferes with radio frequency signals. This can cause malfunctioning of other equipment. 5.2 EMI filter Fig. 5.2 shows a typical single-phase EMI filter [150]. It is connected between the power converter and the grid. The CM choke L cm offers a high impedance path for CM currents I cm1 and I cm2. Hence, the CM current is limited by the CM choke. The capacitors C y1 and C y2 are connected from line and neutral to ground. They have low impedance at high frequency and suppress most of the high frequency CM noise at the output. The CM choke of the EMI filter acts as a short circuit for the output differential current. This prevents fundamental voltage drop across the EMI filter. In applications like ASD the EMI filter alone may not be effective. The EMI filters are only effective if used with shielded output cables, which are bonded to the drive frame and motor frame [95]. This ensures that the CM current passes through the shield and not through the ground.

175 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 141 Figure 5.1: Voltage transient caused by IGBT switching. 250V/div, 250ns/div Figure 5.2: A typical single-phase EMI filter. 5.3 EMI standards Standards like CISPR and IEC [5, 124] specify the limits of high frequency EMI noise that an apparatus can inject to grid. These limits are tabulated in Table 5.1, where AV and QP stand for average and quasi-peak, respectively, and classes A and B are the limits for industry and domestic applications. The limit values are in decibel microvolts (dbµv). The conducted EMI test is performed for frequencies from 150kHz to 30MHz. This range is split into three regions: kHz, 0.5-5MHz, and 5-30MHz. The limits are more stringent for domestic applications. That is because the class B limits are mostly needed to eliminate amplitude modulation (AM) radio and TV interference problem.

176 Conducted emission test equipment Table 5.1: Allowable conducted emission levels (dbµv). Class kHz 0.5-5MHz 5-30MHz A B AV(66) AV(60) AV(60) QP(79) QP(73) QP(73) AV(56-46) AV(46) AV(50) QP(66-56) QP(56) QP(60) Class A=EN55011, CISPR11 Class B=EN55022, CISPR22 The standards suggest the use of LISNs between the equipment and the grid for conducted EMI measurements. The LISN stabilizes the line impedance at 50Ω for noise voltage measurement greater than 1MHz. The LISN is explained in detail in Section Conducted emission test equipment Standards specify the equipment needed and how the CE test must be performed. Fig. 5.3 shows a test setup that is used for performing CE test [151]. The shown vertical and horizontal reference planes are bonded to ground. A non-metallic table is needed with height equal to 80cm. The EUT is placed on the table as shown in Fig The EUT should be placed at a distance of 40cm from the vertical reference plane. The LISN is placed below the EUT on the horizontal reference frame and it is bolted to the ground plane. The power cable connecting the LISN and the EUT must be as short as possible and it should not lie on the ground. The LISN is connected to EMI receiver with the help of a coaxial cable. 5.5 LISN design LISN is utilized in order to obtain noise measurements, under different grid conditions, which meets the CE standards. This section presents the fabrication of a three-phase 10kVA LISN that costs less than 5% of commercial ones. The procedure for the fabrication of aircore inductors is explained. The guidelines for selection of components are explained. The simulation and experimental results are presented.

177 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 143 Power cable must be as short as possible LISN is bolted to ground plane Non-Metallic Table Horizontal Reference Plane (Bonded to Ground) Vertical Reference Plane (Bonded to Ground) Figure 5.3: Conducted emission test equipment Line impedance stabilization network (LISN) Standards like CISPER and IEC [5, 124] indicate guidelines for the conducted noise measurement test. These standards propose the use of an LISN between the grid and the EUT. According to the standards, the LISN should fulfil the following requirements [124, 152]: 1- To stabilize the mains impedance in order to standardize the measurement. 2- To filter out the high frequency noise coming from the grid that can affect the measurements. 3- To provide a path for high frequency noise coming from the EUT to the EMI receiver, also providing 50Ω matching connectors for the receiver. A typical three-phase LISN is shown in Fig The circuit is analysed and the output to input transfer functions are derived analytically in the next section LISN circuit topology and transfer function analysis Fig. 5.4 shows a typical three-phase LISN. The resistance, capacitance, and inductance values are tabulated in Table 5.2. There are three terminals available in the circuit, input to the

178 LISN design A B C a b c EUT E To receiver Figure 5.4: Typical three-phase CE compliant measurement setup schematic to measure conducted EMI noise. LISN (V in ), output of the LISN (V out ), and the port for the measurement (V rec ). Three inputoutput transfer functions are considered and their relationships are derived. Bode magnitude plot of each transfer function is plotted in Fig First, we consider the receiver-to-input transfer function ( Vrec V in ); it is given in (153). The Bode plot of (153) is shown in Fig. 5.5(a). It can be seen that the high and low frequency noises, in the input, are well attenuated. The attenuation at 150kHz is about -35dB, and it is more for higher frequencies. The gain at fundamental frequency (50Hz) is about -50dB; this indicates that the power losses in the resistors R 3 are very small. where, V rec V in = K 1 = C 2 C 3 L 1 L 2 C 2 C 3 R 2 R 3 s 2 + C 3 R 3 s K 1 s 4 + K 2 s 3 + K 3 s 2 + K 4 s + 1 K 2 = C 2 C 3 L 1 R 2 + C 2 C 3 L 1 R 3 + C 2 C 3 L 2 R 2 K 3 = C 2 L 1 + C 3 L 1 + C 3 L 2 + C 2 C 3 R 2 R 3 K 4 = C 2 R 2 + C 3 R 3 (153) Second, we consider the transfer function Vout V in. It is given in (154) and plotted in Fig. 5.5(b). It can be seen that the gain is unity for low frequency, and high frequencies are

179 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 145 Table 5.2: Component values of LISN shown in Fig. 5.4 SL.NO. PARAMETER VALUE 1 R 1 10Ω 2 R 2 5Ω 3 R 3 50Ω 1kΩ 4 C 1 4µF 5 C 2 8µF 6 C 3 250nF 7 L 1 250µH 8 L 2 50µH well attenuated. Fundamental drop across L 1 and L 2 at 10kVA, 415V, is about 1.3V, which is 0.55% of the phase voltage and is negligible. CE frequency range of interest is frequencies from 150kHz to 30MHz. In this frequency range the LISN should act as an open circuit. This can be seen from Fig. 5.5(a) and (b). For low voltage EUT up to the range of 100s of kw, the frequency separation of the filter impedance of the converter and the impedance of the LISN is high. If the converter rating is 10s of MW, then this separation would be small and the converter filter impedance would change the performance of the LISN. However, such high power converters do not undergo standard conducted EMI test. V out = C 2C 3 R 2 R 3 s 2 + (C 2 R 2 + C 3 R 3 )s + 1 V in K 1 s 4 + K 2 s 3 + K 3 s 2 + K 4 s + 1 (154) Finally, the transfer function Vrec V out is given in (155) and plotted in Fig. 5.5(c). This transfer function acts as a high-pass filter and passes the higher frequency noises, generated by the EUT, to the receiver. V rec V out = C 3R 3 s C 3 R 3 s + 1 (155) Expected gain of unity above 10kHz satisfies the frequency range of 150kHz to 30MHz where the conducted EMI test is performed. The LISN is specified with resistors R 1 and R 2 that provide sufficient damping. It can be seen from Fig. 5.5(b) that the peak at 4kHz is less than 0dB and there would not be any resonance amplification. Additionally, the EMI frequencies of interest are between 150kHz

180 LISN design k 10k 100k 1M 10M 30M (a) k 10k 100k 1M 10M 30M (b) k 10k 100k Frequency(Hz) 1M 10M 30M (c) Figure 5.5: Bode magnitude plots of LISN transfer functions. (a) Receiver to input Vrec V in, (b) output to input Vout V in, and (c) receiver to output Vrec V out. and 30MHz. The typical switching frequencies are far below the EMI frequency range of interest and the LISN resonance will not affect the CE test results LISN component design The design and fabrication of the LISN circuit shown in Fig. 5.4 require attention to parameter and component selection Resistor selection There are three resistors for each phase. The losses of resistor R i can be approximately calculated as given in (156), where the inductor voltage drops are negligible. The resistors are carbon resistors, which have good high frequency response. C ci is the impedance of the

181 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 147 Figure 5.6: The dimensions of coil L 1 shown Fig.5.7(a). series capacitors. P Ri = ( V inr i X ci +R i ) 2 (156) R i The losses are calculated and found to be P R1 = 0.88W, P R2 = 1.78W, and P R3 = 0.018W at 50Hz. The resistors used for R 1 and R 2 are parallel combination of 20Ω, 1W resistors. So, for R 1 two parallel resistors and for R 2 four parallel resistors are needed. With this kind of arrangement for the resistors R 1 and R 2, a safety factor of two for power dissipation is used. A normal 50Ω quarter-watt resistor can be used as R 3. With these, the power dissipation of each resistor does not cross its limit and they would be in a safe region of operation. The losses have been experimentally measured to be P R1 = 0.98W, P R2 = 1.95W, and P R3 = 0.017W Inductor design In the LISN, the inductors play a vital role. The inter-winding capacitance of inductors should be minimized, especially L 2, which directly affects the measurement data if it is not well designed. For that reason, L 2 is wound as a solenoid that has only one layer of windings. The inductor L 1 can be wound as a multilayer air-core inductor. The inductor L 1 is designed based on Wheeler s formula [153] for a multilayer air-core inductor, given in (157). L = 31.49a2 N 2 (157) 6a + 9b + 10c where, L is the inductance of the coil in microhenry, N is the number of turns, and a, b, and c are the dimensions of the coil shown in Fig. 5.6 in meters. The bobbin of L 1 is made of nylon with a temperature range from -40 o C to approximately +100 o C. The inductor L 2 is also designed based on Wheeler s formula for a single-layer air-core inductor, given in (158). L = 39.37N 2 D 2 18D + 40l (158)

182 LISN design (a) (b) Figure 5.7: Fabricated inductors. (a) Inductor L 1 and (b) inductor L 2. In the equation, L is the inductance of the coil in microhenry, N is the number of turns, Table 5.3: Specification of Inductors L 1 and L 2. Parameters L 1 L 2 Coil Diameter 65mm 75mm Coil Length 30mm 150mm Wire Gauge 11SWG 11SWG No. of Turns No. of Layers 6 1 Inductance Value 250µH 50µH D is the diameter of the coil, and l is the length of the coil in meters. A PVC tube is used as the bobbin for inductor L 2 with the temperature range from -25 o C to approximately +70 o C. The specifications of the inductors are given in Table 5.3. The photographs of the fabricated inductors are shown in Fig.5.7. The inductors are to be located such that the coupling between them is minimized.

183 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 149 BNC Connector, (a) (b) Figure 5.8: Mechanical layout of the designed LISN Capacitor selection The capacitors used in the LISN are plastic film capacitors. The considerations regarding the capacitors are that they have to have low equivalent series resistance (ESR) and equivalent series inductance (ESL). This is especially in the case of C 3, which is the path for high frequency noise generated by the EUT to the receiver. Ceramic capacitors can also be used as they have low ESR and ESL. From the transfer function Vrec V out shown in Fig. 5.5(c), it can be seen that the high frequency gain of this transfer function is unity. However, if the ESL of the C 3 -R 3 branch is high, the unity gain at high frequency is altered. Mechanical layout of the LISN is given in Fig.5.8(a). The circles, rectangles, and squares show the positions of the inductors L 1, inductors L 2, and R-C branches, respectively. The photograph of the laboratory prototype LISN is shown in Fig.5.8(b). 5.6 Single-phase LISN The test configuration given in Section 5.4 is valid for single- and three-phase applications. However, appropriate LISNs are required for single-phase and three-phase applications. Three-phase LISN is detailed in Section 5.5. The same design can be applied for singlephase LISN. The schematic of a single-phase LISN is shown in Fig It can be seen that the single-phase LISN can be obtained by removing one of the phases.

184 Ground current measurement EUT Figure 5.9: Single-phase LISN. 5.7 Ground current measurement In various power conversion system configurations and applications the ground leakage current is measured differently. Ground leakage currents are injected to ground through stray capacitances. These currents return from the ground connection. The direction of leakage current in the phase and neutral is the same Leakage current measurement of single-phase systems The leakage current flow in a single-phase system is shown in Fig If the phase and neutral currents are measured and added up, the DM currents, i.e., I dm, cancel each other and this results in, I m = (I dm + I cmph ) + ( I dm + I cmn ) = I cmph + I cmn = I cm. (159) Hence, by placing a current probe around the phase and the neutral, as shown in Fig. 5.11, at the same time, it is possible to measure the CM current in it.

185 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 151 Figure 5.10: Leakage current flow in a single-phase system. Figure 5.11: Leakage current measurement of single-phase systems Leakage current measurement of three-phase three-wire systems. In three-phase three-wire applications shown in Fig. 5.12, the current probe is placed around the three phases as shown in the figure. The leakage current would be as follows: I m = (I a + I cma ) + (I b + I cmb ) + (I c + I cmc ) = (I a + I b + I c ) + (I cma + I cmb + I cmc ). (160)

186 Ground current measurement Figure 5.12: Leakage current measurement of three-phase three-wire systems. Summation of three-phase balanced currents is zero, i.e., I a + I b + I c = 0. Hence, (160) simplifies to I m = I cma + I cmb + I cmc = I cm. (161) Leakage current measurement of three-phase four-wire systems. To measure the leakage current of three-phase four-wire systems, the current clamp is placed around the three-phase cable as well as the neutral cable. This is shown in Fig The measured current would be as follows: I m = (I a + I cma ) + (I b + I cmb ) + (I c + I cmc ) + ( I n + I cmn ) = (I a + I b + I c I n ) + (I cma + I cmb + I cmc + I cmn ). (162) Summation of three-phase current and the neutral current in three-phase four-wire systems is zero, i.e., I a + I b + I c = I n. Hence, (162) simplifies to I m = I cma + I cmb + I cmc + I cmn = I cm. (163)

187 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 153 Figure 5.13: Leakage current measurement of three-phase four-wire systems Accuracy enhancement of the measurement The power cables of any apparatus are designed such that they are able to carry the rated current. For instance, a single-phase 10kW power converter s cables are designed to carry rms current of 43A plus some margin. Cables capable of handling this current are thick. Hence, the current clamp needed should have a large aperture. Normally, current clamps with large apertures are rated to measure high current. However, the leakage currents are of the order of tens of milliamperes. Measuring milliampere current with a current probe rated for tens of amperes results in inaccuracy of measurement. A method to enhance the accuracy is to use multiple turns as illustrated in Fig. 5.14(a). Then the measured value is divided by the number of turns. In this way the accuracy of the measurement is enhanced. Fig. 5.14(b) shows a current clamp measuring current in a ten-turn loop. In this case the result should be divided by ten. 5.8 Experimental results The LISN based on the circuit configuration given in Fig. 5.4 is built in the laboratory. The frequency response plot of the LISN is obtained using an AP Instruments Inc. 200 Network Analyzer. The results are shown in Fig Comparing Fig and the analytical re-

188 Experimental results (a) (b) Figure 5.14: Use of multiple turns with current clamp: (a) schematic and (b) experiment. sponse shown in Fig. 5.5, we can see that the experimental results and analytical calculations match till around 2-3MHz. Beyond 3MHz the experimental frequency response shows lower attenuation in Vrec V in and Vout V in. To investigate the reason for the deviation, the frequency response of individual L 1 and L 2 inductors is obtained and is shown in Fig Fig. 5.16(a) shows the admittance plot of inductor L 1. It can be observed that at around 1MHz the effects of parasitic capacitances come into the picture. This is also the case in Fig. 5.16(b), which shows the admittance plot of L 2. One possibility is that the inter-winding capacitance can cause this kind of behaviour; the other possibilities are the capacitances of the probes and the limitations of the network analyser. To investigate the reason, another inductor is fabricated in the laboratory with inductance of 50µH with N=30 turns, D=14.5cm, and l=30cm. The conductors are placed with a pitch of 10mm between the conductors. Capacitance between two conducting surfaces can be calculated by the well-known equation of C = ɛ A, where ɛ is the permittivity of a d homogeneous medium, A is the surface of the conductor, and d is distance between two conductors. In the new inductor design the surface of the conductor is reduced by a factor of about 5 and the distance between two conductors is increased by a factor of about 15. So, the capacitance between two turns will be reduced by a factor of about 75. So the inter-winding capacitances are reduced drastically. The admittance plot of this inductor is obtained and is shown in Fig. 5.16(c). It can be seen that the same patterns are captured with the new inductor. It is also observed that the network analyser had an input capacitance of 25pF. This would resonate close to 4MHz with the LISN inductance. From this experiment we can

189 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter k 10k 100k 1M 10M (a) k 10k (b) 100k 1M 10M k 10k 100k Frequency(Hz) 1M 10M (c) Figure 5.15: Measured frequency response of (a) Vrec V in, (b) Vout V in, and (c) Vout V rec of the LISN. draw the conclusion that this deviation is due to the limitation of the network analyser and not the inter-winding capacitances of the inductors Conducted emission test The LISN is used to evaluate an SMPC and a three-phase motor drive. The results are shown in Fig and Fig Fig. 5.17(a) shows the CE test result of a three-phase motor drive. The background noise, which is due to sampling of the high frequency oscilloscope, is about 30dB; this is shown in Fig. 5.17(b). If the background noise is taken into account, it would be expected that the measured noise level comes below the 60dBµV recommended by CISPER standard. A single-phase SMPC is connected between two lines of the LISN. The CE test is performed and the results are shown in Fig. 5.18(a). This result can be validated with the help of CM current, which is the summation of the line and neutral currents. The CM current is measured with the help of a TCP300 Tektronix current probe with the bandwidth

190 Summary Admitance(mho) Admitance(mho) Admitance(mho) k 100k (a) 1M 10M k 100k (b) 1M 10M k 100k Frequency(Hz) 1M 10M (c) Figure 5.16: Admittance plot of (a) inductor L 1, (b) inductor L 2, and (c) the newly designed 50µH inductor with N=30 turns, D=14.5cm, and l=30cm. of 100MHz. The CM current is scaled by a factor of 50; this is due to 50Ω termination of the CE test. The scaled CM current is shown in Fig. 5.18(b). Comparing Fig. 5.18(a) and Fig. 5.18(b), it can be seen that they tally with each other. A high frequency oscilloscope 500MHz LeCroy 6050 is used as a receiver. The signal is sampled at the rate of 100M samples per second, the number of samples per cycle (50Hz) is 2M samples. To obtained the spectra shown in Fig and Fig. 5.18, FFTs on data are performed in MATLAB and the results are plotted in dbµv. 5.9 Summary EMI generation and filters are detailed in this chapter. Respective standards for EMI measurement and the limits of the EMI noises are provided. EMI test equipment and test configurations are pointed out. The need for LISN is explained. A low-cost LISN is fabricated using components that are easily available in the laboratory. The laboratory prototype LISN

191 Chapter 5. Ground Current and EMI Measurement for Grid-Tied Power Converter 157 Noise Level[dBµV] Noise Level[dBµV] MHz 1MHz 10MHz 25MHz (a) Frequency 0 0.1MHz 1MHz 10MHz 25MHz Frequency (b) Figure 5.17: CE test results of (a) three-phase motor drive and (b) background noise of the high frequency oscilloscope. materials cost about Rs This is less than 5% of that of commercial single-phase certified LISN of similar voltage and current rating. Attention must be paid to the component parasitics for assembling in the laboratory LISN. Different leakage current measurements in different applications are explained. The effectiveness of the fabricated LISN is checked with laboratory measurements on an SMPC and a three-phase adjustable speed motor drive. The tests provide a good assessment of the EMI characteristics of the power electronic equipment.

192 Summary Noise Level [dbµv] Noise Level [dbµv] MHz 1MHz 10MHz 25MHz (a) MHz 1MHz 10MHz 25MHz Frequency (b) Figure 5.18: CE test results of (a) single-phase SMPC and (b) CM current of the SMPC scaled by LISN factor of 50.

193 Chapter 6 Integrated CM Inductor for Parallel Interleaved Converters The power level of power converters can be increased by paralleling smaller rated power converters [50, 51, 148]. Paralleling increases the power rating of the system; it can also increase the reliability of the system by achieving higher system redundancy and availability [52]. The grid current distortion can be reduced through carrier interleaving [53 56]. Phase shifting the carrier of parallel converters shifts the harmonic components of the converters and can result in cancellation of harmonics. This also provides the ability to reduce the switching frequency at higher power levels for the interleaved converters, thus reducing the switching losses. However, carrier interleaving can cause circulation of current between the converters. The circulating current consists of low frequency as well as high frequency components. The low frequency component is close to the fundamental frequency and the high frequency component is around the switching frequency. The high frequency circulating current is due to turning on of the top switch of one converter and bottom switch of the second converter, which belong to the same phase group, at the same time. The low frequency component is due to output voltage mismatch between the converters. This causes unbalanced load sharing in parallel connected converters. Circulation of current increases power loss, saturates the inductors, causes instability, and causes overstress or even damage to power semiconductor devices. Control methods [57 59] are reported in the literature to minimize and limit the circulating current in parallel converters. For limiting the high frequency circulating current, inter-phase inductors are required. For reducing the switching frequency ripple, passive filters like L or LCL filters are used. Integration of inter-phase inductor and boost inductor of the passive filters into a 159

194 160 Figure 6.1: Parallel single-phase PWM converters with inter-phase inductors and LCL filter. The solid boxes contain the components incorporated into the integrated CM inductor. single electromagnetic equipment results in reduction in size and cost. This is addressed in this chapter. Section 6.1 explains carrier interleaving, circulating current, and inter-phase inductor of parallel converters. Section 6.2 provides a combined boost and inter-phase inductor structure proposed in the literature. Section 6.3 details a novel integrated CM inductor (ICMI). Section 6.4 explains the steps involved in the designing of ICMI. Inter-phase inductance, boost inductance, and reluctance calculations of the ICMI are given in Section 6.5. A design example of ICMI is detailed in Section 6.7. In Section 6.8, finite element analyses of the ICMI are provided. Section 6.9 compares ICMI design and other designs. Experimental results on the laboratory prototype are shown in Section Section 6.11 summarizes the chapter.

195 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 161 Figure 6.2: Interleaved carriers with interleaving angle of α= Parallel interleaved converters The operation of transformer-less power converters, with common ac and dc buses, in parallel offers a number of benefits that are discussed in Section 4.4. The advantage of eliminating the transformer is the increase in the power density of the overall system. The primary drawback of such systems is the circulating current between the parallel converters. The topology shown in Fig. 6.1 consists of two parallel single-phase H-bridge PWM converters with inter-phase inductor, L int, between same phases of the converters. An LCL filter is used to filter out the switching frequency component in the output currents. The topology shown in Fig. 6.1 is considered for the analysis in this chapter Interleaving of carriers It is possible to reduce or eliminate certain switching harmonics by interleaving the carrier [56]. Interleaving can also reduce the ground leakage current and EMI noise level; these are explained in Chapter 4. Interleaving is done by shifting one of the carriers by desired angle α. Fig. 6.2 shows the interleaved carriers with an interleaving angle of α= Circulating current In parallel converters with interleaved carriers, there exist time durations when the top switch of one converter and bottom switch of the other converter, which belong to the same

196 Parallel interleaved converters Figure 6.3: States of the top switch of first converter, S + a1, and the bottom switch of the second converter, S a2, of phase a. phase group, are ON at the same time. This is equivalent to application of a short circuit across the dc bus and results in the flow of high circulating current within the system. If this happens in an unprotected power converter, it can result in damage to the power converter. Fig. 6.3 shows the states of the top switch of the first converter, S a1, + and the bottom switch of the second converter, Sa2, of phase a. If these two switches are ON at the same time, a short circuit is applied to the dc bus. It can be seen from Fig. 6.3 that, for instance, with a modulation signal of d a =0, the states of the switches S a1 + and Sa2 are the same, and they turn ON and OFF simultaneously Inter-phase inductor To limit the circulating current and prevent damage to the power converter switches, interphase inductors are introduced to the power converter. The inter-phase inductors offer a high impedance path for the circulating current. This ensures that the circulating current is limited to a small value. They should provide a low impedance path for the output current. This is to prevent large voltage drop across the inter-phase inductor for normal power flow. An inductor with a center tap, as shown in Fig. 6.4, can be used as an interphase inductor. From the dot position it can be seen that the inductor acts as a normal

197 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 163 Figure 6.4: An inductor with a center tap used as an inter-phase inductor. inductor with impedance equal to 2πf sw L int for circulating current and acts as a short circuit for output current, where f sw is the switching frequency and L int is the inductance value of the inter-phase inductor. 6.2 Combined boost and inter-phase inductor The output current is filtered with the help of an LCL filter. The LCL filter consists of gridside inductor L g, filter capacitor C f, and the boost inductor L b. It has been suggested in [2] to integrate the boost inductor and the inter-phase inductor into a single magnetic structure. In the suggested configuration, the main inductance is used as inter-phase inductor, while the leakage inductance serves as boost inductor. The structure of the inductor designed in [2] is depicted in Fig. 6.5(a), and it represents a magnetic structure with unequal air gaps. Although this design reduces the cost and the weight of the overall system, it is not an optimized design in terms of factors such as core geometry and limits of the inductance values that are feasible. First, the windings are on the side limbs, while the center limb, which has double cross section, does not have any windings. Hence, for the structure shown in Fig. 6.5(a), for a condition of equal air gap and given number of turns, less inductance can be obtained compared with the case when the windings are placed on the center limb. Second, the core requires different air gaps for the center and side limbs. Such a core structure is not standard geometry. Thus, manufacturing this magnetic structure would be difficult, especially for amorphous cores that are hard to machine. Third, in high power applications

198 Combined boost and inter-phase inductor (a) (b) (c) Figure 6.5: Structure of ICMI. (a) The magnetic structure given in [2]. (b) ICMI fluxes path due to the circulating currents (dotted lines) and output currents (dashed lines). (c) ICMI winding connections. with higher operating current, high main circulating path inductance and low and accurate leakage inductance are needed. This is especially so for LCL filters where the optimum inductance requirement can be small [18]. In the configuration shown in Fig. 6.5(a), the minimum leakage inductance occurs when the center limb is completely removed. Lesser leakage inductance would not be geometrically feasible. There can be large tolerance in the value of the inductance, in case of large air gap,

199 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 165 due to uncertainty in the fringing flux effects. The ICMI design detailed in this chapter is able to overcome these design issues of the CM inductor that is used for interleaved operation of parallel connected inverters. 6.3 Integrated CM inductor (ICMI) Fig. 6.5(b) and Fig. 6.5(c) show the ICMI. Fig. 6.5(b) shows the flux paths for the circulating current using dotted lines and the output current using dashed lines. The winding connections are shown in Fig. 6.5(c). In the shown configuration, the windings are split into two identical side windings and a center winding. The ratio of splitting the windings is dictated by the ratio of the boost inductance to the inter-phase inductance value. The center winding is split into two identical windings; the windings are connected in series with the center tap connection M taken out as shown in Fig. 6.5(c). The windings on the center limb are wound in a bifilar manner. Hence, the leakage inductance of the center winding is very small and can be neglected. As mentioned before, the leakage inductance of the ICMI is used as boost inductor. The leakage inductance of the shown topology is equal to the inductance of a side winding plus leakage inductance of the center winding. As the leakage inductance of the center winding can be neglected, the leakage inductance of the ICMI would be equal to the inductance of a side winding. Hence, for a given core and air gap, the boost inductor value can be controlled by changing the number of turns in the side windings. The main inductance, which is the inductance between points A 1 and A 2, is used as inter-phase inductor. The inter-phase inductance value is controlled by changing the number of turns in the center winding. Thus, for a given air gap and core size, the number of turns in side windings required to obtain the desired boost inductance is first chosen. Then, the number of turns in the center winding is chosen to get the required value of inter-phase inductance. The steps for designing the ICMI using standard C-type amorphous cores are given in the next section. 6.4 Integrated CM inductor design The flowchart for designing the ICMI is depicted in Fig The steps involved in the design procedure are explained here.

200 Integrated CM inductor design Figure 6.6: Flowchart for designing the integrated CM inductor.

201 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters Core 1 Core 2 Core 3 Core 4 Core Figure 6.7: Ratio of core reluctance to total reluctance as a function of air gap, for different core sizes. Step 1- calculate the desired inductance values for boost inductor, L b, [18] and interphase inductor, L int, based on the power converter requirements. Step 2- calculate the wire gauge required based on the rating of the individual H-bridge converter. Step 3- choose the smallest core size from the available cores under evaluation. The available cores are chosen based on the area product of the cores [154]. A sufficient number of core sizes with area product higher than the calculated value in (164) are considered for evaluation. W a A c = L inti 2 p (10 4 ) 2B max JK w (164) where, W a is window area of the core in cm 2, A c is cross-sectional area of the core in cm 2, I p is the peak current, B max is the maximum peak flux density in tesla, J is the current density in A.cm 2, and K w is the winding factor. Step 4- calculate the minimum air gap required for the chosen cores such that the variation in core reluctance will not affect the total inductance by more than 10%. Set the air gap required to be equal to the minimum air gap. Fig. 6.7 shows the variation in core reluctance by total reluctance versus air gap for different core sizes. This plot can be used to define the minimum air gap required.

202 Inductance calculation Step 5- using the traditional inductor design procedure [154], calculate the number of turns, N 1 and N 2, required for the side windings to obtain the desired boost inductance value L b. Using (169), given in Section 6.5.1, calculate the total number of turns needed for the center winding to obtain the required value of inter-phase inductance L int. Step 6- cross-check whether the calculated total number of turns (N 1 +N 3 ) for the selected core can be held in the window area of the core, considering the winding factor K w. If the selected core fails to hold the total turns calculated, then choose the next larger core size, from available cores, and re-evaluate starting from step 4. K w =0.4 is normally chosen for windings with round conductors. Step 7- calculate the maximum flux density in the core based on the peak current of the power converters. If the maximum flux density is higher than the saturation flux density or any desired flux density level B de, then increase the air gap by 10%, and re-evaluate starting from step 5. For amorphous cores, B sat of 1.5T is used for the design. Step 8- the outputs are the core size, the air gap, and the number of turns designed for the ICMI. The inductance value is proportional to the cross section of the core; it is also proportional to square of the number of turns. With respect to cost, copper wire is cheaper than amorphous cores. The cost of copper is about Rs. 600 per kilogram, whereas that of the amorphous material is about Rs. 900 to 1200 per kilogram (in year 2014). To reduce the cost and the size of the inductor, it is preferable to cut back on the use of core material than that of copper. Extra care is needed in this case to keep the maximum flux density below the saturation flux density or below a desired level. The aforementioned steps ensure that the core is chosen properly and the cost and the size are kept low. Additionally, the air-gap length is selected such that the flux density in the core is neither too small that the core is underutilized, nor too large that the core operates near the saturation limit. 6.5 Inductance calculation Inter-phase inductance calculation The ICMI with individual windings voltage drops and fluxes due to circulating current is shown in Fig. 6.8(a). The inter-phase inductance, inductance between terminals A 1 and A 2,

203 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 169 (a) (b) (c) Figure 6.8: ICMI with (a) individual winding voltage drops and fluxes due to circulating current. (b) Magnetic equivalent circuit for circulating current. (c) Core geometric dimensions. limits the circulating current. It is calculated as given below. V int = V 1 + V 3 + V 2 (165) Each voltage drop can be written in terms of the number of turns in the winding and the flux in the corresponding limb as, dϕ 1 V int = N 1 dt + N dϕ 3 3 dt + N dϕ 2 2 dt (166) The number of turns in windings 1 and 2 are equal, N 1 =N 2. The circulating current is same in these windings. Hence, from the symmetrical structure of the core and windings it can

204 Inductance calculation be concluded that, ϕ 1 = ϕ 2 = ϕ 3 2 = ϕ 2 (167) The (166) is simplified using (167) as, dϕ 1 V int = 2N 1 dt + N dϕ 3 3 dt = (N 1 + N 3 ) dϕ dt (168) Equation (168) shows that the structure shown in Fig. 6.8(a) is equivalent to an inductor with the same core structure but only center winding with number of turns equal to N=N 1 +N 3. Thus, the total number of turns can be obtained as given in (169). N = L int R (169) where, R is the reluctance of the structure shown in Fig. 6.8(b) and is defined in Section Boost inductance calculation As explained in Section 6.3, the center winding does not have a significant effect on the boost inductance. The number of turns for the side windings can be designed using (170). N 1 = L b 2R (170) Reluctance calculation Fig. 6.8(b) shows the magnetic equivalent circuit of the ICMI for circulating current. The equivalent circuit is drawn with N effective turns on the center limb of the ICMI. Fig. 6.8(c) shows the dimensions of the core used in the ICMI. The reluctances R t, R c, and R s are the corresponding reluctances of the core. R gs and R gc are the reluctances of the side and center air gaps, respectively. These are calculated as follows: R t = 1 µ o µ r L c1 A c, R s = 1 µ o µ r L c2 A c, R c = 1 µ o µ r L c2 2A c R gs = 1 µ o g, R gc = 1 g (171) A c µ o 2A c where, A c is the crosssectional area of the core shown in Fig. 6.8(c) and is calculated as A c =A B. L c1 and L c2 are the magnet lengths shown in Fig. 6.8(c). µ o and µ r are the

205 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 171 magnetic permeabilities of air and the core material, respectively. reluctances are calculated as follows: The core and air-gap R core =R t + R s + 2R c (172) R gap =R gc R gs (173) The total reluctance is calculated as R = 1 F (R core + R gap ) (174) where, F is the fringing factor [155] and is equal to F = 1 + 2g Ac Ln 2C g (175) 6.6 Modification of ICMI for use in single converter Fig. 6.9 shows a single-phase grid-connected power converter with LCL filter and CM choke, proposed in [3]. In the shown configuration, the dc-bus midpoint is connected to the LCL capacitor midpoint. In case unipolar PWM method is used, the dc-bus midpoint voltage consists of switching frequency pulses. This connection can cause circulation of current (CM current) within the power converter [10]. The magnitude of the CM current depends on the dc-bus voltage, switching frequency, and the LCL filter components. The CM choke is added to the circuit to increase the impedance of the loop offered to the CM current. This results in reduction of CM current. The next section provides modifications to the ICMI to make it suitable for the configuration shown in Fig Modified ICMI The ICMI structure shown in Fig. 6.5(c) is modified and shown in Fig. 6.10(b). The modification consists of opening the center tap point M and changing the connections shown in Fig. 6.5(c). The boost inductors of LCL filter and CM choke of Fig. 6.9 are depicted in Fig. 6.10(a). Three passive components are needed to realize the structure shown in Fig The modified ICMI integrates these components into a single magnetic structure. Fig. 6.10(b) shows the sense of the windings and the connections of the modified four-terminal ICMI. In this structure, the leakage inductances are used as boost inductors, and the main

206 Design example Figure 6.9: Single-phase grid-connected power converter with LCL filter and CM choke, proposed in [3]. inductances are used as a CM choke. Main inductances are the inductances from points A to D and E to H. Fig. 6.10(c) shows the fluxes in the core due to DM current, i dm. For DM current, the center winding fluxes are the same in magnitude but in opposite direction; thus, they cancel each other and only the fluxes due to side windings exist in the core. Hence, in DM, the center windings act as short circuits and only side windings contribute to forming the boost inductors. Fig. 6.10(d) shows the fluxes in the core due to CM current, i cm. In this mode, fluxes are not cancelled and all the windings contribute to forming the CM choke. 6.7 Design example In this section an ICMI design example is given for the topology shown in Fig The total power rating of the considered system is 7.5kW with grid voltage of 240V rms. The current rating of each converter is about 16A rms, while operating at UPF full load. The switching frequency is 10kHz. The design steps 1 to 8 from Section 6.4 are explained below in a design example. Step 1- The designed values for inter-phase and boost inductances are L int =20mH and L b =900µH, respectively. This makes sure that the circulating current is less than 2A peak or 1.2A rms, which is around 4% of the total current rating. Step 2- The wire gauge chosen is SWG 11. This wire can carry rms current of 20A; the

207 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 173 (a) (b) (c) (d) Figure 6.10: (a) The LCL filter and CM choke shown in Fig (b) Sense of the windings and the connections of the proposed ICMI. (c) Fluxes in the core due to DM current, i dm. (d) Fluxes in the core due to CM current, i cm. current density chosen is J=3 A.mm 2. Step 3- Metglas AMCC series has been chosen, based on the area product calculation (164), and listed in Table 6.1. Step 4- To calculate the air gap, the ratio of core reluctance by total reluctance has been calculated for different air gaps. The results are plotted in Fig From the figure it can be seen that by choosing the air gap of 1.5mm for each limb, the effect of variation in the total inductance due to change in the core reluctance would be around one tenth. This is to

208 Design example Core Table 6.1: ICMI core and winding parameters evaluation Part No. Side Windings Center Windings B max (N 1 ) (N 3 ) (T) 1 AMCC AMCC AMCC AMCC AMCC make the ICMI design less sensitive to core parameter variations. Step 5- The number of turns for the side windings and center winding is tabulated in Table 6.1. Step 6- The number of turns that can be held in a window of a core is calculated as N p = W ak w A w (176) where, N p is the possible number of turns that can be accommodated in the window area of core, W a is the window area, K w is the winding factor, and A w is the area of cross section of a single wire. The possible number of turns N p along with the required number of turns N 1 +N 3 has been calculated and depicted in Fig From the figure it can be seen that the first two cores cannot hold the required number of turns; hence, they are omitted and cannot be used. Step 7- To calculate the maximum flux density B max in the core, we have to calculate the maximum flux density due to circulating current and the maximum flux density due to the output current, and the summation of these two flux densities should be less than the saturation flux density. B max can be calculated using L int îcir B max = { 2(N 1 + N 3 ) + L bîi } 1 (177) N 1 A side where, î cir is the peak high frequency circulating current i cir =0.5(i 2 -i 3 ) shown in Fig A side is the cross-sectional area of the side limb, and î i is the maximum output peak current of individual power converters. The calculated B max is tabulated in Table 6.1. It is seen that none of the core flux densities would be higher than the saturation flux density. Hence,

209 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters AMCC0200 AMCC0250 AMCC0320 AMCC0400 AMCC0500 Figure 6.11: Maximum number of turns that can be accommodated in the window area of cores, and the required number of turns for different core sizes. none of them needs to be omitted. Step 8- The smallest core among the remaining cores is AMCC0320, which is selected for making the ICMI. The ICMI is redesigned with air gaps of 0.5mm and 1.0mm. The results are given in Table 6.2. It can be seen that it is possible to select AMCC0200 core with g=0.5mm. In this case, the maximum flux density is 1.14T. However, the number of turns needed (N 1 + N 2 ) is close to the possible number of turns (N p ). Hence, the windings must be wound with extra care to be accommodated in the window area of the core. The core AMCC0250 can also be used for designing the ICMI. However, this core and AMCC0320 are almost the same size. The core AMCC0250 is only 72g lighter than AMCC0320. It can be observed from Fig. 6.7 that choosing a smaller air gap makes the overall reluctance of the ICMI more dependent on the core parameters and properties. These properties and parameters have a greater tolerance to manufacturing and environmental conditions such as temperature. It can also be observed that choosing a smaller air gap leads to a higher B max in the ICMI. This is an indication of higher level of core utilization with smaller overall core size but higher core power loss density. Hence, the final choice of air gap can be made only after thermal evaluation of the ICMI.

210 Finite element analysis of ICMI Table 6.2: ICMI core and winding parameters evaluation Air gap Core Total Turns Possible Turns B max (mm) Part No. (N) (N p ) (T) AMCC AMCC AMCC AMCC AMCC AMCC AMCC AMCC AMCC AMCC Finite element analysis of ICMI To analyse the ICMI core flux density levels and flux linkage paths, the ICMI has been modelled using FEM. The numerical analyses are done in 2D using FEMM package [156]. The grid used in the numerical simulation consists of nodes, and the boundary is kept far enough away from the magnetic structure. The simulation has been performed with three current profiles. First, the profile with only output current and no circulating current, is shown in Fig. 6.12(a). This is used to evaluate the boost inductance L b. Second, the profile with the circulating current only, is shown in Fig. 6.12(b). This provides the inter-phase inductance L int value. Third, the profile with combined output and circulating currents, is shown in Fig. 6.12(c). This corresponds to the case of the maximum flux density, B max, in the core. In this situation the circulating current is at its peak value and has a polarity that is the same as that of the current in the left side windings (N 1 ). This corresponds to the situation where the circulating current polarity is the same as that of the left side winding, N 1, and the current is at the peak value. This results in maximum flux density in the left limb of the ICMI. It can be observed that the maximum flux density shown in Fig. 6.12(c) is

211 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 177 (a) (b) (c) Figure 6.12: Flux density and flux linkage plot of the ICMI due to (a) output current only, (b) circulating current only, and (c) combined output and circulating currents.

212 Comparison between ICMI design and other designs 0.74T, which is in agreement with the calculated maximum flux density given in Section 6.7. The error between the calculated and simulated maximum flux densities is less than 3%. The simulated values of L b and L int are 19.54mH and 985µH, respectively. The error between calculated values and simulated values of L b and L int is 2.3% and 9.4%, respectively. Flux linkage outside the magnetic component (external flux) should be kept as small as possible. The external flux heats up any nearby metallic objects and causes increased losses. Extra care should be taken while designing a magnetic structure to keep the external flux low and provide paths inside the cores. The flux lines are shown in Fig It can be seen that most of the flux lines are inside the core and the external flux is negligible. 6.9 Comparison between ICMI design and other designs An inductor with unequal air gap, Fig. 6.5(a), has been designed to compare with the ICMI design. For the sake of comparison, the side leg air gap and the core size were kept same for both methods. It was found that the total number of turns needed was 208 to obtain the desired value of L int. To get the desired inductance value for boost inductor, the center limb air gap should be adjusted. It is found that even by removing the center limb completely the desired value of 900µH cannot be obtained. Hence, it can be observed that significantly higher values of L int and smaller values for L b can only be achieved by the ICMI design approach Separated inter-phase and boost inductor design Separated inter-phase and boost inductors are designed to compare with the ICMI. The following three cases are considered: Case A with separate inter-phase inductor and two boost inductors, one for each leg, as shown in Fig. 6.13(a). Case B with separate inter-phase inductor and a boost inductor between the inter-phase inductor and the output filter, as shown in Fig. 6.13(b). Case C is the ICMI structure shown in Fig. 6.5(c). The inter-phase inductors in case A and case B are not identical. Additionally, the boost inductance value in case B is half the boost inductance value in case A. The current rating

213 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 179 (a) (b) Figure 6.13: Separated inter-phase and boost inductor: (a) case A with two boost inductors, one for each leg, and (b) case B with a boost inductor between the inter-phase inductor and the output filter. of the boost inductor in case B is double with respect to case A. Design parameters of the separated inter-phase and boost inductors are tabulated in Table 6.3. Table 6.3: Design parameters of the separated inter-phase and boost inductors. Inductor Core Size Inductance Value Air-gap B max Turns Inter-phase Inductor case A AMCC mH 1.5mm 0.16T 138 Inter-phase Inductor case B AMCC mH 1.5mm 0.153T 145 Boost Inductor case A AMCC µH 1mm 1.19T 58 Boost Inductor case B AMCC µH 1mm 1.2T Inter-phase inductor design The inter-phase inductor is used to reduce the circulating current between the power converters. The inter-phase inductor is a normal inductor with a center tap. The circulating current is quite small due to high inter-phase inductance value. However, half of the output current, i 1, is passing through each winding of the inter-phase inductor. Hence, the conduc-

214 Comparison between ICMI design and other designs Table 6.4: Comparison between different inductor design cases. Case Number of Core Copper Length of C Cores Weight Weight Copper Wire A 4 sets 5.5kg 3.5kg B 3 sets 5.4kg 3.43kg C 2 sets 4.3kg 2.7kg 57.25m (SWG11) 44.6m + 5.9m (SWG11) (SWG8) 44.3m (SWG11) tors current rating should be equal to rms of i 1 2 +i cir. In case A, it can be seen that, the boost inductor also limits the circulating current. Hence, to get the same effective inter-phase inductance as in case B, the inter-phase inductor value in case A should be L inta =L int -2L b. Whereas, in case B, the inter-phase inductor value is equal to L intb =L int. Among the available cores given in Table 6.1, the smallest core which can hold the required number of turns for inter-phase inductor is AMCC0320 in both the cases. The design parameter is tabulated in Table 6.2. It can be seen that the maximum flux density in the core is 0.16T and 0.153T for cases A and B, respectively, and the cores are underutilized. This is due to the need for large window area capable of holding the windings. So, big cores with large window areas are required. It is possible to use materials like ferrite core that have the saturation flux density of 0.2T to 0.5T, but, to have a fair comparison, amorphous core is chosen for the inter-phase inductor Boost inductor design The boost inductors for the cases shown in Fig are designed and their parameters are given in Table 6.3. In case A, two boost inductors, one for each leg, are needed. The AMCC050 core size is used with 58 turns for each inductor. In case B, one boost inductor is used. The core size is AMCC0100 with 32 turns. The conductor area for boost inductor in case B should be double with respect to case A. SWG8 is chosen for the boost inductor in case B.

215 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 181 Table 6.5: Designed and measured parameters of the integrated CM inductor SL.No. PARAMETER Value 1 Designed Inter-phase Inductance L int 20mH 2 Designed Boost Inductance L b 900µH 3 Measured Inter-phase Inductance L int 19.81mH 4 Measured Boost Inductance L b 935µH 5 Side Windings N 1, N 2 40turns 6 Center windings N 3 100turns 7 Air-gap g 1.5mm 8 Conductor Gauge SWG 11 9 Core Size AMCC Comparison between ICMI and separated boost and interphase inductor The comparison between the three mentioned cases is tabulated in Table 6.4. The ICMI needs only two sets of AMCC0320, whereas case A needs two sets of AMCC0320 along with two sets of AMCC050. Case B needs two sets of AMCC0320 along with one set of AMCC0100. The total core weight of ICMI is kg. This is 21% and 19.6% less than case A and case B, respectively. The length of the copper wire needed for ICMI is the least. In fact, the ICMI needs less copper wire with respect to the inter-phase inductors. This is due to greater diameter of the outer layers of the inter-phase inductor. In the inter-phase inductor, all the turns are around the center limb with greater diameter than the side limb. The ICMI reduces the overall weight of the magnetic structure by 22.2% and 20.7%, respectively, corresponding to comparison with cases A and B.

216 Experimental results (a) (b) Figure 6.14: (a) The fabricated integrated CM inductor for a 7.5kW, 240V, single-phase inverter. (b) The thermal image of the ICMI after running the setup for two hours at full-load condition under natural convection cooling Experimental results The ICMI prototype has been built in the laboratory; the designed parameters are given in Table 6.5 and the photograph of the ICMI is shown in Fig. 6.14(a). The fabricated inductors have been tested with 7.5kW two parallel single-phase grid-connected converters with interleaved carrier. Unipolar PWM method with switching frequency of 10kHz is employed as the modulation technique. The setup has been tested at full-load condition continuously, as a STATCOM, for about two hours, and the thermal image of the ICMI is obtained using a FLUKE Ti20 Thermal Imager camera. The thermal image is shown in Fig. 6.14(b). It can be seen, from Fig. 6.14(b), that the maximum temperature of the ICMI is 92 C. In this case, the ICMI is cooled by natural convection. The operating temperature of the amorphous cores is specified in the datasheet to be from -20 C to +155 C. Class F insulation grade is used along with these cores. It can be seen that the maximum temperature attained is within the operating temperature range of the cores and the insulations. A 30W fan is attached to the ICMI to check the effects of forced cooling on the temperature profile. It is observed that the maximum temperature settles down at 71 C, which is 21 C less than in the case of natural cooling. The ambient temperature is 25 C. Converter currents and their harmonic spectra are shown in Fig. 6.15(a) and Fig. 6.15(b), respectively. It can be seen that the fundamental currents supplied by each converter are

217 Chapter 6. Integrated CM Inductor for Parallel Interleaved Converters 183 C1 C2 C1 DC1M C2 DC1M 10.0A/div 10.0A/div 10.0V offset -10.0V offset Timebase 0.0 ms 10.0ms/div 10kS 100kS/s (a) F1 F2 F1 FFT(C1) F2 FFT(C2) 4.00A/div 4.00A/div 4.00kHz/div 4.00kHz/div Timebase 0.0 ms 10.0ms/div 10kS 100kS/s (b) C1 F1 C1 DC1M F1 FFT(C1) 1.00A/div 200mA/div 2.00V offset 4.00kHz/div Timebase 0.0 ms 10.0ms/div 10kS 100kS/s (c) Figure 6.15: Current waveform in the parallel inverters. (a) Converter currents, (b) converter currents harmonic spectra, and (c) circulating current with its harmonic spectrum.

218 Summary Current Voltage C1 C2 F1 F2 C1 DC1M C2 DC1M F1 FFT(C1) F2 FFT(C2) 20.0A/div 200V/div 10.0A/div 100V/div 0.00V offset 0.00V offset 4.00kHz/div 4.00kHz/div Timebase 0.00 ms 10.0ms/div 10kS 100kS/s Figure 6.16: Grid voltage and grid current and their harmonic spectra. almost the same and the circulating current between the converters is small. The circulating current is measured and shown in Fig. 6.15(c) along with its harmonic spectrum. From this, it can be seen that the fundamental circulating current between the converters is almost zero and the high frequency peak circulating current (10kHz component) is around 1.5A. Grid voltage and current and their spectra are shown in Fig It can be seen that the switching frequency ripple component is effectively filtered out in the grid current by the LCL filter using the ICMI as the boost side inductor. The THD of the grid current is calculated to be 1.93% Summary An ICMI structure and its design are detailed, which integrates the boost inductor and the inter-phase inductor, for use in parallel interleaved converters. It makes use of standard core geometries, which improves manufacturability. A step-by-step design procedure of the ICMI is presented. The proposed design reduces the size and cost of the overall system. Experimental results on a 7.5kW parallel single-phase converter show that the fundamental circulating current is about zero and the high frequency peak circulating current between the converters is less than 1.5A. Although a parallel single-phase power converter is presented, the design can also be extended to parallel three-phase power converters.

219 Chapter 7 Conclusion and Future Work Standards such as CISPR, IEC, and VDE [4 6] specify the allowable limits of high frequency EMI noise and ground leakage current that a grid-connected power converter can generate. Several works are available in the literature addressing these issues by designing separate EMI/CM filters [7, 8]. Typically, EMI/CM filters are bulky and increase the size and cost of the overall system. However, it is possible to design DM filters such that the components of the DM filters are used in CM circuit to reduce electromagnetic noises. This potentially eliminates or reduces the size of the EMI/CM filter needed to meet the standards. This is the main theme of the present work. EMI and ground leakage current issues and solutions are investigated. Different design methods and configurations are studied, which address these issues. Experimental test results are provided for experimental validations. The following sections highlight the contributions of the thesis. 7.1 Integrated CM and DM filters EMI noise level and ground leakage current of grid-connected power converters have stringent limits. The common practice in industry is to use bulky EMI/CM filters. The use of properly designed power converters and filters results in elimination or size reduction of the needed EMI filters. In the present work, three-phase, single-phase, and parallel single-phase PWM rectifiers are considered Three-phase PWM rectifier In Chapter 2, an integrated CM and DM filter is proposed for three-phase PWM rectifiers. The proposed filter consists of an LCL filter along with three additional capacitors, C y1, 185

220 Integrated CM and DM filters Figure 7.1: Schematic of grid-connected ASD with LCL filter, dc bus common-mode filter, and dv/dt filter at inverter terminal for the motor load. C y2, and C Mg, as shown in Fig The design procedure specifies that the capacitors C y1 and C y2 need to be sized similar to the LCL filter capacitor C and that they need not be large capacitors. The capacitor C Mg is chosen such that its capacitance is reasonably high in comparison with the parasitic capacitances C p1 and C p2. It is found that C Mg of 100nF satisfies this objective for power level of the order of 10kW. Detailed procedures to design the filters have been obtained as a part of this work. The proposed filter topology aims to restrain the high frequency CM voltage, due to PWM rectifier, from affecting the load. It also keeps the switching frequency current components, along with third harmonic current components that occur due to advanced PWM techniques, within the power converter. The filter topology ensures that there is no need for large oversizing of the LCL filter inductors because the third harmonic circulating current can be designed to be less than 3% of the rated current. Conducted noise emission test has been carried out, which shows the effectiveness of the designed CM filter. It is shown that the CM current at motor side is reduced by 400% by the filter. The proposed filter needs minimal modification of the LCL filter to meet the above CM performance as it only involves the addition of three capacitors to the circuit. A split-capacitor passive damping method is employed for damping the resonant oscillations in DM and CM circuit. The losses in the damping resistors are measured to be less than 40W. The increase in power loss in the damping resistors because of the filter modification is less than 2.5W for a 10kW power converter. Hence, significant EMI reduction can be obtained

221 Chapter 7. Conclusion and Future Work 187 PWM Rectifier PWM Inverter MOTOR Figure 7.2: Single-phase PWM rectifier with combined symmetrical LCL filter with CM filter, connected to a three-phase motor drive inverter with LC filter. using the proposed filter, with minimal increase in component count and at a similar level of power converter efficiency Single-phase PWM rectifier Chapter 2 addresses the EMI noise level and ground leakage current of three-phase gridconnected power converters. However, single-phase grid-connected power converters are widely used in applications such as traction and transportation, which need to meet the EMI/EMC standards. This is addressed in Chapter 4 In this chapter, an LCL filter configuration that can be used with a single-phase gridconnected inverter, which leads to reduced CM current and EMI noise, is proposed. The proposed configuration is shown in Fig The CM voltage for the topology is derived, and it is shown that the CM voltage depends on the circuit configuration and also on the PWM method. Using switching function analysis, it is shown that the CM voltage at the dc bus will be sinusoidal if bipolar PWM is used. The connection between the LCL filter midpoint and the dc-bus midpoint ensures that there is no high frequency CM excitation of the power converter parasitics even with power converter nonidealities. The capacitor C Mg ensures that subsystems connected to the dc bus experience low high-frequency CM voltage. The capacitance value of C Mg is chosen to be reasonably high with respect to the power converter parasitics. The experiments on the laboratory prototype show that the CM voltage with bipolar PWM is sinusoidal and is in agreement with the presented analysis.

222 Integrated CM and DM filters The conducted noise emission test has been carried out, which confirms the effectiveness of the explained method, by which the peak noise in the EMI spectrum was reduced by 35dB. CM current measurement on a 5kW laboratory prototype indicates that the CM filter configuration using bipolar PWM method will reduce the grid-side CM current by more than four times and the motor-side CM current by 21 times when compared with a baseline case that utilizes unipolar PWM method and without such a filter. The drawbacks of the proposed method are in terms of power converter ac-side current ripple, efficiency, and reliability. In the proposed method, only bipolar PWM technique can be used. The use of unipolar PWM method causes high circulating current to flow within the power converter. The efficiency of the proposed method is less than the baseline case. Because the bipolar PWM method is used, the grid current THD is higher in comparison with the baseline Parallel single-phase PWM rectifier A single-phase grid-connected PWM rectifier is proposed in the first part of Chapter 4. The proposed configuration reduces the EMI noise level and ground leakage current effectively. However, the configuration has drawbacks, which have been mentioned in the previous section. These drawbacks can be rectified by using parallel connected power converters and properly interleaving the carriers. This is proposed in the second part of Chapter 4. The proposed configuration is shown in Fig An expression for CM voltage is derived for parallel single-phase grid-connected converter. It is shown that, in the parallel singlephase converter configuration, the CM voltage depends on the employed PWM technique. Unipolar PWM with 180 carrier interleaving angle is shown to provide superior performance from the perspective of ground leakage current and EMI. The explained method makes the CM voltage sinusoidal and free of high frequency pulses. The method is able to reduce the ground leakage current from 570mA to 18mA. The ground leakage current is measured with different carrier interleaving angles. It is found that an interleaving angle of 180 has the least leakage current. Modifications to the circuit topology that made the system insensitive to the nonidealities of the power converters are detailed. The modifications are able to further reduce the leakage current by about 48%. EMI tests carried out show that the explained

223 Chapter 7. Conclusion and Future Work 189 Figure 7.3: Parallel single-phase PWM rectifier with symmetrical LCL filter along with the CM filter. method with the circuit modifications results in improvement of greater than 30dB in the EMI spectrum. Efficiency test was performed for different carrier interleaving angles and with the explained method. It is shown that, without considering the losses in the EMI filter, the efficiency of the explained method is just 0.7% less than the maximum efficiency, which is obtained with 90 interleaving angle. However, a drawback is the requirement for an inter-phase inductor, L int, in addition to the boost inductors L b. 7.2 Integrated CM inductor The power level of power converters can be increased by paralleling smaller rated power converters. Paralleling increases the power rating of the system; it can also increase the reliability of the system by achieving higher system redundancy and availability. The grid

224 Active damping of LCL resonance current distortion can be reduced through carrier interleaving. Phase shifting the carrier of parallel converters shifts the harmonic components of the converters and can result in cancellation of harmonics. This also provides the ability to reduce the switching frequency at higher power levels for the interleaved converters, thus reducing the switching losses. However, carrier interleaving can cause high frequency circulating current between the converters. The high frequency circulating current is limited with the help of inter-phase inductor. For reducing the switching frequency ripple, passive filters like L or LCL filters are used. Integration of inter-phase inductor and boost inductor of the passive filters results in reduction in size and cost. In Chapter 5, an ICMI structure and its design are detailed, which integrates the boost inductor and the inter-phase inductor, for use in parallel interleaved converters. It makes use of standard core geometries, which improves manufacturability. A step-bystep design procedure of the ICMI is presented. The proposed design reduces the size and cost of the overall system. Experimental results on a 7.5kW parallel single-phase converter show that the fundamental circulating current is about zero and the high frequency peak circulating current between the converters is less than 1.5A. Although a parallel single-phase power converter is presented, the design can also be applied to parallel three-phase power converters. 7.3 Active damping of LCL resonance Tight limits of the standards on injection of harmonic currents into the grid have opened a research area on the higher-order filters for grid-connected applications. LCL filters are commonly used in grid-connected power converters to meet these standards. However, the resonance oscillations need to be damped using active or passive damping. Passive damping is simple and more reliable. However, passive damping increases the power loss. In Chapter 3, a comparison of passive damping along with the need for active damping for the CM and DM LCL filter is presented. State feedback based approach is used for active damping. The state feedback controller gains are calculated in CT and DT domains. The analytically derived controller gains are used to implement active damping for different damping factors on a digital controller. The comparison of the results shows the effectiveness of active damping of oscillations in the dc-bus midpoint to ground voltage and LCL capacitor line to line voltage. However, it is also shown that the state feedback based approach for active damping increases the lower-order harmonics in the line currents for high values of DMAD

225 Chapter 7. Conclusion and Future Work 191 gain. This is shown by correlating the admittance of the power converter at harmonic frequencies and using a weighted admittance function (WY) and the measured harmonics in the line current. This is due to the presence of lower-order harmonics during practical operation of the power converter and in the grid voltage. It is found that DMAD gain of 0.5 and CMAD of 0.9 are preferable. Simultaneously activating DMAD and CMAD provides good overall performance. If the background THD of the grid voltage is small, the DMAD can be increased. The analysis of DMAD and CMAD performances is validated by the results from a 10kVA laboratory power converter. 7.4 Circulating power test setup Burn-in tests are performed to test devices at conditions similar to operating conditions. Burn-in tests, normally, continue for sufficiently long time to allow the temperatures to stabilize. For high power applications, burn-in tests need high power sources and loads in the testing laboratory. In Chapter 3, a circulating power method to test a motor drive power converter is proposed. The proposed method draws only losses from the grid. A circuit configuration to test and load the power converter is analysed. The test configuration makes use of only one power converter, which is the motor drive converter to be tested. A simple V/F control of the motor drive inverter is sufficient for SCIM control. The method for smooth start up and loading of the test setup is explained in detail. The circulating power test has been validated in both motoring and regenerative operating modes. The efficiency of the test setup configuration at full-load test was measured to be about 57%, which is in line with the analytical expected value of 60%. This has been validated experimentally, and it is shown that using the explained method the DFIM and the SCIM motor drives can be synchronized without any electrical transients or mechanical oscillations. This enables long-term tests that can be carried out without major loss of power. 7.5 Future work As the technology of semiconductor devices advances, it is possible to operate these switches at higher frequency and higher efficiency. New devices such as gallium nitride (GaN) and silicon carbide (CiS) have the capability of operating at frequencies ranging from hundreds of khz to a few MHz. It is interesting to evaluate the performance of the proposed methods, for

226 Summary EMI and ground leakage current reduction, for these state-of-the-art devices with ultra-high switching frequencies. Two-level power converters are considered in this work. The filtering and switching frequency needed in multi-level power converters are smaller in comparison with two-level power converters. This makes the multi-level power converters more efficient. To evaluate the compatibility of the proposed methods with multi-level power converters, detailed analyses of the configuration and proposed methods are essential. 7.6 Summary In this thesis, three-phase, single-phase, and parallel single-phase grid-connected power converters have been considered. The power converters are interfaced with the grid using LCL filters. Integrated CM filters for three-phase, single-phase, and parallel single-phase power converters, along with active damping of the resonance oscillations in CM and DM circuit, and ICMI for parallel converters are proposed in this thesis. The proposed methods have been validated by experimental tests carried out on the laboratory test prototype. It is shown that the proposed methods are able to reduce the EMI noise level by about 20dB to 30dB. The ground leakage currents are reduced by about 4 to 50 times in different cases. These reductions in EMI noise level and ground leakage current indicate potential elimination or size reduction of the EMI filter. By reducing the size of the EMI filter the losses are reduced and the efficiency of the overall system is increased. The current THD of the proposed methods has been measured and shown to meet the respective standards. It is also shown that by paralleling single-phase power converters it is possible to use unipolar PWM method with the proposed method. By this, the configuration benefits from double effective switching frequency and the distortion in output line current is further reduced. Size reduction in EMI filters results in reduced overall size and weight of the system and increases the power density of the power converter. The proposed methods do not alter the reliability of the system significantly. This is due to the addition of few passive components to the power converters. The number of passive components is a maximum of three capacitors and a minimum of one capacitor. These capacitors are small, of the order of a few microfarads to a few hundred nanofarads. The cost associated with the proposed methods is negligible compared with that of the overall system. However, the proposed methods reduce the size of the EMI filter, which can result in overall cost reduction of the

227 Chapter 7. Conclusion and Future Work 193 power converter. Thus, the methods proposed in this work are able to significantly improve EMI and ground leakage current performance of the grid-connected power converter, while maintaining similar levels of efficiency, distortion, and reliability.

228 Summary

229 Appendix A Parseval s Theorem Total energy contained in a waveform x(t) summed across all t is equal to the total energy of the waveform s Fourier transform X(f) summed across all of its frequency components f. x(t) 2 dt = X(f) 2 df (178) where, X(f) = F [x(t)] represents the continuous Fourier transform of x(t) and f represents the frequency component of x. Alternatively, for the discrete Fourier transform (DFT), the relation becomes N 1 n=0 x(n) 2 = 1 N N 1 k=0 x(k) 2 (179) where, X[k] is the DFT of x[n]. The expression for E CS between frequency range F 1 and F 2 is E CS = F 2 1 x(f ) 2 (180) F 2 F 1 F =F 1 where, F 1 < F

230 196

231 Appendix B Experimental Setup A 10kVA three-phase back-to-back connected power converter with input LCL filter and output dv/dt filter, a 5kVA single-phase grid-connected power converter with LCL filter, and a 7.5kVA parallel single-phase grid-connected power converter with LCL filter are fabricated in the laboratory for evaluation and experimental validation purposes. B.1 Fabricated power converter specifications The parameter specifications of the power converters are tabulated in Table B.1. Table B.1: Power Converter Specifications. Parameters Three-phase Single-phase Parallel Single-phase Power Converter Power Converter Power Converter Rated Power 10kVA 5kVA 7.5kVA Rated Voltage 415V LL 240V 240V Rated Current 14A 21A 31A DC-bus Voltage 700V 700V 700V Switching Frequency 10kHz 10kHz 10kHz Cooling Method Forced-air Forced-air Forced-air B.2 Details of FPGA digital controller The controller board used is powered with an ALTERA Cyclone II FPGA chip. Fig. B.1 shows the controller board employed in the experimental tests. The details of the controller 197

232 198 B.3. Experimental setup Figure B.1: An ALTERA Cyclone II FPGA based controller board employed in the experimental tests. are provided below: Processor: ALTERA Cyclone II EP2C70F672C8 Number of logic elements: Number of I/O: 422 Clock Frequency: 20MHz Coding: VHDL and Block-Diagram Analog-to-digital converter (ADC) used: Analog Devices AD7864AS-1 ADC Sampling Frequency: 20kHz Computation Frequency: 20kHz B.3 Experimental setup Fig. B.2(a) shows two power converters, sharing the same dc bus, along with passive filters and sensing cards. Auxiliary power supplies and the passive filters are shown in Fig. B.2(b). The power converters shown in Fig. B.2(a) can be configured as a three-phase back-to-back connected power converter, used in Chapters 2 and 3, as well as single-phase parallel connected power converters, used in Chapters 4 and 6. For single-phase grid-connected power converter, one of the power converters is used and the other one is isolated. This configuration is used in Chapter 4. Gate driver (GD) card and protection and delay (PD) card used in the experimental test are shown in Fig. B.3.

233 Appendix B. Experimental Setup 199 (a) (b) Figure B.2: (a) Two power converters sharing the same dc bus. (b) Auxiliary power supplies and the passive filters. Figure B.3: Gate driver card and protection and delay card. The ICMI structure presented in Chapter 6 is shown in Fig. B.4. The parameters of the ICMI are tabulated in Table B.2. Fig. B.5 shows a 5.5kW SCIM coupled with a 7.5kW DFIM,

234 200 B.3. Experimental setup Figure B.4: The ICMI structure presented in Chapter 6. Table B.2: Designed Parameters of the ICMI SL.No. PARAMETER Value 1 Inter-phase Inductance L int 20mH 2 Boost Inductance L b 900µH 3 Side Windings N 1, N 2 40turns 4 Center windings N 3 100turns 5 Air-gap g 1.5mm 6 Conductor Gauge SWG 11 7 Core Size AMCC-320 used in the motor drive experimental test. The nameplate details of the SCIM and DFIM are provided in Table B.3. The fabricated LISN is shown in Fig. B.6. The specifications of the inductors used in the LISN are listed in Table B.4. The cabinet housing a 7.5kW parallel single-phase power converter connected to a three-phase power converter along with the passive filters, sensing cards, and auxiliary power supplies is shown in Fig. B.7. A YOKOGAWA WT1600 digital power meter is used for measuring power and ground leakage current. A high frequency oscilloscope (500MHz, 5GSa/s, LeCroy 6050) is used for capturing data. It is also used as a receiver along with the LISN.

235 Appendix B. Experimental Setup 201 Figure B.5: A 5.5kW SCIM coupled with a 10kW DFIM. Table B.3: Nameplate details of the SCIM and DFIM Parameters SCIM DFIM Manufacturer KIRLOSKAR ELECTRIC BROWN BOVERI SWITZERLAND Power 5.5kw 7.5kw Connection /Y /Y Frequency 50Hz 50Hz Voltage 415V (When connected in ) 415V (When connected in Y) Current 11.0A 15.5A

236 202 B.3. Experimental setup Figure B.6: Fabricated three-phase 10kW LISN. Table B.4: Specifications of Inductors L 1 and L 2. Parameters L 1 L 2 Coil Diameter 65mm 75mm Coil Length 30mm 150mm Wire Gauge 11SWG 11SWG No. of Turns No. of Layers 6 1 Inductance Value 250µH 50µH

237 Appendix B. Experimental Setup 203 Figure B.7: The cabinet housing the power converters.