Institutionen för systemteknik

Transcription

1 Institutionen för systemteknik Department of Electrical Engineering Examensarbete Performance Evaluation of Medium-Power Voltage Inverters Examensarbete utfört i Elektroteknik vid Tekniska högskolan vid Linköpings universitet av Emil Häger LiTH-ISY-EX--15/4828--SE Linköping 2015 Department of Electrical Engineering Linköpings universitet SE Linköping, Sweden Linköpings tekniska högskola Linköpings universitet Linköping

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3 Performance Evaluation of Medium-Power Voltage Inverters Examensarbete utfört i Elektroteknik vid Tekniska högskolan vid Linköpings universitet av Emil Häger LiTH-ISY-EX--15/4828--SE Handledare: Examinator: Martin Nielsen Lönn isy, Linköpings universitet Atila Alvandpour isy, Linköpings universitet Linköping, 24 mars 2015

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5 Avdelning, Institution Division, Department Institutionen för systemteknik Department of Electrical Engineering SE Linköping Datum Date Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport ISBN ISRN LiTH-ISY-EX--15/4828--SE Serietitel och serienummer Title of series, numbering ISSN URL för elektronisk version Titel Title Performance Evaluation of Medium-Power Voltage Inverters Författare Author Emil Häger Sammanfattning Abstract Power inverters, used to convert DC power to AC, are often used in e.g. solar power applications. However, they tend to be impractically large and expensive; as such, power miniaturization is an active research area. In this thesis, several classes of modern power inverters are evaluated and compared with regards to size, efficiency and output quality in order to identify areas of potential improvement. Methods for estimation of THD, power losses and input ripple are created and verified against a simulation of a five-level neutral-point-clamped inverter with SPWM control. Finally, this design is implemented physically and is found to achieve 94.5% efficiency and 7% THD under low voltage laboratory conditions, while remaining smaller than an average textbook. Nyckelord Keywords Inverter, neutral-point clamped, SPWM, switching losses, input ripple, total harmonic distortion

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7 Abstract Power inverters, used to convert DC power to AC, are often used in e.g. solar power applications. However, they tend to be impractically large and expensive; as such, power miniaturization is an active research area. In this thesis, several classes of modern power inverters are evaluated and compared with regards to size, efficiency and output quality in order to identify areas of potential improvement. Methods for estimation of THD, power losses and input ripple are created and verified against a simulation of a five-level neutral-point-clamped inverter with SPWM control. Finally, this design is implemented physically and is found to achieve 94.5% efficiency and 7% THD under low voltage laboratory conditions, while remaining smaller than an average textbook. iii

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9 Acknowledgments Many thanks to my supervisor Martin, who patiently suffered through my many questions without complaint. Likewise, thanks to my examiner Atila, without whose infectious enthusiasm this would never have been done. Finally, my brother: for offering motivation whether he knew it or not. Linköping, Mars 2015 Emil Häger v

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11 Contents Notation ix 1 Introduction Background Problem Specification Limitations Method Theory of Operation Switching Strategies Pulse-width Modulation Multilevel Multilevel PWM Topologies H-bridge Diode-clamped Capacitor-clamped Switched-capacitor Switched-inductor Comparison Practical Considerations Filter Selection Conduction Losses Switching Losses Gate charge Switch-conduction Implemented Architecture Schematic Inverter Gate Drivers Control vii

12 viii Contents Filter Expected Results Ripple THD Efficiency Simulation Results Results Physical Implementation Control Output Behaviour Conclusions Discussion Future Work A Component List 47 B Little Box Requirements 49 Bibliography 51

13 Notation Abbreviations Abbreviation AC DC EMI LBC NPC PWM RMS SC SL SHEPWM SPWM SVM THD ZCS ZVS Meaning alternating current Direct current Electromagnetic interference Little Box Challenge Neutral-point clamped Pulse-width modulation Root mean square Switched-capacitor Switched-inductor Selective harmonic elimination pulse-width modulation Sinusiodal pulse-width-modulation Space vector modulation Total harmonic distortion Zero-current switching Zero-voltage switching ix

14 x Notation Symbols Symbol Meaning C DC C iss f c f o f s I in I L Total DC-link capacitance MOSFET input capacitance Filter cutoff frequency Inverter output frequency Swithing frequency Inverter input current Inverter load current (RMS) m Number of levels in a multilevel inverter m a Amplitude modulation index m f Frequency modulation index (f s /f o ) P in Inverter input power P load Inverter output power P on Switch conduction loss P sw Switching power R in Internal resistance of input DC source, or total resistance between DC source and inverter R on MOSFET on-state resistance r i Input current ripple factor r v Input voltage ripple factor S n The n-th harmonic of a signal S V DC DC supply voltage V in Inverter input voltage Inverter output voltage (RMS) V o

15 1 Introduction 1.1 Background Power inverters are used to convert electric power from DC to AC. They can be used to e.g. run AC-powered household appliances on DC sources such as batteries or solar panels, provide variable-frequency AC for electric motors, or as an intermediate step in DC-DC conversion. Medium-to-high power (kw-scale) inverters tend to be large and bulky, which also makes them expensive and impractical. The need for improvement coupled with the slow pace of innovation led Google to offer a million-dollar price (the Little Box Challenge) to whoever could design a 2 kva inverter. The technical specifications for this contest (appendix B) are used throughout this thesis as a reference point for what constitutes a high-quality inverter. 1.2 Problem Specification The aim of this thesis is to evaluate modern power inverter technologies with regard to size, efficiency and output quality. Several classes of inverter are simulated and the results compared and generalized to higher-level inverters. Particular attention is paid to the power loss problem, and an architecture-independent analytical model is developed to provide quick efficiency estimates without the need for a full simulation. Finally, the models and simulations are checked against reality by implementing one architecture on a prototype board and testing it under low-voltage laboratory conditions. 1

16 2 1 Introduction Limitations Only single-phase inverters are considered; while three-phase inverters are common, they are mostly used for industrial rather than household applications. While most of the thesis applies to modified sine wave inverters, the focus is on pure sine wave inverters. The quality metrics of temperature and EMI (electromagnetic interference) are ignored, as they are not relevant at low power and do not appear in SPICE simulations. In addition, resonant-switch converters are not considered since they generally need a highly inductive load to function properly [1, 2] Method First, the basics of power inverters are reviewed, and several topologies are considered for implementation. Based on the requirements in appendix B, a suitable architecture is chosen. Analytical expressions are derived for various performance metrics, and the complete inverter is simulated in SPICE. Finally, the inverter is implemented physically and its performance evaluated based on measurements.

17 2 Theory of Operation 2.1 Switching Strategies Inverters have a fixed number of discrete output voltage levels. Since the desired output is an ideal sine wave, it is desirable to switch between these levels in a way that reduces total harmonic distortion (THD) as much as possible. THD for a signal S is calculated as rms(s S 1 ). (2.1) rms(s 1 ) Where S 1 is the fundamental frequency component of the signal. THD is usually measured for both voltage and current, but for a pure sine wave inverter with a mostly resistive load composed of only passive components, these values are close enough that listing them both would be redundant. Unless otherwise specified, THD values given are for the output voltage. There are two major switching strategies: pulse-width modulation (PWM) and multilevel. PWM switches rapidly between a small number of output levels, while multilevel inverters switch less frequently between a larger amount of output levels. These methods can also be combined to get some of the benefits of both. As long as an inverter can produce the right number of voltage levels, output quality is largely independent of the specific architecture used. The switching pattern is what matters most, with higher switching frequencies and more output levels generally giving lower THD Pulse-width Modulation With PWM, the output signal is "chopped" along the time axis, as seen in Fig Output switches between positive and negative input voltage, with nothing in 3

18 4 2 Theory of Operation between (bipolar switching). The major downsides of this type of control are the switching losses and electromagnetic interference (EMI) created by the large dv /dt Vo (V) Time (s) Figure 2.1: Output of a PWM-controlled inverter at a low switching frequency. Sinusoidal PWM The control signals for a PWM inverter can be generated by comparing a triangle wave V c at the desired switching frequency f s and a sine wave V m at the output frequency f o (see Fig. 2.2). While the sine is greater than the triangle, the inverter output is positive; otherwise it is negative. This control method is called sinusoidal PWM (SPWM) Vc, Vm (V) Time (s) Figure 2.2: Generation of PWM control signals. The ratio of the sine amplitude to the triangle amplitude is called amplitude modulation ratio and is denoted by m a. With an ideal voltage source at the input, the peak of the output voltage Vˆ o at the fundamental frequency is am a V DC, where a is an architecture-specific constant, usually 1 or 0.5. This means the output can be regulated by changing the amplitude of the sine wave. If the DC source is not ideal, or there is significant resistance between it and the inverter, the input voltage becomes

19 2.1 Switching Strategies 5 V in = V DC I in R in (2.2) where V DC is the nominal voltage of the DC source, R in is its internal resistance plus resistance between it and the inverter, and I in is the input current. The voltage drop over R in means m a must vary with the load to maintain a fixed amplitude of the output voltage. Assuming 100% efficiency (P in = P out ), the input current is I in = V DC 2R in ± which gives the input voltage R in P out V 2 DC R 2 in (2.3) V in = V DC V DC 2 R in P out V 2 DC (2.4) ˆ V o av in. from which the desired m a can be determined using Vˆ o = am a V in m a = Some variations on SPWM involves using different carriers, but for most purposes the in-phase triangle waves are sufficient [3]. Other switching methods, such as selective harmonic elimination (SHEPWM) can give lower THD by completely eliminating harmonics. However, these methods give the switching angles as a function of m a and require solving large sets of nonlinear equations [4], which makes them too computationally intensive for on-line use. Solving for a few different values of m a and storing the results in lookup tables is a possible, though somewhat inflexible, workaround. Harmonics While SPWM does not eliminate any harmonics, it does have the benefit of pushing them to higher frequencies. This means a smaller filter can be used at the output to achieve acceptable (< 5%) THD. The magnitude of the harmonics is independent of the switching frequency used. Only the modulation method matters [2] THD (%) Ma Figure 2.3: THD as a function of m a.

20 6 2 Theory of Operation The total harmonic content is dependent on m a, illustrated in Fig When m a > 1, the output starts to degenerate into a square wave. Fundamental (60Hz) = 324.2, THD= % Mag (% of Fundamental) Frequency (khz) Figure 2.4: Harmonic content of a PWM inverter with m a = 0.97 and f s = 6060 Hz. The location of the harmonics depends on the switching frequency: as seen in Fig. 2.4, the first harmonics appear around f s, the second set around 2f s, etc Multilevel Multilevel inverters "chop" the signal along the amplitude axis (Fig. 2.5). Having more voltage levels requires a greater amount of hardware in the inverter, but it also makes the voltage jumps smaller and gives a better approximation of a sine wave; each level added eliminates another harmonic [2] Vout (V) Time (s) Figure 2.5: Voltage output of a 5-level inverter.

21 2.1 Switching Strategies 7 However, the switching will occur at or near the fundamental frequency, rather than at large multiples of it. The time switches spend in the on-state far exceeds the switching period, so conduction losses will be far greater than switching losses. Since the m a parameter can not be used for control in multilevel inverters, they require a controllable buck- or boost converter (depending on the architecture used) at the input in order to regulate the output voltage. Control Signal Generation In order to eliminate the greatest number of harmonics, a multilevel inverter needs to switch at precise angles. The half-height method from [1] finds the ideal switching angles to be halfway between the angles where a sine wave would reach the available voltage levels, i.e ( ) { 2i 1 α i = sin 1, i 1, 2... m 1 } m 1 2 (2.5) where m is the number of output levels in the inverter. Using a microcontroller with a lookup table of the ideal switching angles is a simple and effective way to achieve the desired control. Due to the sine function s quarter-wave symmetry, only (m 1)/2 angles need to be stored. Harmonics Unlike the PWM inverter, multilevel inverters do not push their harmonics to higher frequencies. While the THD is lower, the harmonics are located at relatively low frequencies, requiring a larger filter to eliminate completely. Achieving acceptable THD without a filter is possible (table 2.1) but requries many output levels. As seen in Fig. 2.6, a 5-level inverter at 60 Hz output has harmonics starting at 420 Hz. Levels Achievable THD % % % 9 8.9% % % % % % % Table 2.1: THD for multilevel inverters using ideal switching angles[1].

22 8 2 Theory of Operation Purely multilevel strategies are thus not a great choice for low-frequency applications. At higher fundamental frequencies, each eliminated harmonic gives greater relaxation on the requirements of the output filter cutoff frequency. 100 Fundamental (60Hz) = 434.2, THD= 17.75% Mag (% of Fundamental) Frequency (Hz) Figure 2.6: Harmonic content of a 5-level inverter Multilevel PWM By utilizing PWM control in a multilevel inverter, some of the benefits from both methods can be gained: smaller voltage jumps, high-frequency harmonics, and control by changing m a. The output of such an inverter is shown in Fig Figure 2.7: Voltage output of a 5-level PWM inverter. Control Signal Generation Unfortunately, harmonic elimination in multilevel PWM is a difficult task. The optimal switching angles depend on m a, and as with SHEPWM, solving for them in real-time is not feasible on a microcontroller. However, SPWM is easily adapted for more voltage levels by using multiple triangle waves as shown in Fig While the sine is greater than the upper triangle wave, output is at positive maximum; in between it is neutral; and below the lower triangle wave it is at negative maximum. The switching frequency for each semiconductor will average f s /(m 1).

23 2.1 Switching Strategies 9 Figure 2.8: Control signal generation for a 3-level PWM inverter. The modulation ratio is determined in the same way as for bipolar PWM inverters. Harmonics Despite the multiple voltage levels, no harmonic elimination occurs with basic SPWM control; only the amplitude of the harmonics is affected. The THD lies somewhere between the multilevel and bipolar PWM, with the harmonics located around the switching frequency. The reduced harmonics are illustrated in Fig Mag (% of fundamental) Frequency (khz) Figure 2.9: Harmonics of a 5-level PWM inverter. m a = and f s = Hz. THD 40%.

24 10 2 Theory of Operation 2.2 Topologies Many inverter topologies exist and can be used to get the voltage levels needed by any given switching strategy. Several classes of these (from [1]) are discussed below, with some advantages and disadvantages listed for each H-bridge The most basic inverter is the H-bridge (Fig. 2.10), also called full-bridge. It consists of 4 switches with antiparallel diodes. It is capable of negating the input voltage or blocking it entirely, giving it three output levels: V DC, V DC, and 0. DC+ + AC - DC- Figure 2.10: An H-bridge inverter. By connecting several H-bridges in series (Fig. 2.11), more output levels can be achieved; however, this requires a separate DC source for each cell.

25 2.2 Topologies 11 Vo1 Vdc + H-bridge Vdc + H-bridge Vdc + H-bridge Vo2 Figure 2.11: A seven-level multicell inverter made of several H-bridges. This type of structure also gives a long conduction path of 2(m 1) switches, which reduces the device efficiency Diode-clamped The diode-clamped (also called neutral-point clamped, or NPC) class of inverters, as the name implies, uses DC-link capacitors and diodes to clamp the voltage level at parts of the circuit to desired levels. In this way, each phase leg of the inverter can output between V DC /2 and V DC /2 relative to the designated neutral node.

26 12 2 Theory of Operation DC+ S1 S2 + AC - S3 S4 Figure 2.12: A three-level diode-clamped inverter with a single phase leg. The switches in Fig make up two complementary pairs: (S 1, S 3 ) and (S 2, S 4 ), so the inverter has four possible states. The state where the outer switches S 1 and S 4 are open is unused, since it would give a floating output. Five-level inverters (Fig. 2.13) and higher have similar pairs. Disallowing the states that give a floating output or a DC-to-ground short always leaves m switch states; thus, NPC inverters have only one viable switch combination for each output level. DC+ AC + - DC- DC- Figure 2.13: A five-level diode-clamped inverter with a single phase leg.

27 2.2 Topologies 13 For an m-level inverter, the switches are required to block a voltage of V DC /(m 1). Current flows through up to m 1 switches and one diode, increasing the potential conduction losses when more levels are used. The clamping diodes are also subject to a great deal of stress. They are required to block up to V DC, unless several smaller series diodes are used. While the average diode current is less than the inverter output current, the peaks are many times greater C1 voltage (V) C2 voltage (V) Time (s) Time (s) C3 voltage (V) C4 voltage (V) Time (s) Time (s) Figure 2.14: Voltage over the DC-link capacitors in a five-level NPC inverter. When m > 3, the DC-link capacitors will suffer a charge imbalance (Fig. 2.14). More current is drawn from the inner capacitors, and the output waveform will eventually decay into three levels, as the charge is located entirely on the top and bottom capacitors. Therefore, this architecture is rarely used without some corrective measures [5]. Balancing methods based on switching patterns only work for low modulation indices [6], so balancing methods often involve additional circuitry [7] or else only work under certain circumstances [8], making NPC inverters generally less attractive from a practical standpoint Capacitor-clamped Using capacitors to clamp the voltage to desired levels gives a topology similar to the diode-clamped one. Switches are still required to block V DC /(m 1), but there is no need for high-performance clamping diodes. Instead, it uses m 2 capacitors. This means there are no large peak currents in the device. Three- and five-level architectures are shown in Fig and Fig

28 14 2 Theory of Operation DC+ + AC - Figure 2.15: A three-level capacitor-clamped inverter with a single phase leg. DC+ + AC - DC- DC- Figure 2.16: A five-level capacitor-clamped inverter with a single phase leg.

29 2.2 Topologies 15 As with the diode-clamped topology, capacitor charge imbalance is a problem. However, it occurs in the clamping capacitors rather than the DC-link ones. Fortunately, each voltage level can be synthesized with several switching vectors; careful selection of these can eliminate the charge imbalance Switched-capacitor The switched-capacitor (SC) inverter and its cousin the switched-inductor (SL) inverter offer some advantages over the traditional clamping varieties. They require only a small number of components for each added output level, and offer significant voltage boost capabilities. Fig shows an SC inverter. Note that if m 3, there would be no capacitors and only an H-bridge would remain.the capacitors are charged in parallel while the main switch S m is closed, and discharged in series when it is open and the secondary switches are closed. As a result, the output voltage peak is up to (m 1)/2 times the input voltage, with a step size of V DC. This is a downside in cases where the AC voltage should have a lower peak than V DC ; additional circuitry would be needed to bring down the voltage to the desired level. DC+ S1 S2 S3 + AC Sm DC- - Figure 2.17: A 9-level switched-capacitor inverter. The SC inverter also suffers from a charge imbalance issue; the larger the load, the smaller the average charge is on the capacitor, as it is reduced by the output current. At high loads, the capacitors are fully drained each period, giving a three-level output no matter how many levels the inverter is built for Switched-inductor The switched-inductor (SL) inverter uses an inductor to charge series capacitors, as shown in Fig The duty ratio of the inductor switch can be changed to control the capacitor charge, and thus the output voltage. While the inductor is charging, there is effectively a short across the DC input. Unless the inductor is very large or the duty ratio of the switch very low, this

30 16 2 Theory of Operation leads to extremely large currents through the main switch; extensive paralleling of devices is needed to make this design functional, and the power losses through the main switch will be considerable. DC+ + AC DC- - Figure 2.18: A 9-level switched-inductor inverter. Unfortunately, the charge imbalance issue seen in the SC inverter is also present here, for the same reasons Comparison The number of power electronic components needed for each topology is shown in table 2.2. Topology Switches Diodes Capacitors Switch blocking voltage V Diode-clamped 2(m 1) 4m 5 m 1 DC m 1 V Capacitor-clamped 2(m 1) 2(m 1) m DC m 1 m 3 Switched-capacitor 4 + m m 4 2 V DC Switched-inductor 5 + m 1 m V DC Table 2.2: Comparison between different inverter topology families.

31 3 Practical Considerations 3.1 Filter Selection Since the output is going to be strongly distorted, a low-pass filter is required to eliminate the unwanted harmonics. These harmonics are a considerable proportion (> 30%) of the overall signal energy, so a purely reactive filter is used to minimize losses. Figure 3.1: A T-section low-pass filter made from two inductors and a capacitor. Since this is a resonant circuit, care must be taken to ensure that no harmonics are close to the resonant frequency. In practice, this is easily accomplished for PWM inverters by making the cutoff frequency f c sufficiently low compared to the switching frequency. 17

32 18 3 Practical Considerations THD (%) ,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 10,000 11,000 12,000 13,000 14,000 15,000 16,000 17,000 18,000 Switching frequency (Hz) Figure 3.2: THD of a five-level PWM inverter at different switching frequencies when using a low-pass LC filter with a cutoff frequency of 2.25 khz. Fig. 3.2 shows a rapid decrease in distortion around f s = 2f c, and Fig. 3.3 shows similar results THD (%) Cutoff Frequency (Hz) Figure 3.3: THD of a five-level PWM inverter at different cutoff frequencies with a switching frequency of Hz. All third-order filters of this type have a slope of 18 db per octave, so a cutoff frequency F c F s /4 will put the inverter well below the 5% THD mark while keeping the filter s resonant frequency away from any of the frequencies present on the output.

33 3.2 Conduction Losses Conduction Losses The first major source of power loss is the on-state conduction losses of the MOS- FET switches. Switching strategy has no effect on these losses, since the total current through the inverter is I L for both multilevel and PWM switching. For both NPC and flying-capacitor inverters, the current passes through a maximum of m 1 switches at a time. The total conduction loss can therefore be estimated as P on I 2 L R on(m 1). (3.1) For switched-capacitor inverters, current goes through at most 3 + (m 3)/2 switches, giving P on I 2 L R on ( 3 + m 3 2 ). (3.2) Switched-inductor inverters have 3 series switches regardless of the number of levels; however, a very large current will pass through the main switch while the inductor is being charged, resulting in very high power losses. This needs to be mitigated somehow for the design to be practically workable.

34 20 3 Practical Considerations 3.3 Switching Losses One of the primary sources of parasitic power consumption in PWM inverters is switching losses. While these losses occur in pure multilevel inverters as well, the switching frequency there is relatively low: f s = (m + 1)f o. At the relevant voltage levels (hundreds of volts), switching losses therefore become negligible next to on-state conduction losses. For PWM inverters, the switching losses become a major design consideration. A tradeoff must be made between switching losses, filter size, and output quality. Switching loss has two major sources: gate charge and conduction during the switching period Gate charge The gate charge energy is simply the energy stored on the switch s input capacitance, C iss. For power MOSFETs, this value is usually around 1-5 nf 1, although it may vary depending on the blocking voltage of the device. Energy stored on this capacitance will be E iss = C issvdc 2. (3.3) 2 This portion of the switching energy is load-independent, and must be taken into account even if the device is idle (i.e not conducting) Switch-conduction The precise switching behaviour of a MOSFET is highly dependent on the operating conditions as well as the specific device used. However, an approximation can be found by using a linear model. Assuming V gs = V th gives V ds = V d (V g V th ). (3.4) Assuming the drain current I d rises linearly with gate voltage and reaches its maximum when V ds = 0 gives I d = I L V g V th V d, (3.5) where I L is the load current, V g is the gate-to-neutral voltage, V d is the (fixed) drain voltage and V th is the threshold voltage. This model is only valid in the triode region (0 < V g < V d + V th ), but it is a decent approximation within that interval (see Fig. 3.4). Since the device will always be in the triode region during switching, this limitation is not a problem. 1 Based on data sheets.

35 3.3 Switching Losses 21 Id Time (us) Vgs Time (us) Figure 3.4: Comparison of the linear model (solid) with results from a SPICE simulation (dashed). With this model, power dissipation in the transistor is given by P sw = I d V ds = I L V g V th (V g V th ) 2. (3.6) Fig. 3.5 shows how the instantaneous power consumption rises during the switching period. V d Vg Id Time (us) Time (us) Vds Power (W) Time (us) Time (us) Figure 3.5: Illustration of switch-conduction loss.

36 22 3 Practical Considerations Approximating the gate voltage as rising linearly, the total turn-on energy is E sw = C iss(v DC + V th ) I L t 2 t 1 V DC t (V V t 2 t th DC t) 2 dt. (3.7) 1 V DC (t 2 t 1 ) 2 Taking the input capacitance C iss and drive circuit resistance R drv into account, the total turn-on energy is E sw = C issv 2 DC 2 + I L t 2 t 1 V DC (1 e t R drv C iss ) Vth (V DC(1 e t V DC R drv C iss ) Vth ) 2 dt. (3.8) where t 1 and t 2 are the times when the gate voltage reaches 10% and 90% of its final value, respectively. By symmetry, the turn-off losses are equal. The total switching power (for a single switch) becomes 2E sw f s. In a real application, the current being switched is nowhere near constant, due to stray inductances, non-unity power factor of the load, etc. This model is therefore only an order-of-magnitude estimation of the switching losses.

37 4 Implemented Architecture 4.1 Schematic The chosen architecture is a 5-level PWM inverter with a 60 Hz output. It achieves low dv /dt and THD with a small number of components and a switching frequency of up to a few khz. A complete list of the specific components used for the physical implementation can be found in appendix A. Figure 4.1: Inverter block connections. The gate driver, filter, controller and main inverter blocks are connected as 23

38 24 4 Implemented Architecture shown in Fig Inverter The inverter uses two three-level diode-clamped phase legs (Fig. 4.2). In this configuration, five output levels can be achieved without concern for charge balancing on the DC-link capacitors. Figure 4.2: The proposed architecture, main part. As discussed in section 2.2, each phase leg outputs ±V DC /2 or 0 V. If they are controlled with SPWM using complementary sine waves (Fig. 4.3), the output waveform is near-identical to that in Fig. 2.7, with a peak voltage of V DC.

39 4.1 Schematic 25 1 Carrier and reference signals Vc, Vm Time (ms) Phase leg 1 Phase leg Vo1 0.5 Vo Time (ms) 1 Output Time (ms) Vo1 Vo Time (ms) Figure 4.3: PWM generation for a two-legged inverter. Using complementary legs in this way effectively doubles the switching frequency; f s = 2f t where f t is the triangle wave frequency Gate Drivers All switches used are N-channel MOSFETs; in order to turn them on, the gatesource voltage V gs must exceed the threshold voltage V th, typically around 2 V. This poses a problem, since the upper source nodes will be at V DC when the switches are on, which is the highest voltage available in the system.

40 26 4 Implemented Architecture Vb3 Vs3 Vb2 Vs2 Vb Vs Cb3 Cb2 Cb1 Vdd + Vdc S4 S3 S2 S1 Figure 4.4: Connection of bootstrap capacitors. To reach the higher voltages needed, a series of bootstrap capacitors are used (Fig. 4.4). When the bottom switch S 4 is on, C b3 is charged through the diode to V dd ; when S 4 is off and S 3 is on, C b2 is charged from C b3. C b1 is charged from C b2 in the same way. The bootstrap capacitors must be sized so that they are large enough to charge both the gate it drives and the bootstrap capacitors higher up in the chain [9]. In the case of a three-level diode-clamped circuit, the two upper switches will need to be charged f s /2f o times during the half-period where the bottom bootstrap capacitor is not charged from V dd. It needs to hold enough charge to do this without its voltage falling below V th. With a MOSFET gate charge Q g 70 nc, a drive supply voltage V dd = 10 V, and f s = 6060 Hz, this gives C b1 0.7 µf. Since there is no functional downside to oversizing these capacitors, nor any appreciable difference in cost or size, the sizes C b1 = 10 µf, C b2 = 22 µf and C b3 = 47 µf are chosen, allowing the device to operate over a wide range of switching frequencies. More energy is needed to charge these large capacitors the first time, but the voltage drop during each discharge cycle will be smaller as well; the difference in bootstrap charging power is negligible Control The PWM signals can be generated with a combination of comparators, tri-wave generators and sine generators. However, this approach would require hardware changes to test different output frequencies and control schemes. Due to this inflexibility, a microprocessor is used instead. For the sake of simplicity, the microprocessor runs off a separate DC source rather than a stepped-down main input (as would be the case in an inverter with

41 4.1 Schematic 27 only one input). This should not notably affect the efficiency rating, as the microprocessor only consumes a few milliwatts. The amplitude modulation is controlled either manually by an external control mechanism, or automatically using the microcontroller s built-in analog-todigital converter. Fig. 4.5 shows how a voltage divider at the input can be used to sense V in ; since there is a linear relationship between m a, V in and V out, this allows voltage regulation with a simple P-control algorithm. Rin + 225V DC+ Rdiv1 +5V Vdd A/D Inverter Vss Out 8 Rdiv2 DC- Figure 4.5: Microprocessor connections. Fig. 4.5 shows the connections to the microprocessor, using the voltage divider setup. The switching frequency can be chosen almost arbitrarily by tweaking the control program, as long as it is significantly smaller than the operating frequency of the microprocessor. If f s is set too high, the waveform cannot be synthesized properly Filter As per section 3.1, a reactive filter is placed at the output. Choosing component sizes 0.56 mh and 22 µf gives a filter with the frequency response shown in Fig. 4.6.

42 28 4 Implemented Architecture Figure 4.6: Frequency response of a T-section LC lowpass filter with C = 23 µf and L = 0.56 mh at low load. f c 2 khz. Using f s = Hz, the first set of harmonics (near f s ) should be dampened by around 50 db. The third harmonic (180 Hz) is not completely eliminated due to input ripple and imprecise switching, and will be slightly amplified by the filter. This amplification is less than 1 db however, and should not affect device performance to a noticable degree.

43 4.2 Expected Results Expected Results To verify the accuracy of the models from section 3.2 and section 3.3, the behaviour of the proposed architecture is predicted before it is simulated and implemented Ripple With a sinusoidal output, the instantaneous power draw of the inverter will not be constant. More power is drawn during the peaks, as illustrated in Fig Since V DC is constant, I in must increase when P in does, and vice versa. 200 Vo Time (ms) 5 IL Time (ms) 400 Pin Time (ms) Figure 4.7: Instantaneous power draw of inverter, assuming unity power factor and 100% efficiency. This waveform has a fundamental frequency of 2f o = 120 Hz. Since greater power draw means a higher input current, this ripple appears on both I in and V in (due to voltage drop over R in ). We define the input current ripple factor as and the input voltage ripple factor as r i = I in,max I in,min I in,average (4.1) r v = V in,max V in,min V in,average. (4.2)

44 30 4 Implemented Architecture The input current minimum is always 0 A, and since it is sinusoidal the maximum is twice the average value. Thus, r i = 200%. V in will never exceed V DC, and the minimum depends on the load and the input resistance. With V DC = 225 V and P load = 500 W, the average input current will be 2.5 A. The input voltage minimum becomes V in,min = V DC 2R in I in,average = 225 V 50 V = 175 V (4.3) which gives r v = 25%. However, the input resistance R in and the DC-link capacitors form a low-pass RC filter. With R in = 10 Ω and C DC = 250 µf, the 120 Hz oscillations are dampened by about 50%. Higher frequency components of the ripple are almost completely filtered out, and do not contribute meaningfully to the ripple factor. We can expect a current ripple r i 100 % and voltage ripple r v 12.5 % THD With the filter from section 4.1.4, the harmonics caused by the high-frequency switching are almost completely eliminated. Thus, the only remaining harmonics are those caused by non-ideal devices and input ripple. These distortions are difficult to model analytically since they depend on the interaction between the controller, the switches, and the rest of the circuit, but some estimations can be made. First, the distortions caused by inexact switching (due to propagation delay, rise/fall times, etc.) are unlikely to have a significant impact, as they will be of very high frequencies ( f s ) and thus filtered out. The input voltage ripple is a 120 Hz sinusoid. Since the output voltage is directly proportional to the input, taking the input ripple into account gives us an output of: r V o,ripple = V v sin (120 2π) + 1 o. (4.4) 2 This adds an unwanted third harmonic (as well as some irrelevant high-frequency ones). The value of this harmonic relative to the fundamental will be S 3 = S 1 r v /2 1 + r v /2. (4.5) Assuming 10% voltage ripple, the THD of V o will be approximately 4.7% Efficiency Using the approximations from section 3.2 and section 3.3, the efficiency of the inverter can be estimated. The switches used for the 225 V-450 V inverter have an on-state resistance R on 0.5 Ω, input capacitance C iss 1.6 nf and a threshold voltage V th 3.9 V. Each device blocks V DC /2 and has an effective switching frequency of f s /4 = 12120/4 Hz = 3030 Hz.

45 4.2 Expected Results 31 The outer switches conduct I L while switching; the inner switches conduct I L during the half-period where they are held in the on-state. While switching, the drain current is small and the switch-conduction losses can be neglected. Plugging these numbers into eq. (3.1) and eq. (3.8) gives the efficiency estimates in table 4.1. V DC P load Estimated efficiency 450 V 2000 W 93.3% 450 V 1000 W 96.3% 450 V 500 W 97.8% 225 V 500 W 93.3% 225 V 250 W 96.4% Table 4.1: Efficiency estimates. At the frequency used, switching losses account for 3-8% of the total losses. Efficiency appears to improve as the load decreases, but this effect is likely limited. The gate charge portion of switching losses does not scale with the load, and puts minimum energy requirement on the inverter even when driving no load.

46 32 4 Implemented Architecture 4.3 Simulation Results The proposed architecture was tested in National Instruments MultiSim with a few different loads. The results are shown in table 4.2. The output was 240 V and 120 V for inputs of 450 V and 225 V, respectively. Load Power Factor V DC THD Efficiency Ripple (I) Ripple (V) < 1 W V 3.92% 0.38% 1584% 2.43% 500 W V 3.05% 93.13% 128% 3.60 % 1000 W V 2.83% 94.46% 104% 6.01% 2000 W V 4.04% 93.01% 96% 12.59% 2000 VA V 3.94% 92.87% 114% 9.90% < 1 W V 3.44% 0.23% 932% 2.41% 250 W V 2.71% 93.17% 103% 6.04% 500 W V 3.86% 92.41% 95% 12.56% Table 4.2: Simulation results. Table 4.2 shows the inverter performance under various operating conditions. When checked against the requirements in appendix B, THD is acceptable while efficiency falls just short of the desired 95%. Losses may be reduced i.e. by parallelling switches, so the ripple factor is the most severe point of failure. Simply increasing the size of the DC-link capacitors would work, though the physical size of the inverter would increase dramatically. At low loads, the switching losses are dominant; since they do not scale with the load current, this results in very low efficiency. At < 1 W this is not a cause for concern, however. The extremely large input current ripple factor at low loads is not unexpected, given that the absolute value of the current is so small Magnitude (% of fundamental) Harmonic Figure 4.8: Harmonic spectrum of simulation output at 225 V, 500 W, zoomed to make the smaller harmonics visible. At all other loads, the THD and ripple are very close to the estimations from

47 4.3 Simulation Results 33 section 4.2; the models used appear to be accurate. Fig. 4.8 shows that the third harmonic (caused by input ripple) is the largest, as expected. The efficiency estimates, on the other hand, were less reliable. While seemingly accurate at maximum load (predicting 93.3% in both cases), accuracy drops off as the load is reduced. This is likely because the filter is connected, causing the inverter to "see" its power factor rather than that of the load. Hence, the currents being switched are not as predictable as assumed, and the estimates are off.

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49 5 Results 5.1 Physical Implementation The final implementation (minus the output filter) fits on a 10x16 cm prototype board (Fig. 5.1). The filter (f c 2 khz), consisting of two 0.56 mh inductor coils and one 22 µf film capacitor, takes up slightly less than half of an identical board. Figure 5.1: Physical implementation of a power inverter. Roughly half the board is occupied by the control and drive ICs. The DC-link 35

50 36 5 Results capacitors take up a hefty portion of the rest; to improve matching between the top and bottom DC-link capacitance, five parallel capacitors are used instead of a single large one. Since the microcontroller and gate drivers run on different voltages (5 V and 10 V, respectively), level shifters are used between the microprocessor output and the gate driver logic input Control The control signals are generated from an 8-bit 8 MHz Atmel CPU. The reference sine wave is taken from a lookup table with 1024 samples; the triangle wave has 16 samples per period. This gives f t = 64f o f s = 128f o. For this prototype, f o = 61.8 Hz, so f s = 7910 Hz. The automatic voltage regulation was not implemented, and m a is fixed at 1.0. This is because the internal resistance of the lab voltage source is too small to cause any noticeable voltage drop before the inverter input. For the same reason, there was no observable ripple on V in.

51 5.2 Output Behaviour Output Behaviour Due to equipment availability and safety reasons, the physical implementation was not tested under (or built for) the full-load conditions of 225 V DC input and 120 V RMS output. It was instead tested under low-power conditions: V DC = 20 V DC and V o = 14.1 V RMS AC. The unfiltered output and its spectrum are shown in Fig. 5.2 and Fig % THD, V RMS Vo Time (ms) Figure 5.2: Unfiltered voltage output, no load Magnitude (V) Frequency (khz) Figure 5.3: Unfiltered voltage frequency spectrum, no load. The five-level waveform is correctly synthesized, though the PWM is difficult to see in the figure due to the overshoot that occurs when switching. THD is slightly larger than it would be with ideal switching (Fig. 6.1), but this is not especially surprising. Connecting the filter, but not a load resistor, gives the output shown in Fig. 5.4 and Fig. 5.5.

52 38 5 Results % THD, V RMS Vo Time (ms) Figure 5.4: Filtered voltage output, no load. The dashed line shows the fundamental frequency component Magnitude (V) Frequency (khz) Figure 5.5: Filtered voltage frequency spectrum, no load. While THD is a bit greater than preferred, it is still low enough for most nonsensitive applications. Most distortions are located below 2 khz, since that is the cutoff frequency of the output filter. The "switching spikes" are still present, but are much smaller. Fig. 5.6 shows the filtered output voltage when a 30 Ω resistor is connected at the output. Since there is now an actual current through the switches, THD is increased and there is some power lost. The location of the distortions is unchanged.

53 5.2 Output Behaviour % THD, V RMS Vo Time (ms) Figure 5.6: Filtered voltage output, 30 Ω load. The dashed line shows the fundamental frequency component. The input current was just below 0.3 A, so P in 6 W. V o = V RMS, so we have P out = V 94.5%. (5.1) P in 30 Ω 6 W A small amount of power also goes to the microprocessor, level shifter, and microprocessor circuits, which were connected to separate DC sources. This is only a few milliwatts, however, and does not scale with the load. Hence, this term can be safely disregarded in the efficiency calculations.

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55 6 Conclusions 6.1 Discussion Of the examinded topologies, the NPC and flying capacitor inverters were found to have the best tradeoff between performance, cost and size; while the SC and SL topologies could be implemented with fewer total components, the charge imbalance issue renders them impractical. For the implemented prototype, the low voltage rating of the power MOSFETs is the largest limitation of the device as-is. Exchanging those should allow it to work at DC-link voltages of at least 225 V, as simulated. Estimation Simulation Measurement THD 4.7% 3.85% 7.04% Efficiency 93.3% 92.41% 94.5% Table 6.1: Comparison between estimation, simulation and measurement. Table 6.1 summarizes the differences between estimates, simulation results, and measurements on the prototype. Efficiency matches the simulations well, though it is likely to be reduced at higher power levels as the components get hotter and have higher resistance. Due to the discretization of the control signals, the inverter output is slightly more distorted than expected. The third harmonic caused by input ripple is missing entirely; the low-frequency distortions that remain are caused by non-ideal components and parasitic inductances in the circuit. Fig. 6.1 shows that while the quantization of the control signals only adds about 2% extra THD, these extra distortions are spread evenly throughout the spectrum and will not be completely filtered out. 41

56 42 6 Conclusions Mag (% of fundamental) Mag (% of fundamental) Quantized: 29.01% THD Frequency (khz) Ideal: 26.96% THD Frequency (khz) Figure 6.1: Frequency spectrum of SPWM with quantized and ideal reference signals. Because of the lack of ripple and the quantization distortions, the THD estimates from section are not accurate for this device. Some improvement could be made by tweaking the filter, since the majority of the remaining distortions are below the cutoff frequency. Implementing the automatic voltage control algorithm would likely require a different microprocessor, since the one used has barely enough time to generate the control signals during each period. Adding a few more multiplications to the loop would require further quantization of the control signals, which would further reduce the output quality.

57 6.2 Future Work Future Work While several modulation methods have been discussed in this thesis, only one was implemented. With a better microcontroller, the prototype that was built could be used to compare several different switching methods on a physical circuit, e.g. the 5-level SHEPWM introduced in [10] or the space-vector modulation method from [11]. Another natural progression would be to complete the prototype to work under the Little Box conditions and seeing how this affects performance. A more thorough evaluation of the topologies that were not used for this thesis is also in order; in particular, a switched-capacitor inverter could feasibly be constructed with enough output levels to eliminate the need for an output filter. The impact of the necessary voltage balancing circuits would need to be evaluated. Lastly, resonant-switch converters made for resistive loads as in [12] can offer significant efficiency improvements if adapted to multilevel inverters.