Southern Africa Large Telescope. Prime Focus Imaging Spectrograph. SAAO Detector Subsystem. SALT-3190AE0001: SAAO Document List

Transcription

1 SALT-3190AE0001 SAAO Document List 1 Southern Africa Large Telescope Prime Focus Imaging Spectrograph SAAO Detector Subsystem SALT-3190AE0001: SAAO Document List SAAO PFIS Detector Subsystem Team: Darragh O Donoghue Luis Balona Etienne Bauermeister Dave Carter Geoff Evans Willie Koorts James O Connor Faranah Osman Stan van der Merwe Issue March 2003

2 SALT-3190AE0001 SAAO Document List 2 Issue History Number And File Name Person Issue Date Change History SALT-3190AE0001 SAAO DOD Nov 2002 First draft Document List Issue 1.0.doc SALT-3190AE0001 SAAO Feb 2003 Major update Document List Issue 1.1.doc SALT-3190AE0001 SAAO Document List Issue 1.2.doc Feb 2003 Final CDR draft SALT-3190AE0001 SAAO Document List Issue 1.3.doc SALT-3190AE0001 SAAO Document List Issue 1.4.doc SALT-3190AE0001 SAAO Document List Issue 1.5.doc Feb 2003 Truly the final CDR draft Mar 2003 Finally and truly the CDR draft! Mar 2003 No! Update again because of Detector doc update 1 Document List This is the SAAO PFIS Detector Package Document List: In general, documents with file names beginning SALT-31 are CDR documents and those beginning with lower case letters are PDR documents. File Name Contents Person Responsible SALT-3190AE0001 SAAO Document List Issue 1.2.doc Detector package document list DOD saao.sow.doc SALT-3190BP0001 SAAO SOW Issue 1.5.doc saao.fprd.doc saao.ocdd.doc Detector package statement of work at PFIS PDR Detector package statement of work at PFIS CDR Detector package Functional Performance Requirements summary Document for PFIS PDR. Integrated with PFIS FPRD. Detector package Operational Concepts Definition Document for PFIS PDR. Integrated with PFIS OCDD. DOD DOD DOD

3 SALT-3190AE0001 SAAO Document List 3 SALT-3190AE0002 Schedule Issue 1.0.mpp Detector package schedule at PFIS CDR GPE PFIS_pdrbudget.xls SALT-3190AE0003 SAAO Budget Issue 2.1.xls SALT-3190AE0004 Testing Issue 1.4.doc SALT-3190AS0001 Detector Safety Issue 1.1.doc saao.icd.doc SALT-3190AS0002 SAAO ICD Issue 1.13.doc saao.design-study.doc SALT-3196AE0001 Detector Issue 2.6.doc SALT-3196AE0002 CCD Handling Procedures Issue 1.1.doc SALT-3197AE0001 Cryostat Issue 2.5.doc SALT-3199AS0001 Software Issue 1.1.doc Detector package budget at PFIS PDR Detector package budget at PFIS CDR Detector package testing and commissioning plan Safety report at PFIS CDR Detector package interface control dossier at PFIS PDR Detector package interface control dossier at PFIS CDR Detector package CCD and controller performance document at PFIS PDR Detector package CCD and controller performance document at PFIS CDR SAAO CCD handling procedures Detector package cryostat design document at PFIS CDR Detector package software documentation at PFIS CDR DOD WPK GPE WPK DBC/DOD DBC JOC DOD/DBC

4 SALT-3190AE0004 Testing Document 1 Southern Africa Large Telescope Prime Focus Imaging Spectrograph SAAO Detector Subsystem: SALT-3190AE0004: Testing Document SAAO PFIS Detector Subsystem Team: Willie Koorts Luis Balona Etienne Bauermeister Dave Carter Geoff Evans James O Connor Darragh O Donoghue Faranah Osman Stan van der Merwe Issue March 2003

5 SALT-3190AE0004 Testing Document 2 Issue History Number And File Name Person Issue Date Change History SALT-3190AE Nov PFIS CDR draft Testing Issue 1.0.doc 2002 SALT-3190AE0004 Testing Issue 1.3.doc Feb 2003 PFIS CDR draft SALT-3190AE0004 Testing Issue 1.4.doc Mar 2003 Truly the last PFIS CDR draft Table of Contents 1 Scope Testing Levels Detectors Cryostat Readout Noise & Gain and Full Well Readout Speed Pre-Binning Safety Envelope Mass Instrument Temperature Control Component/Module Replacement Electromagnetic Radiation SDSU II CCD Controller, Subsystem Controller and Power Supply, and CryoTiger Compressor Communications with SALT Computers Communication with the Precision Time Source Communication with CCD and Subsystem Controller PFIS Detector Subsystem Man-Machine Interface (MMI) PFIS Detector Subsystem Algorithms CCD Controller and Subsystem Controller Functions Thermal Control Functions...10

6 SALT-3190AE0004 Testing Document Cryotiger Functions Commissioning Plan...11 Table 3. Commissioning plan...13

7 SALT-3190AE0004 Testing Document 4 1 Scope This document describes the testing and commissioning plan for the Detector Subsystem of the Prime Focus Imaging Spectrograph (PFIS) instrument for the Southern African Large Telescope (SALT). The Detector Subsystem will be developed at the South African Astronomical Observatory (SAAO), will then be shipped to University of Wisconsin (UW), mounted on PFIS for integration and testing, shipped back to South Africa and remounted on PFIS, before being finally mounted on SALT. Different levels of testing will be required at various times in between these stages as will be described in more detail in this document. 1.1 Testing Levels Three levels of testing is envisaged: Basic Functional Test (BFT) Extended Functional Test (EFT) Full Performance Test (FPT) These are detailed as follows: Basic Functional Test (BFT) Temperature test Dark frame test Response to (unfocussed) light test Extended Functional Test (EFT) BFT Noise/Gain test Image test Full Performance Test (FPT) EFT Dark current test Well depth test Charge Transfer Efficiency (CTE) test Quantum Efficiency (QE) test Flat Fielding test Other miscellaneous tests described below The required levels of testing to be performed at the various stages of the instrument are shown in Table 1.

8 SALT-3190AE0004 Testing Document 5 Location / Stage After development at SAAO Detector arrives at UW Detector mounted on PFIS Detector shipped back to South Africa Detector mounted on PFIS on SALT Testing level required FPT BFT EFT BFT EFT Table1: Testing at various stages 2 Detectors CCD chips: Marconi Applied Technologies x 4096 x 15 micron square pixels 30.7 x 61.4 mm imaging area, Frame Transfer mode option 2 readout amplifiers per chip 3 x 1 mini-mosiac CTE: per cent (typical), per cent (guaranteed) Full well: 200 k e - /pix (typical), 150 k e-/pix (guaranteed) Sensitivity: Thinned, back-illuminated. Deep depletion silicon Astro Broad Band anti-reflection coating Dark current: 1e - /pix/hr (typical) at 163 K Readout noise: 3.0 e - /pix at 100 khz (10.0 µsec/pix) 5.0 e - /pix at 345 khz (2.9 µsec/pix) Quantum Efficiency (QE) Wavelenth Spectral Response (QE) (nm) Min Typical Table 2: Quantum Efficiency

9 SALT-3190AE0004 Testing Document 6 CCD Controller: SDSU II (Leach) from Astronomical Research Camera Inc. Gain: Software selectable from: x1; x2; x4.75; x9.5. Prebinning: 1x1 to 9x9, independently in each direction Readout speed: Frame transfer architecture: sec frame transfer time khz ( µsec/pix) Windowing: Up to10 windows Quantum efficiency can be partially verified by inspecting the test data sheets that Marconi will supply with each chip. However, this property is so crucial to the performance of the camera that it is desirable to verify the quantum efficiency independently. To achieve this the cryostat will be mounted on an SAAO telescope (e.g. the 1-m) to obtain observations of standard stars through UBVRI filters. These data will then be compared to observations of the same stars with SAAO CCD cameras where the QE of the chip is known, or the stellar flux at the top of the atmosphere can be modelled with a suitable extinction law, reflectivity for the telescope mirrors, absorption by the filters and cryostat window and attenuation by the filter bandpass. The recorded number of photons/sec can then be compared with the number estimated to be arriving at the detector and the QE deduced. QE testing will either be demonstrated, or reported in writing. Testing of the co-planarity of the 3 x 1 mosaic as well as flatfielding can also be tested with the cryostat on an SAAO telescope. Co-planarity will be tested by carefully focusing a star on the one CCD and then moving it to the other CCD and compare the focus shift, if any. Flatfielding can be tested over small pixel scales since the full array will not be illuminated at the same time. The manufacture s values for CTE will be verified using the Extended Pixel Edge Response (EPER) method. All the above tests are FPT level tests. 2.1 Cryostat The PFIS Detector Subsystem requirement is for: An evacuated chamber for the detector Poisson noise on the dark current pedestal from the longest exposure should be small compared to readout noise of 5 electrons There should be a drip tray to catch condensation on the outside of the cryostat arising in the event of loss of vacuum The first two requirements will be tested by demonstrating that the detector reaches the planned operating temperature and that at this temperature, dark current is less than 1 e - /pix/hr by obtaining a dark exposure (with the detector sealed from light and in a darkened room). These are BFT tests. The third requirement will be tested by inspection. This is an EFT test.

10 SALT-3190AE0004 Testing Document Readout Noise & Gain and Full Well The PFIS Detector Subsystem requirement is for readout noise of less than 5 electrons at slowest readout speed and have a full well capability of 200k e - /pix (typical), 150k e - /pix (guaranteed). This will be tested in the lab by the standard photon transfer curve method using a set of exposures of ever increasing duration. (FPT) When mounted on PFIS the read noise can be obtained by analysing the variance of the bias frame of a zero second exposure readout, applying the noise figure obtained in the lab. (EFT) 2.3 Readout Speed The PFIS Detector Subsystem requirement is for a readout speed which will read out the detector in 5 sec or less. This requirement will be tested in the lab by simply timing readouts (FPT). Windowed readout and prebinning will be required to achieve this figure. 2.4 Pre-Binning The PFIS Detector Subsystem requirement is for software-selected pre-binning from 1x1 to 9x9. Testing will involve demonstrating that the user interface software and SDSU controller software provide this capability. (EFT) 2.5 Safety This is discussed in the Safety Report document SALT -3190AS0001 Detector Safety Issue 1.1.doc. All features of the design will be evaluated in terms of the requirements in the SALT Safety Standards (SALT Safety Analysis: SALT Document 1000AA0030). 2.6 Envelope The PFIS Detector Subsystem Specification limit of?? (TBD) shall be checked by measuring these dimensions. (EFT) 2.7 Mass The Detector Subsyetem can be weighed and verified to be less massive than the PFIS Detector Subsystem Specification limit. (EFT) 2.8 Instrument Temperature Control The PFIS Detector Subsystem Specification calls for stringent controls on heat dumping on the payload, as well as control of surface temperatures of all electronics and electrical components. The SALT Project are to provide thermal control enclosures into which all electronics will be inserted.

11 SALT-3190AE0004 Testing Document 8 Testing this is a joint SAAO and SALT Project responsibility. By measuring the internal temperature of the thermal control enclosures, it can be established weather the manufacturer s specification is being exceeded. The exterior surfaces of all components, cables, pipes, etc can be measured using a handheld temperature probe and by infrared imaging. (EFT) 2.9 Component/Module Replacement The PFIS Detector Subsystem requirement is for suitable mechanical interfaces to be provided so that handling by the dome crane is possible, and all individual modules to weigh less than 15 kg (so they can be manhandled easily). This will be tested by inspection of the finished framework and weighing of the components prior to assembly. (FPT) 2.10 Electromagnetic Radiation The PFIS Detector Subsystem requirement is for the PFIS Detector Subsystem design to incorporate measures to shield its sensitive electronics from electrical noise. Since electromagnetic interference manifests itself by an increase in the CCD readout noise, often visible as a pattern in CCD frames, good noise performance in the lab will be a measure of the effectiveness of the electromagnetic shielding. Another test for the effectiveness of the electromagnetic shielding is to compare the noise performance in the harsh environment of the telescope to the noise levels obtained in the controlled environment of the lab. The 1-m telescope is notorious for being a noisy environment: the planned observations on the 1-m will allow testing of the shielding of the CCD readout electronics. (EFT) The noise performance on SALT will be compared with the noise levels obtained in the controlled environment of the lab. (EFT) 2.11 SDSU II CCD Controller, Subsystem Controller and Power Supply, and CryoTiger Compressor These modules provide power, control and cooling for the CCDs and control for all mechanisms. Their correct functioning will be implicit in all the (BFT) tests Communications with SALT Computers There is a requirement is for: Communications with the PFIS CON computer to receive camera setup information (exposure time, prebinning etc.), to receive instructions for interaction with the images on the PFIS Detector Subsystem display, and to transmit compressed versions of the images to these machines. Communications with the Telescope Control System (TCS) server to obtain telescope parameters (e.g. RA/Dec etc.).

12 SALT-3190AE0004 Testing Document 9 Communications with the Data Processor computer to allow that machine to obtain scientific data from the PFIS Detector Subsystem computer. These functions will be tested as part of the software testing when the PFIS Detector Subsystem computer is attached to the SALT network and the other machines are present and operating. (EFT) Communication with the Precision Time Source The PFIS Detector Subsystem requirement is for the PFIS Detector Subsystem computer to maintain precise time to 1 msec or better and to have scientific images time stamped to 1 msec. Testing the precision of the computer s timing to 1 sec is by inspection. Testing the computer s timekeeping to the one second level can be done by writing software to toggle a pin on the computer s printer port, exactly on each second changeover. Measuring this printer port output with the one second edge of the time service using a two channel oscilloscope gives a direct measure of the PC timing. Testing the accuracy of image timestamping to a precision of 1 msec can be done by using the CCD system (fitted with a simple camera lens) to capture an image of the display of a frequency counter. The frequency counter counts milliseconds, re-started from zero each second from the time service. The number captured thus acts as an exact millisecond timestamp of a frame for testing purposes to be compared to the computer time stamp of the same frame. (FPT) 2.14 Communication with CCD and Subsystem Controller The PFIS Detector Subsystem requirement is for control and status to be exchanged, as well as reading out CCD data at speeds of up to 64 Mbits/sec. This will be tested by demonstrating that the PFIS Detector Subsystem computer is controlling the camera and subsystems and reading out data at the required speeds. (FPT) 2.15 PFIS Detector Subsystem Man-Machine Interface (MMI) The PFIS Detector Subsystem requirement is for the PFIS CON or PFIS Detector Subsystem MMI to setup the camera, initiate the acquisition and readout of images, control the display and storage of the data and manage display interaction. The MMI must be exportable to the SA MMI computers. Testing will involve showing that all this functionality is present in the software and working. (EFT) 2.16 PFIS Detector Subsystem Algorithms The PFIS Detector Subsystem requirement is for algorithms for display interaction (extracting spectra, controlling image display, placing markers on the display, fitting Gaussians etc.). Testing will involve showing that all this functionality is present in the software and working. Test images will be used for FPT; real images at the telescope for EFT.

13 SALT-3190AE0004 Testing Document CCD Controller and Subsystem Controller Functions The requirement is for the CCD Controller and Subsystem Controller to control all aspects of the CCD (e.g. download control code, set/unset frame transfer mode, set prebin factor, set windows, readout the CCD) and Subsystems (control of the Ion Pump). Testing will involve demonstrating that all this functionality is present in the software and working. (FPT) 2.18 Thermal Control Functions The requirement is for the CCD detector temperature to be sensed and controlled and for the CCD controller internal temperature to be sensed. This will be tested by showing that the PFIS Detector Subsystem computer and CCD controller provide this functionality and that it is working (BFT) Cryotiger Functions The requirement is for the Cryotiger to cool the detectors. Testing will be as per the previous subsection.

14 SALT-3190AE0004 Testing Document 11 3 Commissioning Plan The required levels of testing to be performed at the various stages of the instrument are shown in Table 1 above. Table 3 below indicates which tests are to be performed at what stage. A indicates that the test is valid and a, that it is not valid for a specific instance. Refer to Section 2 for the detailed description of each test. TEST Detectors Frame transfer mode functioning QE demonstration/report CTE test ( % or better) Co-planarity test results Flatfielding test results Cryostat Detector reaches temperature Dark current < 1 e - /pix/hr Drip tray installed and functional BFT EFT FPT Readout Noise & Gain and Full Well depth Photo transfer curve noise/gain test (<5 e slowest) Full well depth test (150k e - /pix or better) Noise from bias of zero second exposure Readout Speed (@ 2 x 2 binning) Timed to be 5 sec or less Pre-binning 1x1 to 9x9 pre-binning is possible

15 SALT-3190AE0004 Testing Document 12 TEST BFT EFT FPT Envelope Measured dimensions within allowed values Mass Measured mass within allowed values Instrument Temperature Control Thermal enclosures internal temperature not exceeded External surfaces measurements within range Component/Module Replacement Suitable mechanical handling interfaces provided Individual modules not exceeding 15kg Electromagnetic Radiation Good noise performance in lab Absence of extra noise on 40-in Good noise and absence of pattern on SALT Communication with PFIS/SALT Computers PFIS/SA computers received camera setup info PFIS/SA computers image interaction instructions PFIS/SA computers transmit compressed images TCS server obtained telescope parameters Data reduction PC obtained data from PFIS Detector Subsystem

16 SALT-3190AE0004 Testing Document 13 TEST BFT EFT FPT Communication with Precision Time Source PFIS Detector Subsystem PC within 1 sec from time service PFIS Detector Subsystem PC within 1 msec from time service Communication with CCD & Subsystems Controller CCD Control and Status communication in order PFIS Detector Subsystem PC is controlling camera and subsystems PFIS Detector Subsystem MMI/PCON computer MMI can set up camera MMI can initiate acquisition and readout of images MMI can control data storage and display MMI can manage display interaction MMI is exportable to SA MMI computers PFIS Detector Subsystem Algorithms All algorithms can operate on test images All algorithms can operate on telescope images CCD and Subsystems Controller functions All CCD Controller functionality present and working All Subsystems controller Thermal Control Functions CCD detector temperature sensed and controlled CCD controller internal temp sensed and controlled Thermal enclosures internal temp sensed & controlled Cryotiger Functions Cryotiger cold end reaches required temperature Table 3. Commissioning plan

17 SALT-3190AS0001 Detector Safety Document 1 Southern African Large Telescope Prime Focus Imaging Spectrograph SAAO Detector Subsystem SALT-3190AS0001: Detector Safety Document Geoff Evans Dave Carter Willie Koorts James O Connor Darragh O Donoghue Faranah Osman Chantal Petersen Stan van der Merwe Issue February 2003

18 SALT-3190AS0001 Detector Safety Document 2 Issue History Number And File Name Person Issue Date Change History SALT-3190AS0001 Detector GPE Feb 2003 First draft for CDR Safety Issue 1.0.doc SALT-3190AS0001 Detector Safety Issue 1.1.doc Feb 2003 Final touch-up for CDR ACRONYMS AND ABBREVIATIONS ATP CCD CDR IEC HW N/A PDR PFIS SALT SW TBC TBD UPS Acceptance Test Procedure Charge-coupled Device (Camera) Critical Design Review International Electro technical Commission Hardware Not applicable to this Specification Preliminary Design Review Prime Focus Imaging Spectrograph Southern African Large Telescope Software To Be Confirmed To Be Determined Uninterruptible Power Supply Table of Contents 1 Scope Referenced documents Definitions (from SALT Safety Analysis Document 1000AA0030 Issue B) Hazard SEVERITY categories: Hazard occurrence FREQUENCY categories: Risk Classes Status...5

19 SALT-3190AS0001 Detector Safety Document Safety Committee Safety Analysis Procedure (from SALT Safety Analysis Document 1000AA0030 Issue B) PFIS Detector Subsystem...10

20 SALT-3190AS0001 Detector Safety Document 4 1 Scope This document specifies the safety analysis of the DETECTOR subsystem of PFIS, the Prime Focus Imaging Spectrograph of the Southern African Large Telescope. The document identifies the undesirable events, which can cause injuries to personnel, damage to the telescope equipment and interruption of the telescope operation. Section 5 describes the undesirable events, failure causes and preventive measures. 2 Referenced documents 1000AA0030 IEC PFIS DETECTOR Design Study SALT SAFETY Analysis Issue B.doc Functional safety of electrical/ electronics/ programmable electronic safety related systems 3 Definitions (from SALT Safety Analysis Document 1000AA0030 Issue B) There are different ways to determine the safety risk level for a specified safety function. SALT shall attempt to have a tolerable risk as low as reasonably practicable (ALARP), as described in IEC standard The basic principle defines the following: 3.1 Hazard SEVERITY categories: Severity A Severity B Severity C Severity D Catastrophic failure, which may result in severe injury, death or major damage to the telescope. Critical failure, which may result in minor injury and also interruption of telescope operation for more than one week. Marginal failure, which may result in interruption of telescope operation and cannot be repaired the same night. Negligible failure, which may result in interruption of telescope but can be repaired the same night.

21 SALT-3190AS0001 Detector Safety Document Hazard occurrence FREQUENCY categories: Frequent (F) More than 1 per year Probable (P) 1 per year Occasional (O) 1 per 10 years Remote (R) 1 per 100 years Improbable (I) 1 per 1000 years 3.3 Risk Classes Class I intolerable Class II undesirable, tolerable only if risk reduction is impracticable and too costly Class III tolerable if costs for risk reduction is higher than the improvement gained Class IV negligible risk. 3.4 Status The four parameters in the risk classification matrix can be combined with the purpose to identify the tolerable risk levels for different risks. Table 1 is the SALT risk classification matrix; which shall be used to ensure that the designs are practical and safe to implement. For practical use of the matrix the probability categories have to be quantified carefully and the meaning of hazard severity of each system be specified. The effect of hazard and the frequency of occurrence (Probabilities) can be determined by using reliability calculations, failure mode and effects analysis. Hazard Occurrence Hazard severity Category Frequency (Probability) A Catastrophic B Critical C Marginal D Negligible Frequent I I I II Probable I I II III Occasional I II III III Remote I III III IV Improbable II III IV IV Table 1 Each identified undesirable event may be in one of the following four phases of resolutions: Initial (Initial) SALT initial safety analysis Unacceptable (U) No acceptable design solutions found yet (Risk too high) Acceptable (A) Acceptable design solutions found (Risk okay) Verified (V) Solutions has been verified and implemented

22 SALT-3190AS0001 Detector Safety Document Safety Committee The Safety Committee shall consist of SALT Subsystem managers, System engineer, Control engineer and co-opted members. The purpose of the Safety Committee is to review the identified hazard and their proposed solutions.

23 SALT-3190AS0001 Detector Safety Document 7 4 Safety Analysis Procedure (from SALT Safety Analysis Document 1000AA0030 Issue B) Risk identification and risk reduction form an integral part of the acquisition, operation and maintenance, and the disposal phases of product or astronomical telescope and instruments. Figure 2 shows the typical lifecycle phases of the design and development activities of SALT project, the standard project phase related activities and the safety activities focused on safety related equipment and devices. This document shall be used to develop and compare alternative concepts during concept design phase to satisfy the original design. All the concepts shall be analysed by the project team with respect to the inherent manufacturing, test, installation, operation, maintenance hazards and risks. Based on the results of the analysis overall safety requirements shall be defined for SALT system. This document initially contains a preliminary safety analysis for SALT. Subcontractors shall review and expand this analysis to adequately assess the risk of safety related failures of their supplied equipment. During this process, they shall provide details of the safety measures proposed or/ and implemented in their equipment for approval by the SALT Safety Committee. This document shall be updated accordingly. The subcontractors shall demonstrate that the safety measures proposed have been implemented and they provide adequate protection. Risks of class I (as defined in Table1) are not acceptable. All risks of class II and III need to be approved by the SALT Safety Committee. Figure 1 below clearly demonstrates the three regions that Subcontractors may use as a test in regulating risks in their designs.

24 SALT-3190AS0001 Detector Safety Document 8 Figure 1 Intolerable Risk cannot be justified Tolerable (Risk is undertaken only if a benefit is desired) Tolerable only if further risk reduction is impractical or cost is more than improvement gained As the risk is reduced, it is necessary to spend more to reduce it further Broadly Accepted Region It is necessary to maintain assurance that risk remains at this level Negligible risk

25 SALT-3190AS0001 Detector Safety Document 9 Design and Development Activities Life Cycle Phase Safety Related Activities Responsible The product life cycle phase during which the requirements are specified The product life cycle phase which h/w and s/w are created and documented as designs and documentation such as operation and maintenance instructions are produced Concept Definition And Design Phase Design& Development Phase 1. Initial Hazard Risk Analysis 2. Definition of safety requirement 3. Subsystem Safety Analysis 4. Safety requirement allocation to risk reduction methods (s/w, h/w, elect, mech.) 1. Risk reduction method specification 2. Safety requirement allocation to h/w and s/w 3. Overall risk reduction operation, maintenance, verification, installation planning. 4. Hardware and software design and development. 5. Review subsystem safety analysis and preventive measures 6. Review and update SALT safety analysis doc 7. Assess system safety 1. Client 2. Client 3. Subcontractor 4. Subcontractor 1. Subcontractor 2. Subcontractor 3. Subcontractor 4. Subcontractor 5. Client 6. Client 7. Client The product life cycle phase during which product / system is produced, and system is assembled. Manufacturing Phase 1. Realisation of all h/w and s/w 2. Risk reduction method integration and safety verification. 3. Functional verification of the risk methods and measures. 1. Subcontractor 2. Subcontractor 3. Client The product life cycle phase during which the product / system is installed. Installation Phase 1. Installation, commissioning and verification of risk reduction methods. 2. Safety visit and inspection of equipments 1. Subcontractor/ Client 2. Client The product life cycle phase during which the product / system is put to use, maintained and supported. Operation and Maintenance Phase 1. Overall operation and maintenance 2. Controlled modifications 1. Client 2. Client Figure 2

26 SALT-3190AS0001 Detector Safety Document 10 5 PFIS DETECTOR Subsystem UNDESIRABLE EVENTS FIRST LEVEL CAUSES SECOND LEVEL CAUSES PREVENTIVE MEASURES SEVE- RITY ESTIM FREQUE STAT- US CROSS REFER PFIS DETECTOR falling off the instrument This undesirable event can occur as a result of first level causes 1 or 2 and 3 A I Initial 1. Multiple parts loosening on mount. Excessive vibration Not bolted on properly SALT designed for minimum of vibration Torque nuts and bolts I Initial Use chemical locking compounds or aircraft-type locking nuts. 2. Dropping components during installation or maintenance Inadequate handling equipment Install applicable handling equipment I Initial Safety net not used Use safety net Untrained personnel Train personnel Bottom cover removed Leave cover on as safety net if possible 3. Crane operator error Only trained dome crane operators shall carry out such operations I Initial Electrical shock 1. Chaffed mains cabling Bad cable routing Route cables correctly A I Initial 2. Power not switched off No Power switch Install power switch I Initial

27 SALT-3190AS0001 Detector Safety Document 11 UNDESIRABLE EVENTS FIRST LEVEL CAUSES SECOND LEVEL CAUSES PREVENTIVE MEASURES SEVE- RITY CCD s mechanically damaged or destroyed on the telescope 1. Loose mounting hardware physically damages the CCD s Fasteners not tightened to correct torque Torque fasteners correctly A ESTIM FREQUE STAT- US I Initial CROSS REFER CCD s electronically or electrically damaged or destroyed on the telescope 1. Electronic fault Short circuit of CCD signals Power supply fault Good quality connectors and wiring Good wiring practices Failsafe power supply A I Initial 2. Static damage due to incorrect handling Personnel not following procedures Lack of knowledge Inappropriate clothing Train maintenance personnel as per 3196AE0002 Warning signs on connectors/ cables that must not be unplugged I Initial 3196AE0 002 CCD Handling procedure Sound ESD practices 3. CCD destroyed by ion bombardment Ion pump switched on with its permanent magnet removed Train personnel Appropriate warning signs I Initial Vacuum pump falls off pumping platform 1. Pump not secured Untrained personnel Vibration Operator training Use clamp system that cannot be loosened by vibration B I Initial

28 SALT-3190AS0001 Detector Safety Document 12 UNDESIRABLE EVENTS FIRST LEVEL CAUSES SECOND LEVEL CAUSES PREVENTIVE MEASURES SEVE- RITY Sub units or small parts including fasteners and cover panels falling off PFIS DETECTOR with the possibility of injuring people or damaging the primary mirror PFIS DETECTOR catching fire 1. Loose nuts or bolts Vibration Torque nuts and bolts 2. Tools or components not secured to harness Unsafe tracker position Personnel not using safety procedures Human error Leaving tools on the tracker No Safety net under tracker 1. Electrical fault Oversized trip switch 2. Explosion of flammable gas or liquid Cryotiger working fluid Short circuit due to damaged insulation Use chemical locking compounds or aircraft-type locking nuts Move tracker to lower limit if possible to protect mirror Accessible components and fasteners to be captive Wear hard hats Use controlled toolboxes Use safety net Use correct trip switch Route cables correctly Use quality cables Open flame No open flames near Cryotiger system Appropriate warning signs on Cryotiger compressor 3. Electronics overheating Failure of glycol cooler Monitor electronics temperature B A ESTIM FREQUE STAT- US R Initial R Initial I R R Initial Initial Initial CROSS REFER 4. Glycol pipe bursts or leaks High Pressure, Corrosion, Ageing, Poor glycol line routing This is the responsibility of SALT R Initial

29 SALT-3190AS0001 Detector Safety Document 13 UNDESIRABLE EVENTS FIRST LEVEL CAUSES SECOND LEVEL CAUSES PREVENTIVE MEASURES SEVE- RITY Damage to sensitive electronic equipment due to static Moisture in electronics PFIS DETECTOR cooling system fails PFIS DETECTOR subsystem damaged SDSU Controller power supply failure 1. Maintenance procedures not followed Low humidity Nylon clothing Lack of knowledge Design in ESD protection Train maintenance personnel Warning signs on connectors/ cables that must not be unplugged 1. Condensation Cooler box too cold Monitor cooler box temperature 2. Dome open or leaking Operator error 1. Tracker damages Cryotiger pipes Snow or ice buildup Poor pressure hose routing Facility responsibility Electronics protected by waterproof housing Facility responsibility Ensure safe routing away from tracker motions Monitor PFIS DETECTOR CCD temperatures and warn user 1. Poor Quality Escom power Overloaded circuits Circuits not to be overloaded 2. Lightning induced power surge 1. Power surges Component failure PFIS DETECTOR to be UPS powered Failure of surge arrestors Correctly install and rated surge arrestors Age of power supply PFIS DETECTOR to be UPS powered PFIS DETECTOR to be UPS powered SALT to provide spare SDSU power supply unit B B ESTIM FREQUE STAT- US I Initial R Initial R Initial C I Initial C C I Initial R Initial O Initial CROSS REFER

30 SALT-3190AS0001 Detector Safety Document 14 UNDESIRABLE EVENTS FIRST LEVEL CAUSES SECOND LEVEL CAUSES PREVENTIVE MEASURES SEVE- RITY SDSU Controller failure Cryotiger compressor failure 1. Component failure Integrated circuit infant mortality Age of controller SALT to provide spare SDSU controller 1. Mechanical failure Age of compressor SALT to provide spare Cryotiger compressor C C ESTIM FREQUE STAT- US R Initial R Initial CROSS REFER Shutter failure 1. Jammed mechanism 2. Control signal failure Poor quality shutter Foreign materials Use quality mechanisms Design suitable covers D R Initial Control circuit failure Routine maintenance Electronics circuit failure 1. Power surges Poor circuitry design PFIS DETECTOR to be UPS powered D R Initial Conservative, thoroughly tested circuit design PFIS DETECTOR computer failure 1. Power surges Age of computer Use UPS power Use good quality computers D O Initial Hard drive failure Mechanical failure Electronic failure SALT to provide spare drive with PFIS DETECTOR system software installed O Initial Software bugs 1. Software not fully tested Poor programming Good programming practices D P Initial Test all software fully

31 SALT-3190BP0001 SAAO Statement of Work 1 Southern Africa Large Telescope Prime Focus Imaging Spectrograph SAAO Detector Subsystem SALT-3190BP0001: SAAO Statement of Work SAAO PFIS Detector Subsystem Team: Darragh O Donoghue Luis Balona Etienne Bauermeister Dave Carter Geoff Evans Willie Koorts James O Connor Faranah Osman Stan van der Merwe Issue January 2003

32 SALT-3190BP0001 SAAO Statement of Work 2 Issue History Number And File Name Person Issue Date Change History saao.icd.doc DOD Aug 2001 PFIS PDR issue SALT-3190BP0001 SAAO SOW Issue 1.3.doc Oct 2002 First pre-pfis CDR update SALT-3190BP0001 SAAO SOW Issue 1.4.doc SALT-3190BP0001 SAAO SOW Issue 1.5.doc Nov 2002 Major pre-pfis CDR update Jan 2003 Final PFIS CDR version Table of Contents 1 Scope Schedule Budget Work Detector Subsystem Integration, Test, & Operations Other Documentation Functional Performance and Requirements Document (FPRD) Operational Concept Definition Document (OCDD) Acceptance Test Plan Commissioning Test Plan Optical Specifications and Drawings Mechanical Specifications and Drawings Electrical Specifications and Drawings Parts Lists Wiring Lists Software Modules and Listings Vendor Data Sheets... 7

33 SALT-3190BP0001 SAAO Statement of Work Assembly, Shipping & Installation User's Manual and Calibration Manual Maintenance Manual Deliverables For PFIS CDR Schedule Budget Design Work Towards The CDR... 9

34 SALT-3190BP0001 SAAO Statement of Work 4 1 Scope This document is the Statement of Work between the University of Wisconsin-Madison and the South African Astronomical Observatory (SAAO). It specifies the work to be done by SAAO in connection to the UW's Prime Focus Imaging Spectrograph (PFIS). 2 Schedule The Detector subsystem PI shall provide a schedule, compatible with Microsoft Project 2000, to the PFIS project manager. The initial delivery shall occur 1 month before PDR, and shall be updated each quarter. 3 Budget The Detector subsystem PI shall provide a budget to the PFIS project manager. The initial delivery shall occur 1 month before PDR, and shall be updated each quarter. The budget shall show costs of materials, labor, capital equipment, and overhead, broken down by quarter. 4 Work The Detector subsystem PI agrees to perform the following work. 4.1 Detector Subsystem 1. Design and build a cryogenically-cooled detector housing 2. Integrate the PFIS CCD detectors into the detector housing 3. Integrate the detector housing with an SDSU II Array Controller and Power Supply 4. Characterize detector subsystem performance 5. Provide a LabView virtual instrument control software for the subsystem 4.2 Integration, Test, & Operations 1. Support integration of the Detector subsystem into PFIS 2. Support laboratory testing of the Detector subsystem in PFIS 3. Support commissioning of the Detector subsystem of PFIS at SALT 4. Write observing software for the Detector subsystem

35 SALT-3190BP0001 SAAO Statement of Work 5 5. Write data reduction software for Detector subsystem observations up to the point where detector-specific calibrations (dark frames if relevant, bias frames and flat fielding) are employed. Further reductions, such as wavelength calibrations, or standard star observations are outside the scope of the work. 4.3 Other 1. Participate in PDR and CDR 2. Consult on commissioning science observation program for PFIS 3. Prepare a scientific paper describing the Detector subsystem if deemed sufficiently meritorious, or co-author a paper on the instrument as a whole and contribute the section describing the Detector subsystem. 5 Documentation This section specifies the documentation to be supplied to UW-Madison with the Detector subsystem. Text documentation shall be provided in MS Word or PDF format. Mechanical drawings shall be provided in an electronic format compatible with Autocad release 14. Table 1 shows the delivery dates for certain documents. Documentation described below but not included in Table 1 due with the delivery of the Detector Subsystem to UW- Madison. Table 1: Document Delivery Schedule Document Version Delivery Date Statement of Work Draft PDR 4 weeks UW/SAAO ICD Draft PDR 4 weeks FPRD Draft PDR 4 weeks OCDD Draft PDR 4 weeks PDR Documents Draft PDR 3 weeks UW/SAAO ICD Final PDR + 8 weeks FPRD Final PDR + 8 weeks PDR Documents Final PDR + 8 weeks OCDD Final CDR 6 weeks Acceptance Test Plan Final CDR 6 weeks Commissioning Test Plan Final CDR 6 weeks

36 SALT-3190BP0001 SAAO Statement of Work 6 CDR Documents Draft CDR 3 weeks CDR Documents Final CDR + 8 weeks 5.1 Functional Performance and Requirements Document (FPRD) The Dectector subsystem PI shall provide a Functional Performance and Requirements Document (FPRD) that states the end-item performance specifications, and a verification matrix showing the method of verification of each performance specification. The PI shall provide the FPRD as indicated in Table Operational Concept Definition Document (OCDD) The Detector subsystem PI shall provide a Operational Concept Definition Document (OCDD) describes the operational scenarios relevant to using the Detector subsystem. The PI shall provide the OCDD as indicated in Table Acceptance Test Plan The Detector subsystem PI shall provide an acceptance test plan suitable for demonstrating correct operation of the Detector subsystem. The acceptance test will be run at SAAO before shipping to UW, at UW after shipping from SAAO and during integration, before shipping to South Africa, and again after arriving in South Africa. The plan shall be suitable for verification of correct operation as well as diagnosis of problems, in so far as they can be carried out in each location. The Detector subsystem PI shall provide an Acceptance Test Plan as indicated in Table Commissioning Test Plan The Detector subsystem PI shall provide a commissioning test plan suitable for demonstrating compliance with the FPRD and SOW. The Detector subsystem PI shall provide Commissioning Test Plan as indicated in Table Optical Specifications and Drawings The Detector subsystem documentation shall include specifications for all optical components. (Jeff, this can only include the cryostat window so I would suggest putting this in your next section).

37 SALT-3190BP0001 SAAO Statement of Work Mechanical Specifications and Drawings The Detector subsystem documentation shall include the definition of all mechanical components and subsystems. COTS entities will be defined by supplier details and proprietary parts numbers. Custom components and assemblies will be defined by ACAD14 compatible drawings. Assembly drawings will be of sufficient detail to enable a competent technician to interpret them. 5.7 Electrical Specifications and Drawings The Detector subsystem will include both COTS and custom electronics. The custom electrical specifications shall include voltage, current, peak and average power. 5.8 Parts Lists The Detector subsystem documentation shall include a complete description of materials, parts and components. 5.9 Wiring Lists The Detector subsystem documentation shall include a complete description of all internal wiring, all wiring diagrams, and wire lists describing every cable and connector Software Modules and Listings The Detector subsystem documentation shall include all software listings in electronic format. The documentation shall include a software block diagram showing the relationship of software modules, and describe all inputs and outputs for each module. Also included are all test procedures for component and subsystem-level testing and verification Vendor Data Sheets The Detector subsystem documentation shall include vendor data sheets and specifications for all commercially supplied components Assembly, Shipping & Installation The Detector subsystem documentation shall include manuals that describe the assembly (and disassembly) of the Detector subsystem, how to pack and ship it, and how to install it into the PFIS.

38 SALT-3190BP0001 SAAO Statement of Work User's Manual and Calibration Manual The Detector subsystem documentation shall include a user's manual describing all operational aspects of the Detector subsystem and its calibration Maintenance Manual The Detector subsystem documentation shall include a maintenance manual. The manual shall contain procedures for periodic maintenance and troubleshooting.

39 SALT-3190BP0001 SAAO Statement of Work 9 6 Deliverables For PFIS CDR The Detector subsystem PI agrees to perform the following work for the CDR of PFIS, scheduled for March Schedule The Detector subsystem PI shall update the PDR schedule and send it to the PFIS project manager. The initial delivery shall occur by Jan 2003, and shall be updated each following quarter. 6.2 Budget The Detector subsystem PI shall provide an updated budget to the PFIS project manager. The initial delivery shall occur by end Oct 2002 and shall be updated each following quarter. The budget shall show costs of materials, labor, capital equipment, and overhead, broken down by quarter. 6.3 Design Work Towards The CDR The Detector subsystem PI shall provide the following design documents/reports to the PFIS project manager: ICD This document will be an update of the earlier versions Testing Document This document will describe the Acceptance Testing (by UW of the detector package from SAAO). This document will be complete in that it will mention every aspect of the detector package that needs to be tested. However, details of the tests may be supplied only during manufacture Safety Document This document will confine itself to the safety of the detector package alone. It will be modeled on the SALTICAM equivalent.

40 SALT-3190BP0001 SAAO Statement of Work Detector Document This document will describe the CCD detector and controller performance, similar to the design study document provided for PDR but more specific and with as much concrete information in as possible, using the SALTICAM experience. All control issues (e.g. the shutter) will be included in this document as well. Mosaicing of the PFIS CCDs will also be addressed in this document CCD Handling Procedures A document describing the procedures for safe handling of the CCDs Cryostat Document Document describing the cryostat design from a mechanical and thermal point of view Software Documents A suitable document describing the software Drawings A suitable set of drawings (TBD).

41 SALT-3196AE0001 Detector Document 1 Southern Africa Large Telescope Prime Focus Imaging Spectrograph SAAO Detector Subsystem: SALT-3196AE0001: Detector Document SAAO PFIS Detector Subsystem Team: Dave Carter Luis Balona Etienne Bauermeister Geoff Evans Willie Koorts James O Connor Darragh O Donoghue Faranah Osman Stan van der Merwe Issue March 2003

42 SALT-3196AE0001 Detector Document 2 Issue History Number And File Name Person Issue Date Change History saao.design-study.doc DBC Oct 2002 PFIS PDR issue SALT-3196AE0001 Detector Issue 2.0.doc SALT-3196AE0001 Detector Issue 2.1.doc SALT-3196AE0001 Detector Issue 2.2.doc SALT-3196AE0001 Detector Issue 2.3.doc SALT-3196AE0001 Detector Issue 2.4.doc SALT-3196AE0001 Detector Issue 2.5.doc SALT-3196AE0001 Detector Issue 2.6.doc Nov 2002 First pre-pfis CDR update EFB Nov 2002 Added Sub-System Controller Section EFB Dec 2002 Fixed some errors in Subsystems Controller Section DBC Dec 2002 First major edit for CDR DBC Feb 2003 Inserting mosaicing information. DBC Feb 2003 Insert SDSU controller performance and final touchups for CDR. DBC Mar 2003 Add 3 rd PFIS CCD parameters and fix some formatting problems Table of Contents 1 Scope Overview The CCDs Basic Parameters Sensitivity Frame Transfer Architecture Mini-Mosaic Cosmetics Dark Current and Operating Temperature Readout Noise CCD Controller... 9

43 SALT-3196AE0001 Detector Document Readout Speed Lowest Noise Full Frame Readout Rapid Full Frame Readout Prebinning Frame Transfer Operation Windowing Gain Readout Speed Analysis Readout speed calculations SDSU Controller Configuration Introduction Tests Performed CCD Image area Clock structure a primer Test Results Waveforms with clock pulse width=50µs, Row transfer time=100µs Waveforms with clock pulse width=25µs, Row transfer time=50µs Tabulated Results Discussion Conclusion/Recommendation Sub-Systems Controller Temperature Monitoring Varian Ion Pump EMI Protection of Signals Mosaicing Functional Requirements Mosaicing a Detector System Mosaicing Specifications CCD44-82 Physical Dimensions E2V CCD44-82 Flatness specification E2V CCD44-82 Reflectivity Specifications for the assembled PFIS mosaic: Mosaicing Procedure... 38

44 SALT-3196AE0001 Detector Document 4 9 List of TBC Issues... 39

45 SALT-3196AE0001 Detector Document 5 1 Scope This document reports a design study for the Detector Subsystem of the University of Wisconsin-Madison's Prime Focus Imaging Spectrograph (PFIS). It specifies the performance that the Detector Subsystem could meet to satisfy the overall performance goals of the spectrograph. CCD procurement was recognized to be a long lead time purchase and a contract was concluded with Marconi Applied Technologies in January 2002 to secure devices for the two SALT first light instruments. (Note: in July 2002, Marconi Applied Technologies became E2V but for the remainder of this document, they will still be referred to as Marconi) 2 Overview The detector subsystem will comprise a cryostat containing a 3x1 mini-mosaic of CCD chips. These chips shall be Marconi CCDs with 2k x 4k x 15 micron pixels. They shall be mounted on an invar cold plate and it is decided that SAAO will do the mosaicing in order to achieve co-planarity of the devices. The mosaic shall be housed in an evacuated cryostat and thermally connected to the cold end of a Cryotiger, which shall cool the chips sufficiently to render dark current insignificant, whilst at the same time reducing QE by the smallest extent possible. The detectors shall be managed by an SDSU III CCD controller, which will in turn be controlled by a PC. 3 The CCDs In terms of a contract between the SALT Foundation and Marconi, the latter will supply their CCD chips for use as the PFIS detectors. Other potential sources of chips were discussed in the PDR version of this document, saao.design-study.doc, which should be consulted for details. 3.1 Basic Parameters The CCD characteristics may be obtained from the Marconi data sheets, the most important details of which are reproduced below. In this list, guaranteed (min or max as appropriate) as well as (more generous) typical figures are quoted:

46 SALT-3196AE0001 Detector Document x 4096 x 15 micron square pixels 30.7 x 61.4 mm 2 imaging area Thinned and back-illuminated 3-side buttable 2 output amplifiers Charge transfer efficiency: min: per cent, typical per cent Pixel readout frequency khz Peak signal (full well): min: 150 k e - /pix, typical: 200 k e - /pix Readout noise (at 188 K, 20 khz): max: 4.0 e - /pix, typical: 2.5 e - /pix QE at 500 nm: 80 per cent Spectral range: nm Dark current (at 153 K): max: 4, typical: 0.1 e - /pix/hr Typical QE at -100C: deep depeletion astro broadband response E2V Technologies (ex Marconi) July QE wavelength (nm)

47 SALT-3196AE0001 Detector Document Sensitivity Dr. Paul Jorden of Marconi has provided the above plot (Fig. 1) showing typical performance for Marconi deep depletion silicon and Astro BB anti-reflection coating devices, which have been selected for PFIS. However, it must be remembered that the plot shows typical performance figures (i.e. the mean of a large sample of Marconi devices). Any specific device may not achieve this performance. Marconi have undertaken to guarantee minimum performance as specified in the table below, shown alongside the typical sensitivity for comparison: Table 1 Table 1 CCD Spectral Response Wavelength Minimum QE Typical QE SALT-03 SALT-04 SALT nm >40% 50% nm >70% 80% nm >75% 80% nm >70% 75% nm >45% 50% nm No spec No spec At the time of writing, three science grade devices have been delivered; and their properties are shown in Table 1 under the columns SALT-03, SALT-04 and SALT Frame Transfer Architecture In order to enable rapid spectroscopy, FT operation is essential. None of the large format devices made by Marconi are available off the shelf in Frame Transfer (FT) Mode. Marconi are supplying FT chips in terms of the contract with SALT. This requires a redesign of the clock lines of the chip and therefore a special production run from Marconi. The completion date for the order for the PFIS devices is end February 2003.

48 SALT-3196AE0001 Detector Document Mini-Mosaic A mini-mosaic of 3x1 CCDs will be used. Mosaicing will be carried out by SAAO. See Section Cosmetics In terms of the contract between SALT and Marconi, the latter may supply grade 0 (preferably) or grade 1 (minimum) devices. The numerical definition of these specifications is shown in Table 2, along with the acceptance test reports for the first two devices. Table 2 CCD Grade Blemish Specification Defects Grade 0 Grade 1 SALT-03 SALT-04 SALT-05 Column defects (black or white) White spots Total spots (black or white) Traps 6 or less 12 or less or less 1250 or less 30 or less 1000 or less 2000 or less 50 or less Dark Current and Operating Temperature The performance goal for dark current is to ensure that noise on the dark current pedestal generated during the longest exposure is small compared to the readout noise. We estimate that, with minimum readout noise of 2.5 e - /pix, a dark current rate of 1 e - /pix/longest exposure will fulfill this satisfactorily. The longest exposure is expected to be about 1 hr. So dark current rate of no more than 1 e - /pix/hr is proposed. From the typical dark current rate on the Marconi data sheet (0.1 e - /pix/hr at 153 K) and the T 3 e /T scaling with temperature specified by Marconi, this implies an operating temperature of 163 K or less. Measured dark currents in the first three devices are 0.71, and e - /pix.

49 SALT-3196AE0001 Detector Document Readout Noise Marconi guarantee a readout noise from the on-chip amplifier of 4.0 e - /pix at a readout speed of 20 khz. 2.5 e - /pix is typical. A plot in the data sheet shows this typical figure rising to 5.5 e - /pix at the maximum certified speed of 1000 khz. It might be expected that the maximum readout noise from the on-chip amplifier at 1000 khz would be 4.0/2.5 x 5.5 = 8.8 e - /pix. We expect the SDSU II controller and additional electronics to add 1.5 e - /pix (assuming a gain of 1 e - /ADU). We thus propose the following readout noise performance: 3.0 e - /pix at 100 khz (10.0 µsec/pix) 5.0 e - /pix at 380 khz (3 µsec/pix) These values are TBC1. In terms of the Marconi contract, at a readout speed of pixels/sec, the readout noise must be less than 4 electrons per pixel RMS for all science grade SALT CCDs with typical performance of 2.5 electrons per pixel RMS. The first three PFIS chips have the following performance: Readout Noise (e - /pix) SALT-03 SALT-04 SALT & & & 1.9 Note: Two values for each device are listed because each device has a split output serial register (readout register) and two output amplifiers. 4 CCD Controller Images are obtained by clearing all charge from the CCD detectors, exposing them to light and reading them out with the CCD controller which will be an SDSU III (Leach) controller from Astronomical Research Cameras (San Diego). CCD readout proceeds by clocking the charge in each pixel towards the readout amplifier where it is measured, digitised and sent to the control computer. A schematic of the chip architecture is shown in Fig. 2 (not drawn to scale). The Marconi CCDs have a split readout register with a readout amplifier at either end; each readout amplifier is preceded by 50 extra pixels which are never exposed to light.

50 SALT-3196AE0001 Detector Document columns vertical clocking IMAGE AREA 2049 rows Frame Transfer boundary vertical clocking STORE AREA 2053 rows Readout Amp 1 50 pix Split readout register 50 pix Readout Amp columns Figure 2. CCD architecture for Marconi devices The readout noise associated with the charge measurement process results in a compromise between readout speed and noise: the faster the readout the higher the readout noise. Readout speed is increased if the pixels are combined before being fed through the readout amplifier which is where most time is required. Pixel combination, or prebinning, effectively combines 2 or more rows into the readout register, or 2 or more pixels into one with the combined charge before being fed into the readout amplifier. Windowing is also a possible means of speeding up readout in which pixels in the

51 SALT-3196AE0001 Detector Document 11 readout register which lie outside the desired window are skipped rapidly. Frame transfer operation is another way to reduce readout time further. When operated this way, half of each chip closest to the readout register is masked from light (labeled Store Area in Fig. 2; see also Fig. 3). At the end of an exposure, a frame transfer takes place (in 0.10 sec) transferring the image formed in the half of the chip furthest from the readout register (labeled Image Area in Fig. 2) to behind the mask. Readout of the masked region proceeds as the next exposure is accumulating. In addition to reducing the amount of data to be read out, this technique has the advantage that there is no dead time during read out. The shutter is open throughout this sequence. The field of view is, of course, halved with frame transfer operation. The controller will have 4 video channels allowing the use of the two available output amplifiers per CCD chip. 4.1 Readout Speed Marconi certify performance in the range khz. The SDSU III controller allows readout rates of no more than 1000 kpix/s. Due to the need for real Marconi chips with which to conduct tests, we will use performance estimates from Guy Woodhouse, a CCD engineer we know well who worked on La Palma and now works on the fast CCD camera for the Faint Object Spectrograph for Subaru. Guy has solid experience with the same kind of Marconi chips and SDSU controllers. For the present, we thus aim to match the performance he reports. (However, recent communication from Vikram Dhillon of Sheffield University (U.K.), reporting on the Ultracam instrument commissioning run, indicates that a degree of caution should be exercised when predicting readout speeds with Marconi detectors. The Ultracam experience was that the vertical clock times achieved with good performance were significantly longer than those predicted by Marconi. The Ultracam detectors are AIMO devices, and PFIS uses non-aimo detectors, thus the relevance of this report to PFIS is uncertain.) Correlated Double Sampling (CDS) speeds of 3.0 µsec/pix (at 5 e - /pix readout noise) or 4.6 µsec/pix (at 3.5 e - /pix readout noise) have been achieved with the proposed chips and SDSU controllers by Guy. It may be possible to reduce the 3.0 µsec/pix (with readout noise penalty) but this remains to be investigated. This figure increases linearly with horizontal prebin factor by approximately 1.0µsec/pix. Windowing also adds some overhead to the total readout time (TBC2). We therefore propose a discrete set of normal pixel readout rates in the range khz (TBC3) and software selectable (slower readout rates would result in unacceptably long readout times). In addition, drift scan and charge shuffling during exposure will

52 SALT-3196AE0001 Detector Document 12 require special control of the vertical clocks which will be synchronized at a software selectable rate. Overheads are also associated with row transfers, 50 µsec per row, and pixel skips in the readout register (discards) of 1.0 µsec/pix (TBC4). Each CCD has 4102 rows, 2048 columns and 2 readout amplifiers. There are an additional 50 pixels at the end of each readout register but before the readout amplifier. Thus, readout requires feeding 4106 rows of ( ) columns, or a total of pixels, through each readout amplifier. The following sections discuss various readout modes such as prebin, window, frame transfer and slot mode, and show example calculations of readout time for various combinations. Section 5 gives a more detailed analysis of readout time. 4.2 Lowest Noise Full Frame Readout Lowest readout noise is expected at the slowest readout rate of 100 khz (10 µsec/pix). Readout times at this rate would be: o Time to clear the chip prior to exposure or time for vertical transfers during readout: 4102*50 µsec = sec o Time to read out the full chip (without prebinning): sec *10.0 µsec = sec (readout noise of 3 e - /pix: TBC1) 4.3 Rapid Full Frame Readout The above timing considerations give rise to the following expected performance when high time resolution is desired: o Minimum time to read out the full chip (without prebinning): sec *3.0 µsec = sec (readout noise of 5 e - /pix) Readout time can be decreased further by any one of (or combinations thereof): Frame transfer operation so that only half the detector is used. There is no readout dead time as the next exposure is accumulating during the readout. Prebinning (see next section) Windowing of the chip either in the spatial or wavelength direction or both

53 SALT-3196AE0001 Detector Document Prebinning Software-selectable prebinning of 1x1 to 9x9 (independent in each dimension) will be offered. It is expected that at least 1x2 prebinning will be used as standard where the 2 refers to the spatial direction. For all but the highest resolution observations, 2x2 prebinning will be used. Such prebinning will then result in minimum readout times of: o 1x2 prebinning: sec *11.0 µsec = sec (3 e - /pix readout noise: TBC1) o 2x2 prebinning: sec *11.0 µsec = sec (3 e - /pix readout noise: TBC1) o 1x2 prebinning: sec *4.0 µsec = sec (5 e - /pix readout noise) o 2x2 prebinning: sec *4.0 µsec = sec (5 e - /pix readout noise) We believe there will be a 1 µsec overhead for each horizontal prebinning increment (essentially the time to combine pixels during readout). However, this is TBC Frame Transfer Operation Frame Transfer capability will be provided by the CCD controller. In this mode, at the end of an exposure of the half of the chip furthest from the readout register (the image section of the chip), the data are rapidly shifted (in sec) into the half of the chip next to the readout register (the store section). (illustrated in Fig. 2)Readout of the store section then takes place. Naturally, the store section of the chip must be masked from light so that half the science FoV must be sacrificed. The shutter is open throughout the sequence of operations.

54 SALT-3196AE0001 Detector Document 14 Figure 3. Full frame operation is depicted in the left schematic. The right schematic shows frame transfer operation with the frame transfer mask obscuring half of the detector Minimum readout times are (with 4102 vertical transfers required because although only 2053 are required to move the image into the store area, vertical transfers in the store area are still required): o No prebinning: 102*50 µsec + (1074*205348*10.0) µsec = sec (3 e - /pix readout noise) o 1x2 prebinning: 4102*50 µsec + (1074*1027*11.0) µsec = sec (3 e - /pix readout noise). o 2x2 prebinning: 4102*50 µsec + (537*1027*11.0) µsec = sec (3 e - /pix readout noise). o No prebinning: 4102*50 µsec + (1074*2053*3.0) µsec = 6.82 sec (5 e - /pix readout noise) o 1x2 prebinning: 4102*50 µsec + (1074*1027*4.0) µsec = sec (5 e - /pix readout noise). o 2x2 prebinning: 4102*50 µsec + (537*1027*4.0) µsec = sec (5 e - /pix readout noise). Thus, a continuous sequence of images with sec sampling and no dead time can be obtained. Image smearing will occur during the sec needed for frame transfer. 4.6 Windowing Readout of up to 10 windows (TBC6) of rectangular shape and arbitrary size will be offered by the CCD controller. Note that a window defined on one half of one CCD chip

55 SALT-3196AE0001 Detector Document 15 is also applied to the other half, as well as replicated twice on each of the other two chips. This is because the readout through each amplifier must use the same clocking scheme. The implication of this for spectroscopy is that windowing in the dispersion direction will result in 6 discrete wavelength intervals being readout. The scientific value of windowing in the dispersion direction in spectroscopy seems limited (but perhaps not zero). Two examples will illustrate the readout rate possible with windowed operation. The performance in these examples must certainly be confirmed (TBC7). In the first, a spectrum is to be obtained of a point source located near the middle of the chip, just above the frame transfer boundary, with wavelength range spanning the full width of the detector in dispersion, and 8.64 arcsec (64 pixels) in the cross dispersion direction. Assuming frame transfer operation and 2x2 prebinning, the minimum readout time would be: sec + (32*537*4.0) µsec = sec Where the first contribution (0.205 sec) is the time taken to shift the spectrum down by roughly half a frame (to the readout register) and the time needed for vertical transfers in the store section of the chip. The second contribution (0.068 sec) is the time taken to read out the 32 x 537 pixels. However, the image would be exposed for only sec and there would be sec of dead time, so unacceptable smearing would result. The sec contribution could be eliminated, thereby yielding spectroscopy at a speed of faster than 10 Hz, if the spectrum is shifted just over the frame transfer boundary, rather than all the way down to the readout register. The minimum readout time would then be: (64*50) µsec + (64*50) µsec + (32*537*4.0) µsec = sec sec sec = sec A sequence of such spectra could then be obtained with a cycle time of sec (allowing seconds for safety) and image smearing over a sec interval. The second example is an imaging example in which a target and two comparison stars are to be sampled rapidly by reading out three 128x128 boxes of pixels centred on the three objects. In full frame mode (i.e. shuttered), but 2x2 prebinning, the minimum readout time would involve: sec for vertical transfers, (3*64*( )*1.0) µsec for pixel skipping and (3*64*64*4.0) µsec for pixel reads. These contributions are: sec sec sec = sec once again dominated by the time for vertical transfers. Frame transfer operation would cut this time in half.

56 SALT-3196AE0001 Detector Document Gain The SDSU controller allows the gain to be scaled by one of four preset factors: x1; x2; x4.75; x9.5. The base gain can be set by adjusting the electronics and this is still to be decided: TBD1. 5 Readout Speed Analysis As high time resolution is a niche scientific area, and in response to a request following the PDR, this section seeks to clarify the issue of readout time. We present formulae for calculating readout speeds for the various readout modes. The following definitions apply: Rows An array of 4102 columns. There are 4102 rows (4096+6) that are simultaneously clocked down the device towards the readout register. Cols An array of 2148 pixels ( ) that is clocked serially to the output amplifier. The array is split in two and has two outputs operating in parallel, thus the effective size of the array is 1074 pixels. P dat P skip Data Pixel. A pixel that forms part of the required image data. It can be binned or unbinned, part of a window or full frame/frame transfer image. Skip Pixel. A pixel in the Columns array that is not part of the required image data. Skip pixels have to be clocked out of the detector, thus degrade performance by wasting readout time. PB col The columns prebin factor. Range of 1 to 9 PB row The rows prebin factor. Range of 1 to 9 T row T col T proc 5.1 Readout speed calculations 50µS. Time required to do one row shift. Marconi specifies 100µS, but various communications indicate that 50µS is a realistic time for fast clocking of small signal levels. 1.0µS. Time required to shift the serial register by one pixel. 2.0µS (fast) & 9.0µS (slow). Overhead time associated with signal processing on each data pixel. We now give some examples, repeating the calculations of Section 4 and adding some new cases. Note that windowed readout almost requires a different formula for each case!

57 SALT-3196AE0001 Detector Document 17 Example 1. Full Frame Readout, slow, unbinned: T = (rows * T row ) + (cols * rows * (T col + T proc )) = (4102 * 50) + (1074 * 4102 * ( )) µs = 44.3 seconds Example 2. Full Frame Readout, fast, unbinned: T = (rows * T row ) + (cols * rows * (T col + T proc )) = (4102 * 50) + (1074 * 4102 * ( )) µs = 13.4 seconds Example 3. Frame Transfer Readout, fast, unbinned: T = (rows * T row ) + (cols * (rows/2) * (T col + T proc )) = (4102 * 50) + (1074 * 4102/2 * ( )) µs = 6.81 seconds In normal use, PFIS will be read out in prebinned mode. For this case, the above formula becomes: T = (rows * T row ) + ((cols/pb col ) * (rows/pb row ) * ((T col * PB col )+ T proc )) Example 4. Full Frame readout, fast, binned 2*2: T = (4102 * 50) + ((1074/2) * (4102/2) * ((1.0 * 2) + 2.0)) µs = 4.61 seconds Example 5. Frame Transfer readout, fast, binned 2*2: T = (4102 * 50) + ((1074/2) * (4102/(2*2)) * ((1.0 * 2) + 2.0)) µs = 2.41 seconds Example 6. Full Frame readout, fast, binned 4*4: T = (4102 * 50) + ((1074/4) * (4102/4) * ((1.0 * 4) + 2.0)) µs = 1.86 seconds Example 7. Frame Transfer readout, fast, binned 4*4:

58 SALT-3196AE0001 Detector Document 18 T = (4102 * 50) + ((1074/4) * (4102/(4*2)) * ((1.0 * 4) + 2.0)) µs = 1.03 seconds Note that binning does not gain a factor of PB col * PB row as might naively be expected. It certainly gains a factor of PB row, but the gain in binning in the output register is offset by the fact that the relevant pixels have to be shifted anyway. PFIS also allows windowed (sub-array) readout. The window may be binned or unbinned. Window mode readout can be done in both full frame and frame transfer mode. As multiple windows are allowed, the readout time calculation becomes increasingly complex. Example 8. One window (actually two due to the parallel operation of the two outputs of the CCD), binned 2x2: For this case, more variables have to be defined: WC 100. Number of unbinned columns in window PWC 99. Number of unbinned columns to discard before the start of the window WR 100. Number of unbinned rows in window PWR 100. Number of unbinned columns to discard before the start of the window N 875. Number of unbinned columns to discard after the window such that N = Cols (WC + PWC) The formula becomes: T = (Rows * T row ) + [(WC/PB col ) * (WR/PB row ) * ((T col * PB col )+ T proc )] + [WR/ PB row * ((PWC + N)* T col )] This formula can be expressed as: (Total row transfer time) + (total binned window time) + (total unbinned pre-and-post window time) T = (4102 * 50) + [(100/2) * (100/2) * ((1.0 * 2)+ 2.0)] + [100/2 * (( )* 1.0)] = 0.26 seconds

59 SALT-3196AE0001 Detector Document 19 Readout Mode Table 3: PFIS Readout times PFIS Readout times (in seconds) lowest noise Highest speed, various binning factors 2x2 binning 1x1 2x2 3x3 4x4 9x9 Full Frame Frame Transfer Full Frame, 1 window (100x100) Full Frame, 2 windows same row (100x100) Full Frame, 2 windows separate rows (100x100) Additional values are shown in Table 3. They were calculated using a Readout time calculator set up in the file Readout time calcs.xls This is available to any interested party. In all cases in Table 3 of full frame readout or frame transfer readout, the smearing time or row transfer time, is sec. This is apparent as a tendency for the readout times to converge on this number as the prebinning gets larger and larger. 6 SDSU Controller Configuration 6.1 Introduction An important design decision to be made regarding the SDSU controller configuration for PFIS is the number of clock boards necessary to drive the 3-device mini-mosaic. This affects the size of the controller crate, which has size & mass implications for the instrument. The standard SDSU controller configuration is a 6-slot card frame. For PFIS, the following minimum number of PCBs are required: Timing Board x1 Utility board Clock board x1 x1

60 SALT-3196AE0001 Detector Document 20 Video Board x3 (The PFIS detector package has three CCDs each with two outputs, each SDSU video board has two channels) Thus for the PFIS detector system the 6-slot card frame will be fully populated. If more than one clock board is required to drive the PFIS mosaic, the SDSU 12-slot card frame will have to be used. This is a much larger and heavier box than the 6-slot card frame. There has been some doubt as to whether the SDSU clock board can successfully drive multiple CCD detectors. Opinions sought from users of the SDSU controller have ranged from I have done this and it was fine to I wouldn t want to try to do that. Many groups use the SDSU controller with E2V 2Kx4K detectors apparently satisfactorily. As part of the preparatory work for the PFIS detector system, SAAO has performed tests using the SALTICAM detector hardware to evaluate the ability of the SDSU clock board to drive multiple CCDs. Provisional results are presented here. 6.2 Tests Performed Due to a number of delays to the SALTICAM project it has not been possible to do actual performance tests (i.e. Charge Transfer Efficiency and image smearing) at this time. The tests done involved evaluating the SDSU clock board driver capabilities by examining the image area clock waveforms when driving different configurations and numbers of CCDs with a single SDSU clock driver board. The test results in the form of oscilloscope screenshots are presented below. 6.3 CCD Image area Clock structure a primer CCDs have a system of clock electrodes laid across the imaging area which are used to define pixel positions and to move signal charge towards the output node. The E2V devices as used in SALT detector packages have three clock phases per pixel. During exposure time unvarying voltages are applied to these phases in a low-high-low pattern, and signal charge accumulates under the high clock. To read out the CCD the clock phases alternate between a high and low voltage in a fixed pattern to move the signal charge along. I refer to this fixed clock pattern as a triplet in this document. One clock triplet moves the signal charge along by one pixel. Figure 6.1 is an example of such a clock triplet. The triplet is repeated 4102 times in the case of the CCD44-82 detector to move the entire image down to the readout register.

61 SALT-3196AE0001 Detector Document 21 ØI1 ØI2 ØI3 Figure 6.1: CCD Image Area Clock Triplet From Figure 6.1 note: 1. Clock pulse width 50µs 2. Clock overlap T o is ~16µs 3. Rise time T r of ØI1 is ~16µs, fall time T f is ~14 µs 4. Clock Triplet time ~110µs including fall time of last clock edge.

62 SALT-3196AE0001 Detector Document 22 Clock I2 Clock I3 CCD1 CCD2 CCD3 Image Area Image Area Image Area Clock board driver circuits Store Area Store Area Store Area Readout Register Readout Register Readout Register Clock S1 Clock S2 Clock S3 Figure 6.2: PFIS detectors clock connection scheme Due to their close proximity to each other in the CCD structure, the clock electrodes form capacitors with each other and with the substrate of the CCD. The crosstalk evident between clock phases in Figure 6.1 is an artifact of this capacitive coupling. The above discussion serves to introduce the fact that the CCD image area clock electrodes present a relatively high capacitive load to the controller electronics clock driver circuits. This concept is crucial for a correct evaluation of the test results below. Capacitive loads introduce clock rise/fall time limits on the maximum speed (minimum clock pulse width) achievable with a given clock driver circuit. CCDs are available in full-frame and frame-transfer architecture. In the full-frame CCD, the image area clock electrodes are brought out to three pins on the device connector. A frame-transfer CCD has the image area divided into two halves designated image and store areas, the three image area clocks are brought out to three pins and the three store area clocks are brought out to an additional three pins on the device connector. The SALT CCD44-82 detectors are frame transfer CCDs. For the purposes of these tests I have defined each CCD as representing two equal clock loads image area clocks and store area clocks. A non-frame-transfer CCD has image & store area clocks connected together on-chip, and thus counts as two loads. A frame transfer CCD has image and store area clocks wired independently to pins on the device

63 SALT-3196AE0001 Detector Document 23 connector. Three frame-transfer CCDs as used in the PFIS detector system total 6 loads. Figure 6.2 shows a clock connection scheme for the PFIS detector package using one clock board. 6.4 Test Results Tests were done using an oscilloscope to examine the clock waveforms with different load combinations and clock pulse widths Waveforms with clock pulse width=50µs, Row transfer time=100µs ØI1 ØI2 ØI3 Figure 6.3: Image area clock triplet, three loads Figure 6.3 shows the waveforms we expect to see with the PFIS detector system when using one clock board, where each clock driver circuit has three loads as defined in section 3. The datasheet typical clock pulse width of 50µs is used. This looks acceptable, but in fact contravenes some of the specifications for image area clock rise time (T r ) and clock overlap (T o ) as defined in the CCD44-82 data sheet. The results are discussed in detail in section 4.3 and section 5.

64 SALT-3196AE0001 Detector Document 24 Figures 4 through 7 show expanded views of one clock waveform for each case of one load through four loads, with rise/fall time measurements. Figure 6.4: One load (store area of one frame-transfer CCD) T r : 5µs; T o : 14µs: this is within the E2V specifications

65 SALT-3196AE0001 Detector Document 25 Figure 6.5: Two Loads (one frame transfer CCD) T r : 13µs; T o : 14µs: this does not comply with the E2V specification of T r < 0.5 T o.

66 SALT-3196AE0001 Detector Document 26 F Figure 6.6: Three loads (as for PFIS detector package) T r : 28µs; T o : 14µs: this does not comply with the E2V specification of T r < 0.5 T o.

67 SALT-3196AE0001 Detector Document 27 Figure 6.7: Four loads (two frame transfer CCDs) T r : 33µs; T o : 14µs: this does not comply with the E2V specification of T r < 0.5 T o.

68 SALT-3196AE0001 Detector Document Waveforms with clock pulse width=25µs, Row transfer time=50µs Figure 6.8: image area clock triplet, two loads Notes: 1. Clock pulse width 25µs. 2. Clock Triplet time ~55µs including fall time of last clock edge. 3. Clock overlap is ~8.3µs

69 SALT-3196AE0001 Detector Document 29 Figure 6.9: Four loads (two non-frame-transfer CCDs) Note : The rise time is greater than the pulse width, the clock pulse never reaches the high voltage, thus the indicated rise time is unreliable.

70 SALT-3196AE0001 Detector Document 30 Figure 6.10: Detail of waveform in Figure 6.8. Two loads T r : 17µs; T o : 8µs: this does not comply with the E2V specification of T r < 0.5 T o.

71 SALT-3196AE0001 Detector Document 31 Figure 6.11: Detail of waveform in Figure 6.9. Four loads T r : unreliable; T o : 8µs: this does not comply with the E2V specification of T r < 0.5 T o.

72 SALT-3196AE0001 Detector Document Tabulated Results Table 1: Clock Pulse width T w = 50µs; Triplet time T i = 100µs Loads Rise Time T r (µs) Fall Time(µs) Overlap T o (µs) Comments T r <0.5 T o. In spec T r >0.5 T o. Out of spec T r >0.5 T o. Out of spec T r >>0.5 T o. Out of spec. Table 2: Clock Pulse width T w = 25µs; Triplet time T i = 50µs Loads Rise Time T r (µs) Fall Time(µs) Overlap T o (µs) Comments T r >0.5 T o. Out of spec. 4 Unreliable T r >>0.5 T o. Out of spec. 6.5 Discussion Private communication with Dr Paul Jorden of E2V indicates that reducing clock pulse width and hence row transfer time is acceptable for small signals so long as the amplitude does not reduce (i.e. rise/fall time greater than width). Figures 9 & 11 show a condition where the rise time for four loads exceeds the pulse width of 25µs making the oscilloscope calculated rise/fall time numbers unreliable. The PFIS detector preliminary design documentation used a row transfer time of 50µs for readout time calculations, giving total row transfer time for full frame readout of: 4102 x 50µs = 205ms The E2V data sheet for the CCD4482 recommends the following:

73 SALT-3196AE0001 Detector Document 33 Table 3: E2V datasheet values (all times in µs) Minimum Typical Maximum Row transfer T I Pulse width T w Rise time T r T o Overlap T o T i According to the datasheet, only one of the tabulated test results is acceptable that of one load with 50µs pulse width, as shown in Figure 6.4. However, many groups use the SDSU controller to drive E2V 2Kx4K detectors, most configure their systems as one detector per clock driver output, equating to the two-load test described above. Thus we can safely assume that the two-load option gives acceptable performance in spite of not conforming to the E2V datasheet requirements. In the case of the PFIS detector system, to comply with the T r <0.5 T o specification using one clock board, the clock pulse width will have to be extended as follows: Three load T r : 28µs Overlap required: 2 x T r = 56µs Thus row transfer time T i : 56/0.2 = 280µs Total row transfer time for image readout: This is unacceptably long. 280µs x 4102 = 1.15 seconds However, from discussions with Dr Paul Jorden it seems that the E2V specifications are very conservative, and applicable to large signal levels. 6.6 Conclusion/Recommendation To guarantee best performance (fastest row transfer times in readout) the PFIS detector system must use the large SDSU controller crate with three clock boards. Use of the small SDSU controller crate will result in slower row transfer times due to the SDSU clock driver board limitations when driving high capacitance loads. I estimate that the reduced performance will be approximately 100µs/row = 410ms image transfer time for high signal levels. It should be possible to achieve satisfactory performance with faster row transfer times for small signal levels this is difficult to quantify without more exhaustive tests.

74 SALT-3196AE0001 Detector Document 34 A decision must be made on the trade-off between the best performance achievable with the larger/heavier controller and slower row transfer times obtained with the standard size controller crate. The following information is pertinent to this decision: Mass/size comparison Small crate Large crate Small PSU Large PSU Mass (Kg) Length (mm) Width (mm) Height (mm) Note: these dimensions do NOT include the volume required for cabling/connectors. Cost comparison Small crate system Large crate system $29200 $ Note: These prices are to be confirmed Small crate system details: 1 x ARC-70 6-slot housing $ x ARC?? Large power supply $ x ARC MHz timing board $ x ARC-50 utility board $ x ARC-45 differential video board $ x ARC-30 clock board $ x ARC MHz PCI board $ x 100m optical fibre no charge 1 x watercooled heat exchanger $200 TOTAL $29200

75 SALT-3196AE0001 Detector Document 35 Large crate system details: 1 x ARC-?? 12-slot housing $ x ARC?? Large power supply $ x ARC MHz timing board $ x ARC-50 utility board $ x ARC-45 differential video board $ x ARC-30 clock board $ x ARC MHz PCI board $ x 100m optical fibre no charge 1 x watercooled heat exchanger $200 TOTAL $ Sub-Systems Controller The sub-systems controller consists mainly of a multi-function analog/digital controller originally developed by the SAAO for the InSb infrared camera. Communication from the PFIS computer to the sub-systems controller is via the SDSU controller and its RS- 232 port on the utility board. All connections between the SDSU controller and the subsystems controller are optically isolated. The sub-systems controller and the sub-systems it controls are powered from the sub-systems power supply. The sub-systems controller controls the following PFIS sub-systems: 7.1 Temperature Monitoring The sub-systems controller can monitor two temperature points inside the cryostat. The one temperature point will be on the cold plate and the other TBD2. The sub-systems controller will also control the cold plate heater. 7.2 Varian Ion Pump A Varian Ion Pump unit is used to maintain the cryostat vacuum integrity. The ion pump will also function as a vacuum gauge to allow long-term monitoring of the state of the cryostat vacuum to facilitate maintenance planning. On/Off control of the ion pump and the acquisition of the vacuum reading from the ion pump will be via the sub-systems

76 SALT-3196AE0001 Detector Document 36 controller. The sub-systems controller will also be able to verify the on/off state of the ion pump. 7.3 EMI Protection of Signals The control signals to and from the sub-systems controller and the sub-systems it controls might be susceptible to electromagnetic interference (EMI). The level of interference will be very low as the length of the cables carrying these signals will be short (less than 2 meters) and the control signals will be of a low frequency. To reduce the level of interference all cables carrying control signals between the sub-system controller and the sub-systems it controls will be screened. As an added measure of protection the option of either low-pass filters and/or transient suppressors on the control lines or a de-bounce algorithm in the sub-system controller software controlling the sub-systems will be taken under advisement. 8 Mosaicing The PFIS detector subsystem is based on three E2V CCD44-82 CCD chips mounted on a common cold plate. Mosaicing consists of: Measuring and correcting the co-planarity of the three CCD detector chips. Measuring and correcting the row offset between adjacent CCD chips. Measuring and correcting the degree of rotation between adjacent CCD chips. This document describes the plan for mosaicing the PFIS detector chips and draws heavily on the document CCD Mosaicing by W.P.Koorts, SAAO. 8.1 Functional Requirements CCD mosaicing involves the mounting two or more CCDs such that their detection surfaces are co-planar between individual CCDs as well as to a reference (mounting) plane. It is also necessary to align the rows between individual CCDs and also adjust the amount of rotation between CCDs to get the columns parallel to each other. CCDs are typically mounted on an Invar cold plate which acts as both a thermal sink for cooling as well as a stable platform for holding the mosaic. Each CCD is mounted on three pedestals that are shimmed to the exact height to get the CCDs co-planar at some fixed distance above the cold plate. The reference plane can be either the mounting surface of the cold plate or a reference surface on an attached mounting jig used to accurately position the mosaic in the cryostat.

77 SALT-3196AE0001 Detector Document Mosaicing a Detector System The first requirement is a clean room temperature controlled to 20C to ensure the cleanliness of the CCDs. An Electrostatic Discharge (ESD) station is necessary to protect the CCDs from potentially destructive static electricity. The measuring equipment consists of: A stable surface (granite slab) and frame to support cold plate and measuring equipment. An automated X-Y Positioning Table calibrated in the Z direction. A Laser Displacement Sensor capable of measurements < 1 micron for mosaic flatness measurements. A suitable imaging system for row offset and rotation measurements and adjustments. The mosaicing process consists of accurately measuring a matrix of points on the 3 CCDs mounted on the cold plate. The measurements obtained are analysed to obtain the mean plane of each CCD. The CCDs are then adjusted by precision grinding or lapping of the shims to the exact size required to get the CCDs coplanar. 8.3 Mosaicing Specifications CCD44-82 Physical Dimensions The E2V CCD44-82 has 4k +6 rows of light sensitive pixels. ie = 4102 pixels Detector "height" (sensitive pixels) is therefore 4102*15micron = 61.53mm Top inactive edge spacing is nominally 0.16micron Bottom inactive edge spacing is nominally 5.0mm Total CCD physical height = 61.53mm mm+5.0mm = 66.53mm The "width" image area per CCD is 2048*15micron = 30.72mm Left and right inactive edge spacing per CCD is nominally 0.5mm The gap between packages is nominally 0.5mm Total physical "width" = 93.16mm

78 SALT-3196AE0001 Detector Document E2V CCD44-82 Flatness specification The silicon flatness specification obtained from E2V is ±10 micron. ie. 20 micron peak-to-valley. E2V are confident that they can deliver CCDs that are flat to ±7.5 micron ie. 15 micron peak-to-valley E2V CCD44-82 Reflectivity With astro-broadband coating surface reflectivity at 670nm (red) is about 10% Specifications for the assembled PFIS mosaic: Required Flatness: ± 10 micron for the entire mosaic. Maximum Row offset: 6 pixels (15 microns/pixel *6 = 90 microns) Column Alignment: ±5 pixels in Mosaicing Procedure A granite slab supports the XY table. A displacement sensor mounted on the XY table measures vertically upward to either a reference surface or the mosaiced CCDs supported by the stable frame. The XY table is characterized in Z for all XY positions of interest using a reference surface mounted in the frame at the nominal sensing distance of 30mm. The mosaiced CCDs in their mounting jig are then positioned in the stable frame and the Z distance to each of the CCDs is measured at a number of XY positions. Distance measurements are also taken to the three reference mounting pads on the cold plate mounting jig. On a 2k x 4k CCD E2V measures 9 points, one in the center, one in each corner and one between each of the four corner points whereas ESO typically measures 100 evenly distributed points. The mean plane of the cold plate, represented by the three reference pads as well as the mean plane of each CCD, can now be obtained by software analysis of the data. From this information the precise shim lengths can be calculated. By precision grinding and measuring with a laser micrometer the 9 CCD shims can be adjusted to get the three CCDs coplanar with each other and with the reference plane.

79 SALT-3196AE0001 Detector Document 39 The measurement and shimming process may have to be done iteratively to prevent overshooting the required position. 9 List of TBC Issues TBC1 - TBC2 - TBC3 - TBC4 - TBC5 - TBC6 - TBC7 - Readout noise of 3 and 5 e - /pix at readout rates of 100 and 333 khz Pixel readout overhead for 2x2 compared with 1x1 prebinned readout Readout rates in the range khz Pixel skip times are 1.0 µsec/pix Additional overhead for each increment in prebinning is 1.0 µsec Number of windows allowed Very high speed spectroscopic performance TBD1 - TBD2 - Base gain of electrons/adu Second temperature point inside cryostat

80 SALT-3196AE0002 CCD Handling Procedures Document 1 Southern Africa Large Telescope Prime Focus Imaging Spectrograph SAAO Detector Subsystem SALT-3196AE0002: CCD Handling Procedures SAAO PFIS Detector Subsystem Team: Dave Carter Luis Balona Etienne Bauermeister Geoff Evans Willie Koorts James O Connor Darragh O Donoghue Faranah Osman Stan van der Merwe Issue February 2003

81 SALT-3196AE0002 CCD Handling Procedures Document 2 Issue History Number And File Name Person Issue Date Change History 3196AE0002 CCD Handling DBC Nov 2002 First draft leading up to PFIS Procedures Issue 1.0.doc CDR. 3196AE0002 CCD Handling Procedures Issue 1.1.doc DBC Feb 2003 Final draft for PFIS CDR. Table of Contents 1 Scope Introduction Delivery acceptance Procedure Installation Procedure Removal Procedure Specific Procedures for PFIS CCDs Electrostatic Discharge Damage Prevention Procedures Scope This document outlines the procedures followed at SAAO when taking delivery of new CCD detectors and the subsequent handling procedures for insertion/removal from cryostat/camera systems. It is presented as part of the Critical Design Review Documentation for the SAAO detector package for PFIS. Note that the procedure as written is generic there is a special extra section referring to the SALT CCDs. 2 Introduction CCDs are classified as both ESD (electrostatic discharge) sensitive and clean thus they must only be handled whilst observing ESD precautionary procedures and in a clean environment such as the class 100 laminar flow bench in the CCD cleanroom. The detectors are normally received individually boxed in durable plastic or metal transport containers, mounted in a zero insertion force socket, with all connection pins shorted together. This container is sealed in a special electrostatic protection polyethylene bag. The whole is packed in a normal cardboard box with some form of impact protection bubblewrap etc.

82 SALT-3196AE0002 CCD Handling Procedures Document 3 3 Delivery acceptance Procedure 3.1. Open the cardboard packaging and check identifying marks/labels on the plastic transport container to establish type and serial numbers, and check these against the delivery documentation Store the device as is (unopened) in the CCD development lab until such time as it is needed to connect into the camera system. (There is a possibility that the incorrect device may have been packed in the transport case, although we have never experienced this) The alternative to 3.2. above is to open the transport case to check the device serial number then close and seal the package again for storage. This would be done working at the electrostatic protected area (EPA) at the laminar flow bench in the CCD lab clean room. (If the serial number is inscribed on the device at all some suppliers merely mark the underside of the device with a marker pen) It has happened that we have received a transport package where the CCD has come loose from its ZIF socket and rattles around in the box. In such circumstances the supplier is contacted and usually the device is returned unopened for checking. 4 Installation Procedure 4.1. A CCD camera system is prepared for use with the detector. This process involves assembly and testing in all respects static as well as dynamic tests of circuits, wiring, software, voltage levels etc, including tests with engineering and electrical sample grade detectors (if available), to ensure as far as possible that the system will not damage the detector when it is finally plugged in When it is necessary to open the packaging to transfer the device to the pre-tested system, this is done in the CCD lab clean room at the laminar flow bench. Full Electrostatic Discharge precautions (see below, section 7) are observed. If not already done (see 3.3 above), at this time the device serial number is checked against the number on the transport case. Note that there is little point in checking for mechanical damage other than looking for obvious signs such as bent connection pins etc. Most CCD damage, being due to static discharge, is invisible to the naked eye The cryostat is closed up and transported to the CCD test area The camera system is switched on and a small number of initial tests are performed at ambient temperature to establish whether the device responds to light in a sensible fashion If step 4.4. was successful, the cryostat is evacuated and cooled, and a series of more detailed tests are performed to establish whether the device performs according to specifications. If there are discrepancies these are reported to the manufacturer and reasons/solutions are worked out in conjunction with the manufacturer. In extreme cases a device may be packaged up and returned to the manufacturer for re-testing.

83 SALT-3196AE0002 CCD Handling Procedures Document 4 5 Removal Procedure The following procedure is observed if the CCD has to be removed from a cryostat/camera system: 5.1. The cryostat is warmed up so that all internal parts are at ambient temperature The vacuum is released using clean dry nitrogen gas obtained by bleeding the boil-off from a pressurized LN2 dewar if available, else obtained from the high purity H.P. nitrogen gas supply in the CCD lab Further work is done in the EPA following the Electrostatic Discharge Damage Prevention Procedures as defined below (section 7). Removal is the reverse of the installation procedure described. 6 Specific Procedures for PFIS CCDs 6.1. After checking device type/serial numbers against the delivery documentation the CCDs will be stored in a locked cabinet in the office of the head of electronics The camera system (cryostat and associated controller/electronics) will be tested with electrical sample devices obtained from Marconi/E2V to establish correct setup and operation including initial adjustments to the cold plate temperature control system The mosaiced cold plate assembly will be transferred to the cryostat while working at the electrostatic protected area at the laminar flow bench in the CCD lab cleanroom. 7 Electrostatic Discharge Damage Prevention Procedures For inserting CCDs into cryostat systems. Note that this is a generic procedure, it does not include specifics associated with handling Marconi/E2V CCD44-82s, which have handling tools associated with them such that the actual device package is not touched by the operator The procedure is carried out in a certified class clean room at the class 100 laminar flow bench. An air blower de-ionizer is installed in the L.F. bench The operator works in the EPA fitted to the laminar flow bench. This consists of a conductive mat on the work surface, a conductive floor mat, a wrist strap and conductive gloves. All these components are connected to a central earth point which in turn is connected to mains earth. The installation has a test device for validating the correct performance of the wrist strap and conductive gloves The cryostat is placed on the conductive mat and the cryostat body and 0v rail of the associated circuitry are connected to the central earth point. At this stage all circuit electrical connections to the CCD socket are shorted together and to 0v by an integral shorting plug/mechanism.

84 SALT-3196AE0002 CCD Handling Procedures Document The CCD transport container is placed on the conductive mat and opened. The earth plane of the container is connected to the central earth point. At this stage all items are defined at the same (earth) potential The CCD is removed from the transport case, the mechanism/material shorting all pins together is removed**, and the CCD is mounted in the cryostat and plugged in The circuit shorting plug/mechanism is disconnected to prepare the system for switch on. ** Some CCDs (such as the Marconi/E2V devices) are transported with conductive rubber squashed over the pins as a shorting mechanism, instead of a ZIF socket.

85 SALT-3197AE0001 Cryostat Document 1 Southern African Large Telescope Prime Focus Imaging Spectrograph SAAO Detector Subsystem SALT-3197AE0001: Cryostat Document SAAO PFIS Detector Subsystem Team: James O Connor Etienne Bauermeister Dave Carter Geoff Evans Willie Koorts Darragh O Donoghue Faranah Osman Stan van der Merwe Issue March 2003

86 SALT-3197AE0001 Cryostat Document 2 Issue History Number And File Name Person Issue Date Change History SALT-3197AE0001 Cryostat Nov 2002 First pre-pfis CDR draft Issue 2.0.doc SALT-3197AE0001 Cryostat Issue 2.4.doc Feb 2003 Truly the final CDR draft SALT-3197AE0001 Cryostat Issue 2.5.doc Mar 2003 Definitely and truly the final CDR draft! Table of Contents 1 Scope Overview Requirements Mosaicing Thermal Vacuum Final Design Structure Field Lens Thermal Control System Detector Assembly Detector Interface Vacuum System Electrical Connections Mass Properties Fabrication Components COTS items Cryostat body Surface finishes Risks Thermal Vacuum...20

87 SALT-3197AE0001 Cryostat Document Mechanical damage Risk Management...20

88 SALT-3197AE0001 Cryostat Document 4 1 Scope This document describes the mechanical design rationale of the Final Design for the Cryostat as required for the Prime Focus Imaging Spectrograph (PFIS) Instrument. NOTE: This is the final design configuration and the only entities that might change are the mounting arrangement of the field lens to the vacuum wall and the internals of the plug box containing the connectors and pre-amplifier boards. 2 Overview In this instrument the Cryostat has its function of housing the detector modules and the carrier for the field lens (which also forms the window of the Cryostat). 3 Requirements 3.1 Mosaicing Requirements The individual CCD s have the following specifications on the focal plane: Surface undulation 10µm Peak to valley. The Optical Alignment requirements are as follows: Tip/tilt of average focal plane: 20 µm of one long edge compared to the other and 10 µm on the short edges. Deviation in focal plane orientation between CCD s: 1 arcmin. Alignment of pixel columns and rows: 6 pixels in 4096 (5 arcmin) Options It has been decided to do the mosaicing at SAAO for the following reasons: a. SAAO will have to have an ability to maintain the detectors for SALT and as such needs to develop a mosaicing facility. b. Experience gained on SALTICAM will minimize the risks on PFIS mosaicing. (The only reasons for having the SALTICAM mosaicing done at E2V were time and manpower constraints.)

89 SALT-3197AE0001 Cryostat Document Thermal The temperature requirements of the CCD s are as follows: Control temperature: 160 K Peak to valley fluctuation: less than 0.5 K Cool down time: less than 4.5 hours 3.3 Vacuum The vacuum in the cryostat will have to be maintained to less than 10-4 Pa. 4 Final Design 4.1 Structure The structure of the cryostat consists of 3 main parts, i.e. the front plate, the main body and the interface plate for mounting the cryostat to the camera flange Front plate The front plate (Fig. 1) has the functions of: a. Carrying and constraining the field lens in place. b. Serving as mounting base for the detector assembly. c. Attaching the Cryostat to the interface plate. The window is carried in a stainless steel clamp. Silicon RTV is used to bond the lens to the clamp in a similar fashion as lenses are bonded into cells. The clamp will pull the lens assembly down onto an O-ring to form the vacuum seal (Fig. 2). Locating pins will determine the centering of the lens to the detector optical center. Tip/tilt adjustments will be possible with shims between the lens clamp and the front plate of the Cryostat. The detector assembly bolts to inside of the front plate in such a manner that the detector center will be on axis with the center of the field lens. The inside face of the plate will also serve as the reference face to which the focal plane will be positioned. Fig 3 depicts the inside of the complete front plate assembly. The front plate assembly also serves as attachment points (Fig 4) for the Cryostat to the interface flange (Fig 5). This design will enable removal and replacement of the Cryostat without upsetting the optical alignment.

90 SALT-3197AE0001 Cryostat Document 6 Figure 0: GENERAL VIEW OF CRYOSTAT

91 SALT-3197AE0001 Cryostat Document 7 Cold Braid Attachment Heat Shield Tip/Tilt Adjuster Guide Bracket Front Plate Lens Clamp Figure 1: COMPLETE FRONT PLATE ASSEMBLY Front Plate O-Ring Lens Clamp Shim Gap Field Lens RTV Figure 2: SCHEMATIC OF WINDOW AND CLAMP

92 SALT-3197AE0001 Cryostat Document 8 Front Plate Flexure Connection Board Cold Plate Pedestal (Top Shield) Heat Shield Flexure Clamp Thermal Manifold Pedestal (Side Shield) Pedestal Figure 3: FRONT PLATE ASSEMBLY (INTERNAL) Front Plate Guide Bracket Tip/Tilt Adjuster Guide Shims Hold Down Flange Figure 4: ATTACHMENT POINTS

93 SALT-3197AE0001 Cryostat Document 9 Guide Pedestal Interface Flange Hold Down Bolts Figure 5: INTERFACE FLANGE Main body The main body has the functions of: a. Providing space for the detector package. b. Carrying the cold end. c. Carrying the plug box containing the connectors and pre-amplifier. d. Mounting of the Ion pump and vacuum valve. Fig. 6 shows an exploded view of the cryostat and Fig. 7 and Fig. 8 show cross sectional assembly drawings.

94 SALT-3197AE0001 Cryostat Document 10 Vacuum Valve Ion Pump Assembly Cold End Assembly Main Body Plugs End Cap Plug Box Front Plate Assembly Interface Assembly Figure 6: EXPLODED VIEW Figure 7: CROSS SECTION 1

95 SALT-3197AE0001 Cryostat Document Interface Flange Figure 8: CROSS SECTION 2 Fig. 5 depicts the interface flange. This flange is permanently attached to the camera flange, but has the facility for rotational adjustment during installation. The cryostat is connected to the interface plate in such a manner that it can be adjusted for tip/tilt, but no rotation will be possible. This arrangement will facilitate removal/replacement of the cryostat without disturbing the optical alignment Structural Analysis The FEA analysis for Salticam indicated that no undue flexures or stresses were present in the thin area (5 mm wall thickness) of the lid. The lid on the PFIS Cryostat is substantially thicker (10 mm minimum) with a wall/thickness of 17 mm where the field lens is located. The remainder of the structure is a clone of the Salticam design. For these reasons it was decided not to do a FEA analysis for PFIS. 4.2 Field Lens The field lens is used as window to the cryostat as well. A flow of dry air is provided to prevent the front surface from frosting up. Shims will facilitate limited tip/tilt adjustment, but decenter and rotation will be locked by the mounting arrangement. Fig. 9 depicts the mounting arrangement.

96 SALT-3197AE0001 Cryostat Document 12 Front Plate Field Lens Lens Bracket Locating Pin Cap Screw 4.3 Thermal Control System Figure 9: FIELD LENS MOUNTING A great deal of time and effort was devoted to the design of SALTICAM to minimizing the heat load as well as ensuring a good temperature distribution across the detector surface. This experience and knowledge was applied to the design of the PFIS Cryostat The cold path will consist of the following elements (Fig. 10): a. Heater elements. b. Temperature sensors. c. Thermal manifold. d. Cold braid. e. Junction. f. Cold end. g. Trap. h. Compressor/heat exchanger.

97 SALT-3197AE0001 Cryostat Document 13 Figure 10: SCHEMATIC OF THERMAL SYSTEM The thermal manifold is designed such that the most even temperature distribution through the CCD Invar package is ensured. This is achieved through contacting on the cold plate and with cold blocks directly onto the underside of the package in appropriate places. (Fig. 11) Heater elements and temperature sensors are attached to the manifold such that a temperature fluctuation of less than 0.5 K can be achieved. A cold braid will lead from the manifold to the junction that is integral to the cryopump end (Fig. 12). The final adjustment to reach the required stabilization temperature of 160K on the focal plane will be made by reducing or increasing the conductivity of this cold braid. The arrangement is such that it will facilitate easy connection/disconnection upon assembly/disassembly of the cryostat.

98 SALT-3197AE0001 Cryostat Document 14 Cold Plate Top Clamp Block Thermal Spider Bottom Clamp Block CCD Figure 11: COLD BLOCKS ONTO CCD

99 SALT-3197AE0001 Cryostat Document 15 Cryotiger Heater Recesses Cold Braid Attachment Thermal Manifold Cold Braid Attachment Figure 12: COLD END ASSEMBLY Heat Load By polishing the inside of the cryostat walls and installing a gold plated heat shield assembly the thermal loading was substantially reduced. Heat load: Radiative load on surface other than focal plate Heat generated by amplifiers on chips Heat generated by pixels on chips (during readout) Radiative heat on detector surface Conductance through mechanical connectors Conductance through electrical wiring Total heat load 90 mw 150 mw 750 mw 2400 mw 150 mw 120 mw 3660 mw 3,7 W

100 SALT-3197AE0001 Cryostat Document Temperature Distribution Following the Salticam analysis it can be said the temperature distribution in the manifolds and surface of the chips are well within acceptable limits. 4.4 Detector Assembly The assembly consists of the following: 3 x CCD s 1 x cold plate 4 x G10 flexures 4 x aluminum pedestals 1 x heat shield assembly Fasteners and clamp plates Pedestal Flexure Flexure Clamp Cold Plate Figure 13: FLEXURE MOUNTING OF COLD PLATE TO PEDESTALS

101 SALT-3197AE0001 Cryostat Document 17 Four G10 flexures carry the CCD/cold plate assembly (Fig. 13). This material has good flex as well as thermal properties. Aluminium pedestals are used to mount the flexures to the front plate. A set of thermal shields gold coated for minimum radiation encapsulate the assembly except for the focal plane and where the cold plate attachment points protrude through (Fig. 14). Top Shield Side Shield Pedestal Mounting Method Figure 14: THERMAL SHIELDS a. The CCD s are mounted on an Invar cold plate 6 mm thick. The standard Marconi method of attachment and alignment is used. b. The focal planes of the CCD s will be aligned to a dedicated bolt on bracket to give the zero reference for the planes. This bracket is then utilized to mount the detector assembly to the front plate of the cryostat. The face of the front plate serves as the reference for the offset of the focal planes to the back plane of the lid (Fig. 15). This method removes any dimensional criticality from the cold plate (except for flatness).

102 SALT-3197AE0001 Cryostat Document 18 Reference Plane Focal Plane Front Plate Field Lens Figure 15: OFFSET OF FOCAL PLANE TO REAR OF FRONT PLATE 4.5 Detector Interface The interior face of the front plate will be used as the mounting and reference plane of the detector package. The cold plate/ccd assembly is attached to the inner mounting pedestals with G10 flexures. The method of assembly will be as follows: a. The four pedestals will be bolted to the front plate. b. The cold plate assembly (with the gauging bracket in place) will be placed in position over the inverted lid. c. Once it is established that the detector assembly is in the correct location, the G10 flexures will be attached and tightened. d. After checking the installation the gauge bracket will be removed. e. Following this the electrical connections will be made and the front plate screwed down in position. f. Once the front plate is in position the cold path will be connected through an aperture in the body of the cryostat. 4.6 Vacuum System A Varian 2 l/s ion pump (with noble gas capability) is used to maintain vacuum over an extended period. An activated charcoal cryopump (getter) is also installed on the cold end (Fig. 16). The vacuum will be monitored via the integral gauge reading from the ion pump controller. Viton o-rings will be used on all sealing surfaces, except for the bonding of the window into the lid. It is not foreseen that metallic sealing rings will be required on any of the sealing surfaces. In order to minimize molecule attachment to interior surfaces, most of the internal surfaces will be electro-polished, including the surfaces that will have gold coatings applied to them.

103 SALT-3197AE0001 Cryostat Document 19 All internal holes and jointing surfaces are designed such that the potential for molecules traps are minimized (bleed holes and shaved threads). Cryopump Cryotiger Figure 16: CRYOPUMP ON CRYOTIGER 4.7 Electrical Connections There are three electrical connectors going through the vacuum wall for the CCD s. These connectors are of the CANON type and well suited to HVAC environment. The connectors for the CCD s have an external plug box enclosing them, also containing the preamp boards, external connectors to the SDSU II controller and shorting plug arrangement. 5 Mass Properties The following mass properties are calculated for the cryostat: Front plate and window: Cryostat body: Detector assembly: Cold end Adjustable Interface assembly Vacuum system Connectors, wiring and plug box Total Mass 1.15 kg 1.60 kg 0.90 kg 1.75 kg 1.35 kg (not required at PDR) 0.85 kg (0.75 kg Vac Pump not foreseen at PDR) 0.85 kg (0.5 kg Plug Box not foreseen at PDR) 8.50 kg The above does not make provision for the wiring looms going to the cryostat, nor the cooler hoses.