(12) Patent Application Publication (10) Pub. No.: US 2013/ A1

Transcription

1 US 2013 O161725A1 (19) United State (12) Patent Application Publication (10) Pub. No.: US 2013/ A1 PARK et al. (43) Pub. Date: Jun. 27, 2013 (54) SEMIONDUTOR MEMORY DEVIE AND Publication laification METHOD OF MANUFATURING THE SAME (51) Int. l. HOIL 29/792 ( ) (75) Inventor: Yong Dae PARK, Seongnam-i (KR): HOIL 2L/2425 ( ) Ga Hee LEE, Suwon-i (KR) (52) U.S. l. USP /324; 438/525; 257/E29.309; (73) Aignee: SK HYNIX IN., Icheon-i (KR) 257/E21473 (57) ABSTRAT A emiconductor memorv device include conductive film 21) Appl. No.: 13/613,653 ry (21) Appl. No 9 and inulating layer alternately tacked on a Subtrate, Sub tantially vertical channel layer penetrating the conductive (22) Filed: Sep. 13, 2012 film and the inulating layer, multilayer film including a charge torage film interpoed between the conductive film (30) Foreign Application Priority Data and the Subtantially vertical channel layer, and a firt anti diffuion film formed on etched urface of the conductive Dec. 21, 2011 (KR) O film d Ox X 8xx xxxx xxxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx XXXXXXXXXXXXXXXXXXXX XXXXXxxxxxx xxxxxxxx xxxxx XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 3

2 Patent Application Publication Jun. 27, 2013 Sheet 1 of 15 US 2013/O A1 FIG.1 enote xxxx xxxx XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX xxxxx xxxx xxxx xxxxxx xxxx xxxxxx xxxxx 44S4 4ay aaaay aaa aa 4.

3 Patent Application Publication Jun. 27, 2013 Sheet 2 of 15 US 2013/O A SSX xxx XXXXXxxxx KXXXXXXXX XXXXXXXXX -- KXXXXXXXX: -Mc XXXX XXXXX kxxx) XXXX foretore i O F XXXXX X: XXXX XE.X.... "......'.... (XXXX XXXX XXXXX XXXX XXXX XXXX X. Xxxxx X. xxxx XX : x : 8 X X x : 8 X 8 AYS 25 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -XXXXXXXXXXXXXXXXXXaXXXXXXXXXXXXXXXXXXX X XXXXXXXXXXXXXXX S XXXXXXXXXXXXXXX XXXXXXXXXXXXX S XXXXXXXXXXXXXX S X XXXXX xxx XXXXXXXXXXX SXXaXXXXXX XXXXXXXXXXX XXXX XXXXXXXXXXX XXXXXXXXXX S XXXX Xx8x:. XXXXXXXXXXX xxxxx xxxxx K XXXXXXXxxxx KXXXXXXXXXXX xxxxxxxxxxx XXXXXXXXXX AWAS XXXXXXXXXXXX SxXXXXXY XXXXXXX-See XXXXX: XXXXXXXXXXXXX 3XX S xxxxxxxxxxxxxxxx {XXXXXXXXXXXXX S XXXXXXXXXXXXXXXXX-Ser-XXXXXXXXXXXXXXX. XS A

4 Patent Application Publication Jun. 27, 2013 Sheet 3 of 15 US 2013/O A1 FIG i : X A X. 8. XX A? 8. X S S. (x A. al X. 8 a' 8. : ººººººººººººººº 8???????? 8 XXXX S xxx ( Ty SS ( SS X. E

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9 Patent Application Publication Jun. 27, 2013 Sheet 8 of 15 US 2013/O A1 FIG.7E A x: X x: x: x: I 109 t xxxx Ex e B X: fic S circk 1. l S 3X X r Emitrict - Fig E. XXXXXXXXX KXXXXXXXXXXXXXX KXXXXXXXX XXXXXXXXX XXXXXXXXXXXXXXX {XXXXXXXX x, XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX N ex -105 XXX: {XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX aaaa ra gaaaa. Sa

10 Patent Application Publication Jun. 27, 2013 Sheet 9 of 15 US 2013/O A1 FIG.7F tilted on implantation tilted on implantation XXXXXXXX x XXXX-XXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXX XXX: XXXXXXXXXXXXX: x-u-113 XXXxxxxx at 15 -N : 1. XXX. ExXX) X """." W l a: eee. e a wa greer retreeterror rerette fir : l X i * - more r.. areae r xxxxxx PSXXXXXXXXXXXXX xxxxxxx : 1- w S "Omo" root 15: 109 reee reeerter erie l XXX e XXXXXX KXXXXXXXXXXXXXX KXXXXXXXX XXXXXX XXXX XXXXXXXXXXXXXXX XXXXXXXXX {XXXX XXXXX 8XXXX {xxxx ext XX-XX XXXXX {XXXX XXXX XXXXX KXXXX XXXXX {XXXX XXXXX XXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XX ee: 121 R 123 XXX O7 xxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxxxx XXXXXXXXXx: 105 Xxxxxxxx

11 Patent Application Publication Jun. 27, 2013 Sheet 10 of 15 US 2013/O A1 FIG.7G SS XXX: 125 XXXXXX KXXXXXXXXX ex XXXXXX XXXXXXX KXXXXXXXXX XXXXXXXXXX X {XX XXXXXXXXXX 1 O 9 ExxxxXXXXX x KXXXXXXXXXX xxxx o xxxx xxx XXXXXXXXX aaaaaaaaaar X aaraavara 3. S X.. N-109 K : X. RexXxxxx XXXXXXXXX KXXXXXXXXXXXXXX XXXXXXXXXXXXXXX, KXXXXXXXX xxxx Af XXXXXXXXX {XXXXXXXXXXXXX: exx Syway e XXX XXX.. x3 12. r. R 1) XXXXX.. M **Sea- X Aw XXXX Y XXXXX rt re XXX XXXX XXXXX XXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ex XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

12 Patent Application Publication Jun. 27, 2013 Sheet 11 of 15 US 2013/O A1 * 103 O

13 Patent Application Publication Jun. 27, 2013 Sheet 12 of 15 US 2013/O A1 FIG XX ex X 8 XX S $38 x x XXX ix X. 2

14 Patent Application Publication

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16 Patent Application Publication Jun. 27, 2013 Sheet 15 of 15 US 2013/O A1 FIG.8 102

17 US 2013/O A1 Jun. 27, 2013 SEMONDUTOR MEMORY DEVIE AND METHOD OF MANUFATURING THE SAME ROSS-REFERENE TO RELATED APPLIATION 0001 Priority i claimed to Korean patent application number filed on Dec. 21, 2011, the entire dicloure of which i incorporated herein by reference in it entirety. BAKGROUND Technical Field 0003 Variou embodiment relate generally to a emicon ductor memory device and a method for manufacturing the ame, and to a emiconductor memory device adaptive to enhance operational characteritic and a method for manu facturing the ame Related Art In order to increae a degree of integration of a emiconductor memory device, a ize of a memory cell i required to be reduced, but it i increaingly difficult to reduce the ize. To thi end, a emiconductor memory device having a three-dimenional (3D) tructure in which memory cell are tacked ha been developed. In particular, in cae of a flah memory device, a memory array i formed to have variou type of 3D tructure A a memory array i formed to have a 3D tructure, a voltage application cheme and an operating cheme, a well a operational characteritic, are changed. Thu, a manufacturing method and tructure for preventing a degra dation of operational characteritic i required. BRIEF SUMMARY 0007 Variou embodiment relate to a emiconductor memory device and a method of manufacturing the ame capable of enhancing operational characteritic A emiconductor memory device according to an embodiment include: conductive film and inulating layer alternately tacked on a Subtrate; Subtantially vertical chan nel layer penetrating the conductive film and the inulating layer; multilayer film including a charge torage film inter poed between the conductive film and the ubtantially vertical channel layer; and a firt anti-diffuion film formed on etched urface of the conductive film An operating method of a emiconductor memory device according to an embodiment include: alternately and repeatedly tacking firt inulating layer and firt conductive film on a Subtrate; forming a channel hole penetrating the firt inulating layer and the firt conductive film; doping impuritie onto ide wall of the firt conductive film expoed through the channel hole; forming multilayer film including a charge torage film on inner wall of the channel hole; and forming a ubtantially vertical channel layer within the channel hole. BRIEF DESRIPTION OF THE DRAWINGS 0010 FIG. 1 i a perpective view of a emiconductor memory device according to an embodiment; FIG. 2 i a cro-ectional view of the emiconduc tor memory device illutrated in FIG. 1; 0012 FIG. 3 i a plan view of the emiconductor memory device illutrated in FIG. 1; 0013 FIG. 4 i a cro-ectional view of a emiconductor memory device according to an embodiment; 0014 FIG. 5 i a plan view of the emiconductor memory device according to an embodiment; 0015 FIG. 6 i a graph illutrating operational character itic of a emiconductor memory device according to an embodiment; 0016 FIGS. 7A to 7K are cro-ectional view illutrat ing a method for manufacturing a emiconductor memory device according to an embodiment; and 0017 FIG. 8 i a ectional view illutrating a method for manufacturing a emiconductor memory device according to an embodiment. DETAILED DESRIPTION Hereinafter, variou embodiment of the preent dicloure will be decribed with reference to the accompa nying drawing. The ame reference numeral or the ame reference deignator may denote the ame element through out the pecification. However, the embodiment may be implemented in many different form and hould not be con trued a being limited to the embodiment et forth herein. Rather, thee embodiment are provided o that the dicloure will be thorough and complete, and will fully convey the cope of the invention to thoe killed in the art and are defined by the claim coverage of the preent invention FIG. 1 i perpective view of a emiconductor memory device according to an embodiment. FIG. 2 i a cro-ectional view of the emiconductor memory device illutrated in FIG.1. FIG.3 i a plan view of the emiconduc tor memory device illutrated in FIG. 1. (0020 Referring to FIGS. 1 to 3, conductive film 113 and inulating layer 109 are alternately and repeatedly tacked on a ubtrate (not illutrated). The conductive film 113 may include a polyilicon film and may be formed a polyilicon film with P type impuritie doped therein. The inulating layer 109 may be formed a oxide film. (0021. A channel hole 119A (ee FIG.7) penetrating the conductive film 113 and the inulating layer 109 may be formed. Multilayer film ML and a ubtantially vertical channel layer 137 may be formed within the channel hole 119A. Here, the multilayer film ML are interpoed between the conductive film 113 and the vertical channel layer 137. Accordingly, the conductive film 113 may be dipoed to ubtantially cover the multilayer film ML at different height of the vertical channel layer 137. (0022. The vertical channel layer 137 may be formed of a polyilicon film. The channel hole 119A may be filled by the ubtantially vertical channel layer 137. Alo, the ubtan tially vertical channel layer 137 may include an empty pace at the center thereof, for example, a ubtantially cylindrical hape (or a ubtantially macaroni-like hape), and in thi cae, the internal empty pace of the Subtantially vertical channel layer 137 may be filled with the inulating layer The multilayer film ML may include a charge tor age film 133. Additionally, the multilayer film ML further may include a tunnel inulating layer 135 interpoed between the charge torage film 133 and the ubtantially vertical channel layer 137 and a blocking inulating layer 131 inter poed between the charge torage film 133 and the conductive film 113. The tunnel inulating layer 135 may beformed a an oxide film ubtantially covering outer wall of the ubtan tially vertical channel layer 137. The charge torage film 133 may be formed a a nitride film ubtantially covering the

18 US 2013/O A1 Jun. 27, 2013 tunnel inulating layer 135. The blocking inulating layer 131 may be formed to Subtantially cover the tunnel inulating layer 135 and may be formed a an oxide layer, or preferably, a a high-k inulating layer Such a aluminum oxide film having a dielectric contant value higher than that of an oxide film In a bit-cot calable (BiS) tructure or a pipe haped BiS (P-BiS) tructure, the multilayer film ML may be formed on the entire inner wall of the channel hole 119A, o the ubtantially vertical channel layer 137 may be ubtantially covered by the multilayer film ML. The multi layer film ML may extend from between the vertical channel layer 137 and the conductive film 113 to between the vertical channel layer 137 and the inulating layer Additionally, electrical characteritic of the device may vary according to the concentration of impuritie included in the conductive film 113. For example, when the concentration of impuritie included in the conductive film 113 i low, an eraure peed i lowered. Namely, a threhold voltage of a memory cell M i not readily lowered during an erae operation. The impurity concentration of the conductive film 113 may be lowered in etching the conductive film 113 to form the channel hole 119A, and may alo be lowered by a follow-up cleaning proce or thermal treatment proce. In order to compenate thi, impuritie may be additionally injected (or doped) onto etching Surface (inner wall) of the conductive film 113 expoed after the formation of the chan nel hole 119A to raie impurity concentration of the conduc tive film Alo, in order to prevent impuritie included in the conductive film 113 from being dicharged to an outer ide from etched Surface (i.e., expoed inner wall), an anti-dif fuion film 125 may be formed on the etched urface of the conductive film 113. In the BiS Structure or the P-BiS tructure, the conductive film 113 and the inulating layer 109 may be etched to form the channel hole 119A, inner wall of the conductive film 113 expoed through the channel hole 119A may make etched urface. The etched urface of the conductive film 113 ubtantially face the ubtantially vertical channel layer 137. Thu, the anti-diffuion film 125 may be interpoed between the inner wall of the conductive film 113 ubtantially facing the ubtantially vertical chan nel layer 137 and the multilayer film ML Accordingly, the tunnel inulating layer 135, the charge torage film 133, the blocking inulating layer 131, and the anti-diffuion film 125 may be interpoed between the ubtantially vertical channel layer 137 and the conductive film 113. If the anti-diffuion film 125 erve a a blocking inulating layer, the blocking inulating layer 131 may be omitted. In thi cae, the tunnel inulating layer 135, the charge torage film 133, and the anti-diffuion film 125 may be interpoed between the ubtantially vertical channel layer 137 and the conductive film Additionally, when the conductive film 113 are etched to form the channel hole 119A, a great deal of lo of impuritie i made at upper and lower corner of the conduc tive film 113. In order to prevent thi, anti-diffuion film 111 and 115 (i.e., may be referred to a econd anti-diffuion film) may be further formed on upper and lower portion of each of the conductive film 113. In thi cae, the anti-diffu ion film 111 or 115 may be further interpoed between every one of the conductive film 113 and the inulating layer The anti-diffuion film 111,115, and 125 decribed herein may include a nitride film. Among them, the anti diffuion film 111 may be formed a a nitride film through depoition, and the anti-diffuion film 115 and 125 may be formed by nitriding the conductive film The ubtantially vertical channel layer 137, the multilayer film ML, and the conductive film 113 a decribed above may contitute a memory cell M, and the anti-diffuion film 125 may be further included in the memory cell M FIG. 4 i a cro-ectional view of a emiconductor memory device according to an embodiment. FIG. 5 i a plan view of the emiconductor memory device according to an embodiment Referring to FIGS. 4 and 5, outer ide wall of the conductive film 113 may be etched urface. The reaon i a follow In a terabit cell array tranitor (TAT) tructure, intead of a conductive film, a acrificial film (not illutrated) uch a a nitride film may be formed between the inulating layer 109, the inulating layer 109 and the acrificial film may be etched to form a channel hole, and the ubtantially vertical channel layer 137 may be formed in the channel hole 119A. Subequently, when an etching proce i performed to pattern the inulating layer 109 and the acrificial film, the inulating layer 109 and the acrificial film remain epa rately on mutually different ide wall of the mutually differ ent ubtantially vertical channel layer 137. Subequently, the acrificial film between the inulating layer 109 may be removed, multilayer film ML including the charge torage film 133 may beformed on the ide wall of the ubtantially vertical channel layer 137 and the urface of the inulating layer 109 may be expoed a the acrificial film were removed, and pace between the inulating layer 109 with the multilayer film ML formed thereon may be filled with the conductive film 113. Thereafter, an etching proce may be performed on the conductive film 113 uch that the conduc tive film 113 remain only between the inulating layer 109. In thi manner, in the TAT tructure, the multilayer film ML extend from between the ubtantially vertical channel layer 137 and the conductive film 113 to between the con ductive film 113 and the inulating layer 109. In detail, the multilayer film ML extend from between the ubtantially vertical channel layer 137 and the inner ide wall of the conductive film 113, to outer ide wall of the inulating layer 109 by way of pace between the inulating layer 113 and the inulating layer Through the foregoing proce, the outer ide wall of the conductive film 113 make etched urface. With the outer ide wall correponding to the etched urface of the conductive film 113 expoed, impuritie may be additionally injected (or doped) onto the expoed etched Surface (outer ide wall) of the conductive film 113 to increae the lowered impurity concentration of the conductive film 113. Alo, in order to prevent impuritie included in the conductive film 113 from being dicharged to the outide from the etched Surface (i.e., the expoed outer ide wall), the anti-diffuion film 125 may be formed on the outer ide wall of the con ductive film 113. Alo, an anti-diffuion film (not illutrated) may be further interpoed between every one of the conduc tive film 113 and the inulating layer The ubtantially vertical channel layer 137, the multilayer film ML, and the conductive film 113 a decribed above contitute a memory cell M, and the anti

19 US 2013/O A1 Jun. 27, 2013 diffuion film 125 formed on the outer ide wall of the conductive film 113 may be further included in the memory cell M FIG. 6 i a graph illutrating operational character itic of a emiconductor memory device according to an embodiment Referring to FIG. 6, it can be een that, when impu rity concentration of a conductive film ued a a word line or a control gate i low (A, B, and ), threhold Voltage (i.e., Vth) were not lowered although an erae time wa length ened, but when the concentration of impuritie included in the conductive film wa high (D and E), threhold voltage were Sufficiently lowered a the erae time wa lengthened The impurity concentration of the conductive film may be lowered in a proce of etching the conductive film, and in thi cae, the impurity concentration may be raied by doping impuritie onto the etching Surface of the conductive film after the etching proce, thu preventing a degradation of operational characteritic. Alo, in order to prevent impu ritie of the conductive film from being dicharged from the etched urface of the conductive film during a follow-up cleaning proce or thermal treatment proce, an anti-diffu ion film may be formed on the etched urface of the con ductive film after impurity doping, thu preventing a degra dation of operational characteritic Hereinafter, a method of manufacturing a emicon ductor memory device a decribed above will be decribed FIGS. 7A to 7K are cro-ectional view illutrat ing a method for manufacturing a emiconductor memory device according to an embodiment. FIG. 8 i a ectional view illutrating a method for manufacturing a emiconductor memory device according to an embodiment a well Referring to FIG. 7A, in the cae of the P-BiS tructure, an inulating layer 103 may be formed on a ub trate 101, and a pipe gate 105 including a acrificial film 107 may be formed on the inulating layer 103. Additionally, for example, a conductive film 105A may be formed on the inulating layer 103, and a partial region of the conductive film 105A may be etched to have a certain depth to form a trench in the conductive film 105A. The trench may be filled with the acrificial film 107 uch a a ilicon nitride film 107 or a polyilicon film. Subequently, a conductive film 105B may beformed on the acrificial film 107 and the conductive film 105A. Here, the conductive film 105A and 105B may be formed a polyilicon film with impuritie doped therein In the cae of the BiS tructure, a illutrated in FIG. 8, a common ource 102 may be formed on the ubtrate 101. The common ource 102 may be formed by injecting econd type (e.g., an N type) of impuritie different from firt type (e.g., a Ptype) of impuritie included in the Subtrate, or may be formed by depoiting a polyilicon film including the econd type of impuritie. Meanwhile, in the cae of the TAT tructure, the proce decribed above with reference to FIG. 7B may be performed without forming a pipe gate or a OO SOU Tranitor for forming peripheral circuit may be fabricated in neighbor region while the foregoing proce i performed or before or after the proce Hereinafter a proce of fabricating a emiconduc tor memory device having a P-BiS tructure will be decribed a an example Referring to FIG. 7B, inulating layer 109 and con ductive film 113 may be alternately and repeatedly formed on the Subtrate 101 with a tructure including a pipe gate formed thereon. Here, the inulating layer 109 may be formed a ilicon oxide film and ued a inulating layer between cell gate. The conductive film 113 may be formed a polyilicon film including P type impuritie and ued a control gate or word line. The number of Stacked conduc tive film 113 may correpond to the number of memory cell connected in erie in a memory String For reference, preferably, the inulating layer 109 may be formed a the lowermot layer and the uppermot layer in the tacked tructure of the conductive film 113. Alo, the inulating layer 109 of the lowermot layer and the uppermot layer may be formed to be thicker than the inu lating layer 109 formed between the conductive film 113. The uppermot conductive film among the conductive film 113 may be ued a a gate of a elect tranitor, o it may be formed to be thicker than the other conductive film. In the BiS tructure or the TAT tructure, the lowermot conduc tive film may alo be ued a a gate of the elect tranitor, o it may alo be formed to be thicker Additionally, anti-diffuion film 111 and 115 may be further formed between the conductive film 113 and the inulating layer 109. Namely, the anti-diffuion film 111 and 115 may be further formed on upper and lower portion of the repective conductive film 113, and here, the anti-diffu ion film 111 and 115 may be formed a nitride film. The lower anti-diffuion film 111 may be formed through depo ition, and the upper anti-diffuion film 115 may be formed through depoition or by nitriding an upper Surface of each of the conductive film 113. The anti-diffuion film 111 and 115 may be formed to protect upper and lower corner of the conductive film 113 in a follow-up proce of etching the conductive film 113, to the prevent impuritie of the conduc tive film 113 from being dicharged to the outide from the upper and lower corner Referring to FIG.7, a hard mak may be patterned to form a hard mak pattern 117 (ee alo FIG. 7B) expoing a region in which a channel hole i to be formed, and Stacked tructure 109, 111, 113, and 115 may be etched through an etching proce uing the hard mak pattern 117 a an etching mak. Accordingly, two channel hole 119A and 119B may be formed in every ingle memory String. In forming the channel hole 119A and 119B, preferably, etching may be performed on and up to an upper portion of the pipe gate 105 uch that the acrificial film 107 within the pipe gate 105 i expoed. Ideally, the ide wall of the channel hole 119A and 119B are perpendicular or ubtantially perpendicular to the ubtrate 101, but in term of proce characteritic, the channel hole 119A and 119B may be formed uch that the ide wall thereof are le loped than being perpendicular A the channel hole 119A and 119B are formed, inner ide wall (etched urface) of the conductive film 113 may be expoed from the ide wall of the channel hole 119A and 119B and the acrificial film 107 may be expoed from the bottom of the channel hole 119A and 119B. The ide wall of the conductive film 113 may alo be expoed lop ingly. Additionally, in the proce of etching the conductive film 113 to form the channel hole 119A and 119B, impuri tie included in the conductive film 113 may be dicharged to lower impurity concentration of the conductive film 113. Thu, procee may be performed to compenate for it Additionally, when impuritie are doped into the pipe gate 105 in the proce of doping impuritie into the conductive film 113, impurity concentration of the pipe gate 105 may be further increaed to caue a voltage breakdown

20 US 2013/O A1 Jun. 27, 2013 problem. Thu, in order to complement for thi problem, preferably, an anti-doping film i formed on the bottom of the channel hole 119A and 119B and doping impuritie into the conductive film 113 may be ubequently performed. Thi will be decribed in below a follow Referring to FIG.7D, anti-etching film 121 may be formed on ide wall of the channel hole 119A and 119B and the channel hole 119A and 119B may be filled with inulat ing layer 123. The anti-etching film 121 may be formed a nitride film, and the inulating layer 123 may be formed a oxide film Referring to FIG. 7E, upper portion of the inulat ing layer 123 may be etched Such that the inulating layer 123 remain only on the bottom of the channel hole 119A and 119B. Here, the inulating layer 109 between the con ductive film 113 may be protected by the anti-etching film 121 and thu not etched. Subequently, upper portion of the anti-etching film 121 may alo be etched uch that the anti etching film 121 remain only on the bottom of the channel hole 119A and 119B. Here, expoed portion of the anti etching film 121 may be removed, and the anti-etching film 121 may remain a high a the inulating layer 123. Alo, in order to expoe ide wall of the conductive film 113 and prevent the pipe gate 105 from being expoed, preferably, the anti-etching film 121 and the inulating layer 123 remain by only the height correponding to a middle portion of the lowermot inulating layer 109 among the inulating layer 109. Accordingly, the anti-doping film 121 may be formed on the bottom of the channel hole 119A and 119B and the pipe gate 105 may not be expoed Referring to FIG. 7F, in order to upplement impu ritie of the conductive film 113 dicharged through the ide wall of the conductive film 113 expoed, a the channel hole 119A and 119B are formed, a proce of doping impu ritie onto the ide wall of the conductive film 113 expoed through the channel hole 119A and 119B may be performed. Here, the ame type of impuritie (e.g., boron) a the type (e.g., P type) of impuritie included in the conductive film 113 may be doped Impurity doping may be performed through tilted ion implantation. Alo, impuritie may be diffued into the conductive film 113 through the expoed inner ide wall (etched urface) of the conductive film 113 by upplying a ga including P type impuritie, thu creating impuritie. Accordingly, impurity injected region may be formed on expoed edge region of the conductive film 113, and thu, impurity concentration of the conductive film 113 may be raied to reach a target concentration or higher Referring to FIG. 7G, anti-diffuion film 125 may be formed on the expoed ide wall of the conductive film 113. The anti-diffuion film 125 may be made of nitride film and may be electively formed only on the expoed ide wall of the conductive film 113 through a nitriding proce A the anti-diffuion film 125 are formed on the expoed ide wall of the conductive film 113, all the ur face of the conductive film 113 may be ubtantially ur rounded by the anti-diffuion film 111, 115, and 125. A a reult, although a follow-up cleaning proce orthermal treat ment proce may be performed, impuritie included in the conductive film 113 can be prevented from being dicharged to the outide, and thu, impurity concentration of the con ductive film 113 may not be lowered Thereafter, procee for removing the anti-doping film and the acrificial film may be performed Referring to FIG.7H, anti-etching film 127 may be formed on the ide wall of the channel hole 119A and 119B. The anti-etching film 127 may be formed a nitride film Referring to FIG. 7I, the inulating layer 123 remaining on the bottom of the channel hole 119A and 119B and the acrificial film 107 within the pipegate 105 may be removed. When the inulating layer 123 and the acrificial film 107 are removed, the inulating layer 109 between the conductive film 113 may be protected by the anti-etching film A the inulating layer 123 and the acrificial film 107 are removed, a ubtantially horizontal pace 129 may be formed and connected to the channel hole 119A and 119B in ubtantially the vertical direction Referring to FIG. 73, the anti-etching film 121 and 127 are removed Referring to FIG. 7K, the multilayer film ML including the charge torage film 133 may beformed on inner wall of the pipe gate 105 and the channel hole 119A and 119B. The multilayer film ML may include the tunnel inu lating layer 135, the charge torage film 133, and the blocking inulating layer 131. The blocking inulating layer 131 may be formed on the inner wall of the ubtantially horizontal pace 129 within the pipe gate 105 and the channel hole 119A and 119B, and may be formed a a high-k inulating layer Such a an aluminum oxide film having a dielectric contant value higher than that of a ilicon oxide film or nitride film. The charge torage film 133 may be formed on a urface of the blocking inulating layer 131 and may be formed a a nitride film. The tunnel inulating layer 135 may beformed on a urface of the charge torage film 133 and may be formed a a ilicon oxide film Subequently, the channel layer 137 may be formed in the channel hole 119A and 119B and the ubtan tially horizontal pace within the pipe gate 105. The channel layer 137 may include ubtantially vertical channel layer formed within the channel hole 119A and 119B, repec tively, and a ubtantially horizontal channel layer formed in the ubtantially horizontal pace 129. In the BiS tructure or the TAT tructure, uch a pipe gate 105 or uch a ub tantially horizontal pace 129 in the pipe gate 105 doe not exit, o the ubtantially vertical channel layer 137 may be formed only within the channel hole 119A and 119B Additionally, the channel layer 137 may be formed to fill the entirety of the channel hole 119A and 119B and the ubtantially horizontal pace 129. Alo, when the channel layer 137 are formed on the multilayer film ML, the channel layer 137 may be formed uch that they do not fully fill the channel hole 119A and 119B and the ubtantially horizon tal pace 129. In thi cae, the channel layer 137 may be formed to have a ubtantially hollow cylindrical hape (or a macaroni-like hape), and the inner pace (i.e., the remaining pace of the channel hole and the horizontal pace) of the channel layer 137 may be filled with the inulating layer Thereafter, although not illutrated, the tacked tructure 109,111,113, and 115 are etched to form a lit, and elect line may be defined according to a conventional tech nique. Alo, bit line and a common Source line may be formed to be connected to the ubtantially vertical channel layer Through the foregoing procee, impuritie are additionally doped onto the conductive film 113 and the doped impuritie may be prevented from being dicharged

21 US 2013/O A1 Jun. 27, 2013 from the conductive film 113 by uing the anti-diffuion film 111,115, and 125, whereby electrical characteritic of the emiconductor memory device can be enhanced Thu, according to embodiment of the preent invention, operating characteritic of the emiconductor memory device can be enhanced. What i claimed i: 1. A emiconductor memory device compriing: conductive film and inulating layer alternately tacked on a Subtrate; Subtantially vertical channel layer penetrating the con ductive film and the inulating layer; multilayer film including a charge torage film interpoed between the conductive film and the ubtantially ver tical channel layer; and a firt anti-diffuion film formed on etched urface of the conductive film. 2. The emiconductor memory device of claim 1, wherein the firt anti-diffuion film i interpoed between inner wall of the conductive film and the multilayer film. 3. The emiconductor memory device of claim 1, wherein the firt anti-diffuion film i formed on outer wall of the conductive film. 4. The emiconductor memory device of claim 1, further compriing: a econd anti-diffuion film interpoed between the con ductive film and the inulating layer. 5. The emiconductor memory device of claim 4, wherein the econd anti-diffuion film i formed on upper and lower portion of the conductive film. 6. The emiconductor memory device of claim 4, wherein the firt anti-diffuion film and the econd anti-diffuion film include a nitride film. 7. The emiconductor memory device of claim 1, wherein the multilayer film comprie: a tunnel inulating layer interpoed between the Subtan tially vertical channel layer and the charge torage film; and a blocking inulating layer interpoed between the charge torage film and the conductive film. 8. The emiconductor memory device of claim 1, wherein the multilayer film extend from between the ubtantially vertical channel layer and the conductive film to between the Subtantially vertical channel layer and the inulating layer. 9. The emiconductor memory device of claim 1, wherein the multilayer film extend from between the ubtantially vertical channel layer and the conductive film to between the conductive film and the inulating layer. 10. The emiconductor memory device of claim 1, wherein the conductive film include a polyilicon film having P type impuritie doped therein. 11. An operating method of a emiconductor memory device compriing: alternately and repeatedly tacking firt inulating layer and firt conductive film on a Subtrate; forming a channel hole penetrating the firt inulating lay er and the firt conductive film; doping impuritie onto ide wall of the firt conductive film expoed through the channel hole; forming multilayer film including a charge torage film on inner wall of the channel hole; and forming a ubtantially vertical channel layer within the channel hole. 12. The operating method of claim 11, wherein the firt conductive film include a P type polyilicon film. 13. The operating method of claim 11, wherein P type impuritie are doped onto ide wall of the firt conductive film in order to increae impurity concentration of the firt conductive film. 14. The operating method of claim 11, wherein the impu ritie are doped onto the ide wall of the firt conductive film through a tilted ion implantation proce. 15. The operating method of claim 11, wherein the impu ritie are doped onto the ide wall of the firt conductive film through diffuion under an impurity ource ga atmophere. 16. The operating method of claim 11, further compriing: forming an anti-doping film on the bottom of the channel hole before impuritie are doped; and removing the anti-doping film before the multilayer film are formed. 17. The operating method of claim 11, further compriing: forming a firt anti-diffuion film on expoed ide wall of the firt conductive film in order to prevent impuritie from being dicharged from the firt conductive film, after the impuritie are doped. 18. The operating method of claim 17, wherein a econd anti-diffuion film i further formed between the firt inulat ing layer and the firt conductive film, in tacking the firt inulating layer and the firt conductive film. 19. The operating method of claim 18 wherein the firt anti-diffuion film and the econd anti-diffuion film are formed of nitride film. 20. The operating method of claim 11, further compriing: before the firt inulating layer and the firt conductive film are tacked, forming a econd inulating layer and a econd conductive film on the ubtrate; forming a trench in the econd conductive film; filling the trench with a acrificial film; and forming a third conductive film on the acrificial film and the econd conductive film, wherein the channel hole penetrate the third conductive film in order to expoe the econd inulating layer. 21. The operating method of claim 20, further compriing: before the multilayer film are formed, removing the econd inulating layer to expoe inner wall of the econd conductive film and the third conductive film, wherein the multilayer film and the ubtantially vertical channel layer extend from inner wall of the channel hole to inner wall of the econd and third conductive film. 22. The operating method of claim 11, further compriing: before the firt inulating layer and the firt conductive film are tacked, forming a common Source region on the Subtrate. k k k k k