BG0803 1/3 inch CMOS Full HD Digital Image Sensor. BG0803 Datasheet

Transcription

1 0803 1/3 inch CMOS Full HD Digital Image Seor 1/3-inch CMOS FULL HD Digital Image Seor 0803 Datasheet (The contents of this Preliminary Datasheet are subject to change without notice) eneral Descriptio 0803 is a high performance 1/3 inch Full HD CMOS digital image seor with an active-pixel array of 1936H x 1096V. This chip features high seitivity and high dynamic range 2.8um x 2.8um pixels. An external trigger mode is implemented. It is programmable through a simple two-wire serial interface. Features High seitivity and high dynamic range pixel. Single frame or video trigger mode. Programmable controls: gain, frame rate, frame size, exposure. Superior low light performance. Enhanced NI performance. Auto black level calibration. lack sun cancellation. Defect pixel correction Maximum 30 frame per second. Applicatio High-end surveillance Industrial vision Key Parameter Parameter Optical format Active pixel array Pixel size Active pixel array Area Frame rate Color filter array CA Shutter Type Seitivity@550nm Dark current@60⁰c 1 SN max Dynamic range Output Power supply Table 1 Key Specification Digital IO Analog Pixel Power Coumption Temperature range 2 Package Option Note 1: junction temperature Note 2: junction temperature Typical Value 1/3 inch 1936H x1096v 2.80um(H) x 2.80um(V) um x um 30fps@full frame ayer /W 0 Electronic olling 2.2V/lux.sec 10mV/s (preliminary) 41d 70d 12-bit 1.35V~1.65V 1.7V~3.45V 3.15V~3.45V 3.2V~3.4V 300mW@30fps -30 ~70 ⁰C CSP In the absence of confirmation by device specification sheets, IATES takes no respoibility for any defects that may occur in equipment using any IAES device shown in catalogs, data book, etc. Contact IATES in order to obtain the latest device specification before using any IATES device. 1/ 17

2 Table of Content eneral Descriptio... 1 Features... 1 Applicatio... 1 Key Parameter... 1 Top-level Description... 5 lock-level Description... 6 Image Seor Array... 6 I2C Slave Interface... 6 Digital Image Processing... 7 Pin Outs... 8 Output Timing Chip Control ain Frame Time Exposure Window Control Vertical lanking Control ead out order estart egister Description Chip Characteristics QE respoe I/O Timing Electrical Specificatio Maximum atings Power-up Sequence Mechanical Drawing / 17

3 List of Figures Figure 1 lock Diagram... 5 Figure 2 Pixel Array ead Out... 6 Figure 3 Color Filter Arrangements... 6 Figure 4 I2C Slave Write Operation... 7 Figure 5 I2C Slave ead Operation... 7 Figure 6 Pin Diagram... 8 Figure 7 Output Timing Diagram Figure 8 Analog Processing and AD Conversion Figure 9 Imaging a Scene Figure 10 QE respoe Figure 11 I/O Timing Diagram Figure 12 Power-up Sequence Figure 14 Mechanical Drawing / 17

4 List of Tables Table 1 Key Specification... 1 Table 2 IO Description... 8 Table 3 IO Timing Table 4 Electrical Specification Table 5 Maximum atings / 17

5 Top-level Description 0803 is a progressive-scan image seor with 1936x10966 active pixels array which generates a stream of pixel data at a maximum frame rate of 30 fps. Frame size, exposure, gain and other parameters are programmable through I2C interface. Figure 1 shows the function diagram of The timing and control circuitry sequences through the rows of array, resetting and then reading each row in turn. Once the pixel data of a row is put onto bit-line, analog processing and A/D conversion is performed in column parallel way. The output from the ADC is a 12-bit value for each pixel and then is passed to digital data path. Digital image processing unit provides row wise noise canceling, black level correction and dead pixel cancellation. esides, digital gain is performed in this part. After these, image will output in parallel way along with VSYNC, HSYNC and synchronized pixel clock. I2C slave interface is utilized in this chip which is used to get access to the internal register file. The register file controls the array, analog signal and digital signal chain. Array&Analog path Image Seor Array Timing and Control Analog processing and A/D Conversion Datapath Digital Image Processing Parallel Output egister File I2C Slave SDA SCL Figure 1 lock Diagram 5/ 17

6 lock-level Description Image Seor Array The image seor array contai 1936 x 1096 active pixels. esides, 6 dark rows and 144 dark colum can be read out for special purpose as Figure employs primary color filter of (red, green and blue), the color filter arrangement (top right corner of pixel array) is show in Figure 3. 6 dark rows 144 dark colum 1936x1096 Active Pixel Active (0,0) point Figure 2 Pixel Array ead Out LACK PIXELS (0,0) point LACK PIXELS Figure 3 Color Filter Arrangements I2C Slave Interface 0803 is programmable through I2C interface with reading slave device address 0x65 and writing slave device address 0x64. The related IO pin is SCL and SDA. SCL works as the serial clock and SDA as the data line. Figure 4 showss example of the write operation (Writing 0x2C register with 0x56 data). The sequence is defined as following: 6/ 17

7 SCL The master sends a start bit to the slave. The master sends the slave device address with write mode. The slave sends an acknowledge bit to the master to indicate receive its slave device address. The master sends 8-bit register address to the slave. The slave sends an acknowledge bit after it receives the 8-bit data. The master sends 8-bit register data to the salve. The slave sends an acknowledge bit after it receives the 8-bit data The master sends a stop bit to the slave. SDA 0x64 ADD 0x2C E 0x56 DATA STAT ACK ACK ACK STOP Figure 4 I2C Slave Write Operation Figure 5 showss example of the read operation (Writing 0x56 data from 0x2C register). The sequence is defined as following: The master sends a start bit to the slave. The master sends the slave device address with write mode. The slave sends an acknowledge bit to the master. The master sends 8-bit register address to the slave. The slave sends an acknowledge bit to the master. The master sends a start bit to the slave. The master sends the slave device address with read mode. The slave sends an acknowledge bit to the master. The slave sends 8-bit data to the master The master sends a no-acknowledge bit to the slave. The master sends a stop bit to the slave to stopping read. SCL SDA 0x64 ADD 0x2C E 0x65 ADD 0x56 DATA STAT ACK ACK STAT ACK ACK STOP Figure 5 I2C Slave ead Operation Digital Image Processing Digital Image processing unit provides row wise noise canceling and LC. ow wise noise correction: ow wise noise is handled automatically by the image seor. ow wise noise correction unit measures a set of optical black pixels at the start of each line and 7/ 17

8 then apply the average to the tied active pixels of the line. LC: lack level correction is handled automatically by the image seor. y measures the average value of pixels from a set of optical black lines in the image seor, it reduce the circuit offset to an acceptable level. Pin Outs A VSSA VDDA _PLL VSSA VSS VDDIO D11 VSS D7 VDDIO VDDD VSSA VDDA VDD VN VDDA VDDA VDD D8 VDD HSYNC VDD VSSS VSSA VSSA C VDDA _PLL VSSA VPUMP VDDA D4 VDD TI ST VSSS VDDA VDD D E VSS VDD VDDIO CLKIN D3 D2 TOP View VDDPIX VDDPIX VSSPIX VSSA VSSA VDDA F VSS VDD D1 VDDA VDD D5 VDD VSYNC SCL VSSS VSS VDD D0 PCLK VDDA VDDA VDD D9 VDD D6 PD VSSS VDDA VSSA H VDDIO VSSIO VSSA VSS VDDIO D10 VSS SDA VDDIO VDDD VSSA VDDA Figure 6 Pin Diagram NO PIN NAME NO 1 A1 VSSA 2 A2 VDDA_PLL 3 A3 VSSA 4 A4 VSS 5 A5 VDDIO 6 A6 D11 7 A7 VSS 8 A8 D7 9 A9 VDDIO 10 A10 VDD 11 A11 VSSA 12 A12 VDDA 13 1 VDD 14 2 VN 15 3 VDDA Table 2 IO Description I/ TYPE DESCIPTION O - P Analog round - P PLL Analog Power - P Analog round - P Digital Core round - P I/O Power - P Digital Core round - P I/O Power - P Analog round O A eference 8/ 17

9 16 4 VDDA 17 5 VDD 18 6 D VDD 20 8 HSYNC 21 9 VDD VSS VSSA VSSA 25 C1 VDDA_PLL 26 C2 VSSA 27 C3 VPUMP 28 C5 VDDA 29 C6 D4 30 C7 VDD 31 C8 TI 32 C9 ST 33 C10 VSS 34 C11 VDDA 35 C12 VDD 36 D1 VSS 37 D2 VDD 38 D3 VDDIO 39 D10 VDDPIX 40 D11 VDDPIX 41 D12 VSSPIX 42 E1 CLKIN 43 E2 D3 44 E3 D2 45 E10 VSSA 46 E11 VSSA 47 E12 VDDA 48 F1 VSS 49 F2 VDD 50 F3 D1 51 F4 VDDA 52 F5 VDD 53 F6 D5 54 F7 VDD 55 F8 VSYNC 56 F9 SCL 57 F10 VSS O D Hsync - P Digital Core round - P Analog round - P Analog round - P PLL Analog Power - P Analog round O A eference I D Trigger Pin I D stb - P Digital Core round - P Digital Core round - P I/O Power - P Pixel Array Power - P Pixel Array Power - P Pixel Array round I D Main Clock - P Analog round - P Analog round - P Digital Core round O D Vsync I D I2C Slave Clock - P Digital Core round 9/ 17

10 58 F11 VSS 59 F12 VDD 60 1 D PCLK 62 3 VDDA 63 4 VDDA 64 5 VDD 65 6 D VDD 67 8 D PD VSS VDDA VSSA 72 H1 VDDIO 73 H2 VSSIO 74 H3 VSSA 75 H4 VSS 76 H5 VDDIO 77 H6 D10 78 H7 VSS 79 H8 SDA 80 H9 VDDIO 81 H10 VDD 82 H11 VSSA 83 H12 VDDA - P Analog round O D Pixel Clock I D Power down, active high - P Digital Core round - P Analog round - P I/O Power - P I/O round - P Analog round - P Digital Core round - P I/O Power - P Digital Core round I D I2C Slave Data - P I/O Power - P Analog round Output Timing The 0803 images are read out in progressive scan mode, which are divided into frames and further divided into lines. y default, the seor produces 1920H*1080V pixels. The VSYNC and HSYNC signal indicates the boundaries between and lines. PIXCLK can be used as a clock to latch the data. PIXCLK VSYNC HSYNC DOUT[0:11] D0 D1 D2 D3 D4 D5 D6 DN Figure 7 Output Timing Diagram 10/ 17

11 Chip Control ain 0803 has two stages of gain, including AD amp gain and Digital gain. AD Digital gain itline ain Mapping ain code I2C Slave Interface Figure 8 Analog Processing and AD Conversion amp ain: amp ain controls the slope of AD ramp. The ramp gain is determined by ain ramp =(160-vrefh)/(vrefl+1-vrefh) Digital ain: Digital gain can be controlled by register 0xb7 and 0xb8 on page 00. The format for digital gain setting is x_xxx_xxx.yyy_yyy_yy where 16'h0100 represents a 1x gain. Frame Time In case of integration time is less than vertical size plus vertical blanking value, frame time is decidedd by the sum of vertical size and vertical blanking. Otherwise, frame time is decided by the integration time. Exposure Integration time is controlled by TEXP register, which use T row as time unit. Typically, the value of the TEXP register is limited to the number of line per frame (VLANK+VSIZE), such that the frame rate is not affected by the integration time. After write TEXP register, use ESTAT register to make an update. Window Control HSTAT, HSIZE, VSTAT, VSIZE control the starting coordinates and size of the image window. 11/ 17

12 Vertical lanking Control Vertical blank time is controlled by the VLANK registers, which is calculated in terms of OW_TIME. ead out order y default, place the seor as Figure 9 shows to achieve the right image order See Seor Le 1 A1 A2 (0803 rear view) (0,0) Figure 9 Imaging a Scene 0803 also supports row mirror and column flip process. estart To restart 0803 at any time during the operation of the seor, write a "1" to the ESTAT register. The seor will stop the current frame immediately and a new frame starts. egister Description 0803 has two banks of control registers, which is controlled by page register 0xf0. Each 8-bit address accesses an 8-bit storage space. Some register may take more than one coecutive addresses, which mea these contents of coecutive addresses form the value of the register together is programmable through I2C interface with reading slave device address 0x65 and writing slave device address 0x64. 12/ 17

13 Chip Characteristics QE respoe QE wavelength (nm) Figure 10 QE respoe I/O Timing t tf tp tfp T CLKIN CLKIN PIXCLK t DH t DS DATA[11:0] DATA_1 DATA_2 DATA_3 DATA_4 DATA_5 DATA_6 VSYNC HSYNC t PFH t PLH t PFL t PLL Figure 11 I/O Timing Diagram Symbol f CLKIN t t F Table 3 IO Timing Definition Min Typ Max Input clock frequency 37 Input clock rise time 3 Input clock fall time 3 13/ 17 Unit

14 t P t FP f PIXCLK T DS T DH t PFH t PFL t PLH t PLL C LOAD C IN PIXCLK rise time 2 PIXCLK fall time 2 Frequency of PIXCLK 12.5 DATA SETUP time 5 DATA HOLD time 5 PIXCLK to FV HIH 0 PIXCLK to FV LOW 0 PIXCLK to LV HIH 0 PIXCLK TO LV LOW 0 Output load capacitance - <1.5 - Input pin capacitance - - pf pf Electrical Specificatio Symbol V DD-A V DD-D V DD-IO V DD-Pix V IH Definition VDDA voltage VDD voltage VDDO voltage VDDPIX voltage V IL Input Voltage High Table 4 Electrical Specification Condition Min Typ Max Unit Note V V V V 0.7 Input Voltage Low *V DD-IO 0.3 *V DD D-I V V I IN V OH V OL I OH Input Leakage Current Output High Voltage Output Low Voltage Output Current High No pull-up resistor,vin=v DD- IO or DND V OH=0.9*V DD-IO *V DD-IO 0.1* *V O DD-IO μa V V ma I OL I DD-A Output Current Low Analog Operating Current V OH=0.1*V DD-IO -7 f PCLK=80 MHz Default setting 50 ma ma I DD-D Digital Operating Current f PCLK=80 MHz Default setting 75 ma I DD-IO IO Operating Current f PCLK=80 MHz Default setting 20 ma I DD-Pixel Pixel Operating Current f PCLK=80 MHz Default setting 5 ma 14/ 17

15 Maximum atings Item Supply voltage(analog 3.3) Supply voltage(analog 3.3) Supply voltage(digital 1.5) Supply voltage(pixel 3.3) Input voltage Output voltage Operating temperature Storage temperate Table 5 Maximum atings Symbol Min. Max. Unit V DD-A V DD-IO V DD-D V DD-Pix T opr T stg V V V x V VI -0.3 OVDD_IO+0.3 V VO -0.3 OVDD_IO+0.3 V emarks Not exceed 4V Not exceed 4V Power-up Sequence The recommended power up sequence is show infigure Turn on VDDO, VDDA, VDD and VDDPIX power supply. 2. After 10ms pull up ST. 3. Wait 10ms to supply CLKIN. VDDA VDDO VDD VDDPIX ST CLKIN 10ms 10ms Figure 12 Power-up Sequence 15/ 17

16 Mechanical Drawing Figure 13 Mechanical Drawing 16/ 17

17 evision History Version Initial release Version Package & typical connection added Version Seor parameter updated. Preliminary version Version Update Tab 4, 5 for vddpix part. Move referencee design to PC Design uide 17/ 17