FIN424C / FIN425C 20-Bit Ultra-Low-Power Serializer / Deserializer for µcontroller and RGB Displays

Transcription

1 November 2009 FIN424C / FIN425C 20-Bit Ultra-Low-Power Serializer / Deserializer for µcontroller and RGB Displays Features Data & Control Bits 20 Frequency 10MHz Capability QVGA Interface Microcontroller / RGB µcontroller Usage I86 & m68 Selectable Edge Rates Yes Dynamic Current 9mA / Pair Standby Current 10µA Core Voltage (V DDA/S) 2.5 to 3.0V I/O Voltage (V DDP) 1.6V to V DDA/S ESD 15KV (IEC) Package MLP-32 (5 x 5mm) Ordering Information FIN424CMLX FIN425CMLX Applications Slider, Folder, and Clamshell Mobile Handsets GSM and CDMA Phones Typical Application Baseband Simple Interface 20-Bit Serializer Serializer Ohms Description The FIN424C and FIN425C μserdes are a low-power serializer/ deserializer pair that can help minimize the cost and power of an LCD interface. They are designed to operate transparently between the baseband processor and LCD. /WE and chip-select timing is maintained from the serializer to the deserializer. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. Typical reduction is 5:1. Through the use of differential signaling, shielding, and EMI filters can also be minimized, further reducing the cost of serialization. Differential signaling is important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. Major reduction in power consumption allows minimal impact on battery life in mobile applications. Related Resources For more information, please visit: Built-in voltage translation Deserializer Internal Termination 20-Bit Deserializer Main Display Figure 1. Mobile Phone Example FIN424C / FIN425C Rev

2 FIN424C Serializer Pin Descriptions Pin Name DP[19:0],, VDDS VDDA Description LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge) LVCMOS Data Input Low-Power Mode SerDes Standby Internal Use (Should be ) Serial Data Output Serial Clock Output Power Supply for Parallel I/O and Internal Circuitry Power Supply for Serial I/O Power Supply for Core Ground Pins Notes: 1. 0 = V IL; 1 = V IH. 2. All and pins must be connected to ground and, respectively. 1 2 VDDS 3 VDDA Figure 2. DP[17] DP[16] DP[15] DP[14] DP[13] DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] PAD Must be Grounded 0 Serializer Low Power 1 Serializer Enabled 0 Serializer and Deserializer in Low Power 1 Serializer and Deserializer Enabled DP[12] DP[11] DP[10] DP[9] DP[8] DP[7] DP[6] FIN424CMLX MLP-32 Pinout (Top Through View) FIN424C / FIN425C Rev

3 FIN425C Deserializer Pin Descriptions Pin Name DP[19:0] SLEW,, VDDS VDDA Description LVCMOS Output LVCMOS Data Output Low-Power Mode Parallel Output Edge Rate Control Internal Use (Should be ) Serial Data Input Serial Clock Input Power Supply for Parallel I/O and internal circuitry Power Supply for Serial I/O Power Supply for Core Ground Pins Notes: 3. 0 = V IL; 1 = V IH. 4. All and pins must be connected to ground and, respectively. 1 2 VDDS 3 VDDA Figure 3. DP[17] DP[16] DP[15] DP[14] DP[13] SLEW DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] PAD Must be Grounded 0 Deserializer Low Power 1 Deserializer Enabled 0 Slow Output Edge Rates 1 Fast Output Edge Rates DP[12] DP[11] DP[10] DP[9] DP[8] DP[7] DP[6] FIN425CMLX MLP-32 Pinout (Top Through View) FIN424C / FIN425C Rev

4 Table 1. Reset and Standby Modes / States FIN424C FIN425C FIN424C Mode 0 X Reset Mode 1 0 Standby Mode 1 1 Operating Mode Application Diagram Baseband Processor /WE DP[15:0] A0 CS1 CS2 Reset DP[15:0] DP[16] DP[17] FIN424C 1.8V 2.8V Figure 4. Pins FIN424C Parallel Input State DP[19:0] Disabled LOW FIN425C Parallel Output State / Disabled HIGH DP[19:0] Disabled LAST STATE / Disabled HIGH DP[19:0] Enabled ENABLED / Enabled ENABLED FIN425C 2.8V 2.8V DP[15:0] DP[16] DP[17] Slew Dual-Display, 16-Bit, µcontroller Interface Main Display 16-Bit µcontroller /WE A0 DATA[15:0] RESET /CS Sub-Display 8-Bit µcontroller /WE A0 DATA[7:0] RESET /CS FIN424C / FIN425C Rev

5 Baseband Processor /WE A0 CS Reset Baseband Processor PCLK HSYNC VSYNC /CS Reset FIN424C 1.8V 2.8V Figure 5. FIN424C 1.8V 2.8V Figure 6. Additional Application Information FIN425C 2.8V 2.8V Slew Single Display, 18-Bit, µcontroller Interface FIN425C 2.8V 2.8V Slew Single-Display, 18-Bit, RGB Interface Main Display 18-Bit µcontroller /WE DATA[17:0] /A0 CS RESET PCLK Main Display 18-Bit RGB DATA[17:0] HSYNC VSYNC /CS RESET Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential serial wires the same length. Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires. Use a design goal of 70 to 130Ω differential characteristic impedance. Do not place test points on differential serial wires. Design differential serial wires a minimum of 2cm away from the antenna. Visit Fairchild s website at contact your sales representative, or contact Fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines. FIN424C / FIN425C Rev

6 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V DD Supply Voltage V V IO All Input / Output Voltage -0.5 V DDP+0.5 V T STG Storage Temperature Range C T J Maximum Junction Temperature +150 C T L Lead Temperature (Soldering, Four Seconds) +260 C ESD IEC Board Level 15.0 Human Body Model, JESD22-A114 Recommended Operating Conditions All Pins 7.5 Serial I/O,, PAR/SPI to 14.0 The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit (5) V DDA, V DDS Supply Voltage V V DDP Supply Voltage 1.6 V DDA/S V T A Operating Temperature C Notes: 5. V DDA and V DDS supplies must be hardwired together to the same power supply. V DDP must be less than or equal to V DDA/V DDS. 6. Typical values are tested at T A=25 C and 2.75V. kv FIN424C / FIN425C Rev

7 Electrical Specifications Values valid for over-supply voltage and operating temperature ranges unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit DC Parallel I/O and Serial Characteristics V IH Input High Voltage 0.7 x V DDP V DDP V V IL Input Low Voltage 0.3 x V DDP V V OH V OL Output High Voltage Output Low Voltage SLEW=0 I OH=-250µA SLEW=1 I OH=-1mA SLEW=0 I OL=250µA SLEW=1 I OL=1mA 0.8 x V DDP V 0.2 x V DDP V I IN Input Current -5 5 µa V GO Serial Input Voltage Ground Offset FIN425C to FIN424C 0 V Z Serial Transmission Line Impedance Ω Power Characteristics I DYN_FIN424C I DYN_FIN425C Dynamic Current FIN424C Dynamic Current FIN425C I BRST_FIN424C Burst Standby Current FIN424C I BRST_FIN425C Burst Standby Current FIN425C I STBY I RES Standby Current Reset Current AC FIN424C Specifications V DDA/S=2.75V, V DDP=1.8V, =1, =1 V DDA/S=2.75V V DDP=1.8V, =1, =1, C L=0pF V DDA/S=2.75V, V DDP=1.8V, =1, /RST=1, No STROBE Signal, V DDA/S=2.75V, V DDP=1.8V, =1, /RST=1, No STROBE Signal, C L=0pF FIN424C / FIN425C V DDS/A=V DDP=3.0V, =0, /RST=1 FIN424C / FIN425C V DDS/A=V DDP=3.0V, /RST=0 5.44MHz 4 ma 5.44MHz 5 ma 1.3 ma 1.8 ma 10 µa 10 µa f W0 Strobe Frequency 0 10 MHz t R, t F Input Edge Rates 40 ns t S1 DP Setup Time DP Before n (7) 5 ns t H1 DP Hold Time DP After n (7) 15 ns AC FIN425C Specifications t R0, t F0 t R1, t F1 tcs t PWL Output Edge Rates of Output Edge Rates of DP[19:0] DP[19:0] to Falling edge of C L=5pF 20% to 80% Output Pulse Width Low, Measured 30% to 30% AC Oscillator Specifications SLEW=0, CL=5pF 20% to 80% (7) 8 17 SLEW=1, C L=5pF 20% to 80% (7) 10 SLEW=0, C L=5pF 20% to 80% (7) 8 22 SLEW=1, C L=5pF 20% to 80% (7) 17 DP t CS t PWL 0 4 (7) ns f OSC Serial Operating Frequency MHz t OSC-STBY Oscillator Stabilization Time After Standby V DDA=V DDS=2.75V =1, Transition ns ns µs FIN424C / FIN425C Rev

8 Symbol Parameter Conditions Min. Typ. Max. Unit t OSC-RES Oscillator Stabilization Time After Reset AC Reset and Standby Timing V DDA=V DDS=2.75V =1, Transition t t -RES after last n -RES t - STBY µs 0 ns t -STBY Standby Time After Last Strobe 200 ns t VDD-SKEW t VDD-RES t RES-STBY Allowed Power up Skew between V DDP and V DDA/S Minimum Reset Low Time After V DD Stable Wait Time After Note: 7. Characterized, but not production tested. VDDA/S t VDD-SKEW t VDD-RES t RES-STBY t OSC-STBY - + ms 20 µs 20 µs FIN424C / FIN425C Rev

9 Physical Dimensions Figure 7. PIN #1 IDENT 0.10 C 0.15 C 0.08 C SEATING PLANE PIN #1 IDENT (DATUM B) MAX B A 5.00 (0.20) C C (DATUM A) C A B 0.05 C NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WHHD-4. THIS PACKAGE IS ALSO FOOTPRINT COMPATIBLE WITH WHHD-5. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP32Arev MIN 3.86 MIN 0.28 MAX 0.50TYP X40 E 32-Lead, Molded Leadless Package (MLP), QUAD, JEDEC MO-220, Variation WHHD-4, 5mm Square Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Ordering Information Part Number Operating Temperature Range FIN424CMLX -30 to +85 C Green FIN425CMLX -30 to +85 C Green PIN #1 ID PIN #1 ID (0.76) (0.25 ) 3.37 MAX 0.20MIN X4 Eco Status Package Packing Method 32-Lead, Molded Leadless Package (MLP), QUAD, JEDEC MO-220, Variation WHHD-4, 5mm Square 32-Lead, Molded Leadless Package (MLP), QUAD, JEDEC MO-220, Variation WHHD-4, 5mm Square Tape and Reel Tape and Reel For Fairchild s definition of Eco Status, please visit: FIN424C / FIN425C Rev

10 FIN424C / FIN425C Rev