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2 Computer Architecture Formulas 1. CPU time = Instruction count x Clock cycles per instruction x Clock cycle time Execution time old 2. Amdahl's Law: Speedup^,,,,,, = ^^.^^.-^^.-^^ =, i t..- ^ ^ Fraction, hanced bxecution time,^ (^ _ Fraction, hanced) + o^^^h.m ^peeaupgnhanced 3. Power^y^^j^ - 1/2 x Capacitive load x Voltage^ x Frequency switched 4. Power^i^,i^ = Current^t^ji^ x Voltage 5. Average memory-access time = Hit time -i- Miss rate x Miss penalty 6. Availability = Mean Time To FaiI/(Mean Time To Fail + Mean Time to Repair) -I r^- ij iir r ij /'i Defects per unit area X Die areav" 7. Die yield = Wafer yield x I 1 -t- ^ 1 where Wafer yield accounts for wafers that are so bad they need not be tested and a is a fitted parameter that approximates the number of masking levels critical to die yield (usually a = 4.0) 8. Misses per instruction - Miss rate x Memory access per instruction 9. Cache index size: l'"**^" = Cache size/(biock size x Set associativity) 10. Means arithmetic (AM), weighted arithmetic (WAM), and geometric (GM): AM = i n n ( 5^ Time,- WAM = ^ Weighty x Time, GM = m Time, = exp - x ^ ln(time,) n where Time, is the execution time for the /th program of a total of n in the workload, Weight, is the weighting of the rth program in the workload. 11. Geometric standard deviation - exp ^ ln(time,) - ln(geometic mean))' Rules of Thumb 1. Amdahl/Case Rule: A balanced computer system needs about 1 MB of main memory capacity and I megabit per second of I/O bandwidth per MIPS of CPU performance /70 Locality Rule: A program executes about 90% of its instructions in 10% of its code. 3. Bandwidth Rule: Bandwidth grows by at least the square of the improvement in latency. 4. 2:1 Cache Rule: The miss rate of a direct-mapped cache of size N is about the same as a two-way setassociative cache of size N/2. 5. Dependability Rule: Design with no single point of failure.

3 In Praise oi Computer Architecture: A Quantitative Approach Fourth Edition "The multiprocessor is here and it can no longer be avoided. As we bid farewell. to single-core processors and move into the chip multiprocessing age. it is great timing for a new edition of Hennessy and Patterson's classic. Few books have had as significant an impact on the way their discipline is taught, and the current edition will ensure its place at the top for some time to come." Luiz Andre Barroso. Google Inc. "What do the following have in common: Beatles' tunes. HP calculators, chocolate chip cookies, and Computer Architecture^ They are all classics that have stood the test of fime." Robert P. Colwell, Intel lead architect "Not only does the book provide an authoritative reference on the concepts that all computer architects should be familiar with, but it is also a good starting point for investigations into emerging areas in the field." Krisztian Flautner, ARM Ltd. "The best keeps getting better! This new edition is updated and very relevant to the key issues in computer architecture today. Plus, its new exercise paradigm is much more useful for both students and instructors." Norman P. Jouppi, HP Labs ""Computer Architecture builds on fundamentals that yielded the RISC revolution, including the enablers for CISC translation. Now. in this new edition, it clearly explains and gives insight into the latest microarchitecture techniques needed for the new generation of multithreaded multicore processors." Marc Tremblay, Fellow & VP, Chief Architect, Sun Microsystems "This is a great textbook on all key accounts: pedagogically superb in exposing the ideas and techniques that define the art of computer organization and design, stimulating to read, and comprehensive in its coverage of topics. The first edition set a standard of excellence and relevance; this latest edition does it again." Milos Ercegovac, UCLA "They've done it again. Hennessy and Patterson emphatically demonstrate why they are the doyens of this deep and shifting field. Fallacy: Computer architecture isn't an essential subject in the information age. Pitfall: You don't need the 4th edition of Computer Architecture." Michael D. Smith. Harvard University

4 "Hennessy and Patterson have done it again 1 The 4th edition is a classic encore that has been adapted beautifully to meet the rapidly changing constraints of "late-cmos-era" technology. The detailed case studies of real processor products are especially educational, and the text reads so smoothly that it is difficult to put down. This book is a must-read for students and professionals alike!" Pradip Bose, IBM "This latest edition of Computer Architecture is sure to provide smdents with the architectural framework and foundation they need to become influential architects of the future." Ravishankar Iyer. Intel Corp. "As technology has advanced, and design opportunities and constraints have changed, so has this book. The 4th edition continues the tradition of presenting the latest in innovations with commercial impact, alongside the foundational concepts: advanced processor and memor>' system design techniques, multithreading and chip multiprocessors, storage systems, virtual machines, and other concepts. This book is an excellent resource for anybody interested in learning the architectural concepts underlying real commercial products." Gurindar Sohi. University of Wisconsin-Madison "I am \ery happy to have my students study computer architecture using this fantastic book and am a little jealous for not having written it myself." Mateo Valero, UPC, Barcelona "Hennessy and Patterson continue to evolve their teaching methods with the changing landscape of computer system design. Smdents gain unique insight into the factors influencing the shape of computer architecmre design and the potential research directions in the computer systems field." Dan Connors. University of Colorado at Boulder "With this revision. Computer Architecture will remain a must-read for all computer architecture smdents in the coming decade " Wen-mei Hwu. University of Illinois at Urbana-Champaign "The 4th edition of Computer Architecture continues in the tradition of providing a relevant and cutting edge approach that appeals to students, researchers, and designers of computer systems. The lessons that this new edition teaches will continue to be as relevant as ever for its readers." David Brooks, Harvard University Architec "With the 4th edition, Hennessy and Patterson ha\e shaped Computer ture back to the lean focus that made the 1st edition an instant classic." Mark D. Hill, University of Wisconsin-Madison

5 Computer Architecture A Quantitative Approach Fourth Edition

6 John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a Fellow of the IEEE and ACM, a member of the National Academy of Engineering and the National Academy of Science, and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. In 1981, he started the MIPS project at Stanford with a handful of graduate students. After completing the project in 1984, he took a one-year leave from the university to cofound MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998,focusing on microprocessors for the embedded marketplace. As of 2006, over 500 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. David A. Patterson has been teaching computer architecture at the University of California, Berkeley since joining the faculty in 1977, where he holds the Pardee Chair of Computer Science. His teaching has been honored by the Abacus Award from Upsilon Pi Epsilon, the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award for contributions to RISC and shared the IEEE Johnson Information Storage Award for contributions to RAID. He then shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair ofthecs division in the Berkeley EECS department, as chair of the Computing Research Association,and as President of ACM.This record led to a Distinguished Service Award from CRA. At Berkeley, Patterson led the design and implementation of RISC I, likely the first VLSI reduced instruction set computer.this research became the foundation of the SPARC architecture, currently used by Sun Microsystems, Fujitsu, and others. He was a leader of the Redundant Arrays of Inexpensive Disks (RAID) project, which led to dependable storage systems from many companies. He was also involved in the Network of Workstations (NOW) project, which led to cluster technology used by Internet companies.these projects earned three dissertation awards from the ACM. His current research projects are the RAD Lab, which is inventing technology for reliable, adaptive, distributed Internet services, and the Research Accelerator for Multiple Processors (RAMP) project, which is developing and distributing low-cost, highly scalable, parallel computers based on FPGAs and open-source hardware and software.

7 Computer Architecture A Quantitative Approach Fourth Edition John L Hennessy Stanford University David A. Patterson University of California at Berkeley DAIHOCQUOCGIAHANQI^ TRUt^G TAM THONG TIN THU VIEN With Contributions by Andrea C. Arpaci-Dusseau University of Wisconsin-Madison Remzi H. Arpaci-Dusseau University of Wisconsin-Madison Krste Asanovic Massachusetts InstHute of Technology Robert P. Colwell R&E Colwell & Associates, Inc Thomas M. Conte North Carolina State University Jose Duato Universitat Politecnica de Valencia and Simula Diana Franklin California Polytechnic State University. San Luis Obispo David Goldberg Xerox Palo Alto Research Center Wen-mei W. Hwu University of Illinois at Urbana-Champaign Norman P. Jouppi HP Labs Timothy M. Pinkston University of Southern California John W. Sias University of Illinois at Urbana-Champaign David A. Wood University of Wisconsin-Madison ELSEVIER Amsterdam Boston Heidelberg London New York Oxford Paris San Diego San Francisco Singapore Sydney Tokyo l< MORGAN KAUFMANN PUBLISHERS

8 Puhllsher Denise E. M. Penrose Project Manujier Dusty Friedman, The Book Company In-housc Senior Project Manager Brandy Lilly Developmental Editor Nate McFadden Editorial Assistant Kimberlee Honjo Cover Design Elisabeth Seller and Ross Carron Design Cover Image Richard lansons Collection: Lonely Planet Images Composition Nancy Logan Text Design: Rebecca Evans & Associates Technical Illustration David Ruppe. Impact Publications Copy-editor Ken Delia Penta Proofreader Jamie Thaman Indexer Nancy Ball Printer Maple-Vail Book Manufacturing Group Morgan Kaulmann Publishers is an Imprint of Elsevier 500 Sansnme Street. Suite 400. San Francisco. CA This book is printed on acid-ivee paper , 2007 by Elsevier, Inc. All rights reserved. Published Fourth edition 2007 Designations used by companies to distinguish their products are often claimed as trademarks or registered trademarks. In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. Permissions may be sought directly from Elsevier's Science & Technology Rights Department in Oxford. UK: phone: (+44) fax: (+44) permissions@elsevier. com. You may also complete your request on-line via the Elsevier Science homepage ihttp:// etsevier.com). by selecting "Customer Support" and then "Obtaining Permissions." Library of Congress Cataloging-in-Publication Data Hennessy, John L. Computer architecture : a quantitative approach / John L. Hennessy. David A. Patterson : with contributions by Andrea C. Arpaci-Dusseau... [et al.]. 4th ed. p.cm. includes bibliographical references and index. ISBN 13: ISBN 10: (pbk. : alk. paper) ^ 1. Computer architecture. I. Patterson. David A. II. Arpaci-Dusseau, Andrea C. III. Title. QA76.9.A73P '2 dc For all information on all Morgan Kaufmann publications. visit our website at n \v^v.nlkp.conl or n\v\v.t)ooks.elsevier.com Printed in the United States of America Working together to grow libraries in developing countries \v\v\v.bookaid.org ELSEVIER BOOK AID International Sabre Foundation

9 To Andrea, Linda, and our four sons

10 Foreword by Fred Weber, President and CEO ofmetoram, Inc. I am honored and privileged to write the foreword for the fourth edition of this most important book in computer architecture. In the first edition, Gordon Bell, my first industry mentor, predicted the book's central position as the definitive text for computer architecture and design. He was right. I clearly remember the excitement generated by the introduction of this work. Rereading it now. with significant extensions added in the three new editions, has been a pleasure all over again. No other work in computer architecture frankly, no other work I have read in any field so quickly and effortlessly takes the reader from ignorance to a breadth and depth of knowledge. This book is dense in facts and figures, in rules of thumb and theories, in examples and descriptions. It is stuffed with acronyms, technologies, trends, formulas, illustrations, and tables. And, this is thoroughly appropriate for a work on architecture. The architect's role is not that of a scientist or inventor who will deeply study a particular phenomenon and create new basic materials or techniques. Nor is the architect the craftsman who masters the handling of tools to craft the finest details. The architect's role is to combine a thorough understanding of the state of the art of what is possible, a thorough understanding of the historical and current styles of what is desirable, a sense of design to conceive a harmonious total system, and the confidence and energy to marshal this knowledge and available resources to go out and get something built. To accomplish this, the architect needs a tremendous density of information with an in-depth understanding of the fundamentals and a quanfitative approach to ground his thinking. That is exactly what this book delivers. As computer architecture has evolved from a world of mainframes, minicomputers, and microprocessors, to a world dominated by microprocessors, and now into a world where microprocessors themselves are encompassing all the complexity of mainframe computers Hennessy and Patterson have updated their book appropriately. The first edition showcased the IBM 360. DEC VAX, and Intel 80x86. each the pinnacle of its class of computer, and helped introduce the world to RISC architecture. The later editions focused on the details of the 80x86 and RISC processors, which had come to dominate the landscape. This latest edition expands the coverage of threading and multiprocessing, virtualization IX

11 Computer Architecture and memory hierarchy, and storage systems, giving the reader context appropriate to today's most important directions and setting the.stage for the next decade of design. It highlights the AMD Opteron and SUN Niagara as the best examples of the x86 and SPARC (RISC) architectures brought into the new world of multiprocessing and system-on-a-chip architecture, thus grounding the art and science in real-world commercial examples. The first chapter, in less than 60 pages, introduces the reader to the taxonomies of computer design and the basic concerns of computer architecture, gives an overview of the technology trends that drive the industry, and lays out a quantitative approach to using all this information in the art of computer design. The next two chapters focus on traditional CPU design and give a strong grounding in the possibilities and limits in this core area. The final three chapters build out an understanding of system issues with multiprocessing, memory hierarchy, and storage. Knowledge of these areas has always been of critical importance to the computer architect. In this era of system-on-a-chip designs, it is essential for every CPU architect. Finally the appendices provide a great depth of understanding by working through specific examples in great detail. In design it is important to look at both the forest and the trees and to move easily between these views. As you work through this book you will find plenty of both. The result of great architecture, whether in computer design, building design or textbook design, is to take the customer's requirements and desires and return a design that causes that customer to say, "Wow, I didn't know that was possible." This book succeeds on that measure and will, I hope, give you as much pleasure and value as it has me.

12 Contents Foreword Preface Acknowledgments ix xv xxiii Chapter 1 Fundamentals of Computer Design 1.1 Introduction Classes of Computers Defining Computer Architecture Trends in Technology Trends in Power in Integrated Circuits Trends in Cost Dependability Measuring,Reporting,and Summarizing Performance ^ Quantitative Principles of Computer Design Putting It All Together: Performance and Price-Performance Fallacies and Pitfalls Concluding Remarks Historical Perspectives and References 54 Case Studies with Exercises by Diana Franklin 55 Chapter 2 Instruction-Level Parallelism and Its Exploitation 2.1 Instruction-Level Parallelism;Concepts and Challenges Basic Compiler Techniques for Exposing ILP Reducing Branch Costs with Prediction Overcoming Data Hazards with Dynamic Scheduling Dynamic Scheduling: Examples and the Algorithm Hardware-Based Speculation Exploiting ILP Using Multiple Issue and Static Scheduling 114 XI

13 xii Contents 2.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation Advanced Techniques for Instruction Delivery and Speculation Putting It All TogetherThe Intel Pentium Fallacies and Pitfalls Concluding Remarks Historical Perspective and References 141 Case Studies with Exercises by Robert PColwell 142 Chapter 3 Limits on Instruction-Level Parallelism 3.1 Introduction Studies ofthe Limitations of ILP Limitations on ILP for Realizable Processors Crosscutting Issues: Hardware versus Software Speculation Multithreading: Using ILP Support to Exploit Thread-Level Parallelism Putting It All Together: Performance and Efficiency in Advanced Multiple-Issue Processors Fallacies and Pitfalls Concluding Remarks Historical Perspective and References 185 Case Study with Exercises by Wen-mei W. Hwu and John W. Sias 185 Chapter4 Multiprocessors and Thread-Level Parallelism 4.1 Introduction Symmetric Shared-Memory Architectures Performance of Symmetric Shared-Memory Multiprocessors Distributed Shared Memory and Directory-Based Coherence Synchronization:The Basics Models of Memory Consistency: An Introduction Crosscutting Issues Putting It AIITogether:The SunTl Multiprocessor Fallacies and Pitfalls Concluding Remarks Historical Perspective and References 264 Case Studies with Exercises by David A.Wood 264 Chapter 5 Memory Hierarchy Design 5.1 Introduction Eleven Advanced Optimizations of Cache Performance Memory Technology and Optimizations 310

14 Contents ^ xiir 5.4 Protection:Virtual Memory and Virtual Machines 5.5 Crosscutting Issues: The Design of Memory Hierarchies 5.6 Putting It All Together: AMD Opteron Memory Hierarchy 5.7 Fallacies and Pitfalls 5.8 Concluding Remarks 5.9 Historical Perspective and References Case Studies with Exercises by Norman RJouppi Chapter6 Storage Systems 6.1 Introduction 6.2 Advanced Topics in Disk Storage 6.3 Definition and Examples of Real Faults and Failures 6.4 I/O Performance, Reliability Measures,and Benchmarks 6.5 A Little Queuing Theory 6.6 Crosscutting Issues 6.7 Designing and Evaluating an I/O System The Internet Archive Cluster 6.8 Putting It All Together: NetApp FAS6000 Filer 6.9 Fallacies and Pitfalls 6.10 Concluding Remarks 6.11 Historical Perspective and References Case Studies with Exercises by Andrea C. Arpaci-Dusseau and Remzi H. Arpaci-Dusseau Appendix A Pipelining: Basic and Intermediate Concepts Introduction The Major Hurdle of Pipelining Pipeline Hazards How Is Pipelining Implemented? What Makes Pipelining Hard to Implement? Extending the MIPS Pipeline to Handle Multicycle Operations Putting It All TogetherThe MIPS R4000 Pipeline Crosscutting Issues Fallacies and Pitfalls Concluding Remarks A-2 A-11 A-26 A-37 A-47 A-56 A-65 A-75 A-76 A-77 Appendix B Instruction Set Principles and Examples B.I Introduction B.2 Classifying Instruction Set Architectures B.3 Memory Addressing B.4 Type and Size of Operands B.5 Operations in the Instruction Set B-2 B-3 B M4

15 xiv Contents B.6 Instructions for Control Flow B.7 Encoding an Instruction Set B.8 Crosscutting lssues:the Role of Compilers B.9 Putting It AllTogether:The MIPS Architecture B.10 Fallacies and Pitfalls B.I 1 Concluding Remarks B.I 2 Historical Perspective and References B-16 B-21 B-24 B-32 B-39 B-45 B-47 Appendix C Review of Memory Hierarchy C.I Introduction C.2 Cache Performance C.3 Six Basic Cache Optimizations C.4 Virtual Memory C.5 Protection and Examples of Virtual Memory C.6 Fallacies and Pitfalls C.7 Concluding Remarks C.8 Historical Perspective and References C-2 C-15 C-22 C-38 C-47 C-56 C-57 C-58 Appendix D Appendix E Companion CD Appendices Embedded Systems Updated by Thomas M. Conte Interconnection Networks Revised by TItvothy M. Pinkston and Jose Duato Appendix F Vector Processors Revised by Krste Asanovic Appendix G Hardware and Software for VLIW and EPIC ^ Appendix H Large-Scale Multiprocessors and Scientific Applications Appendix I Computer Arithmetic by David Goldberg Appendix J Survey of Instruction Set Architectures Appendix K Historical Perspectives and References Online Appendix {textbooks.elsevier.com/ ) Appendix L Solutions to Case Study Exercises References Index R-1 1-1