HPC in the Loop and Cyber-Physical Systems

Transcription

1 High-Performance and Embedded Architecture and Compilation HPC in the Loop and Cyber-Physical Systems Marc Duranton HiPEAC vision coordinator CEA Fellow Commissariat à l énergie atomique et aux énergies alternatives Post-H202 vision for HPC workshop Sunday, 24 June 2018, Frankfurt

2 HiPEAC = High-Performance and Embedded Architecture and Compilation HiPEAC's mission is to steer and increase the European research in the area of high-performance and embedded computing systems, And stimulate cooperation between: a) academia and industry b) computer architects and tool builders. 3

3 HIPEAC HISTORY HiPEAC5 HiPEAC4 HiPEAC3 HiPEAC2 HiPEAC

4 MEMBERSHIP 13 partners, 522 members, 99 associated members, 423 affiliated members and 855 affiliated PhD students from 363 institutions in 40 countries. Membership is free of charge. Associated hipeac.net/members/stats/map members: 76 Total:

5 Conference ACACES summer school Computing systems weeks Stimulating collaboration HiPEAC Jobs WP2 Connecting the communities HIPEAC STRUCTURE Consultation meetings HiPEAC Vision 2019 Disseminating the HiPEAC Vision WP4 Roadmapping WP1 Growing the communities Membership management Growing the industrial community Growing the innovator community Growing the stakeholder community Growing the new member states membership WP3 Dissemination Communications Road show Awards Website Management Project management Financial management Industrial Advisory board 6

6 Conference ACACES summer school Computing systems weeks Stimulating collaboration HiPEAC Jobs WP2 Connecting the communities HIPEAC STRUCTURE Consultation meetings HiPEAC Vision 2019 Disseminating the HiPEAC Vision WP4 Roadmapping WP1 Growing the communities Membership management Growing the industrial community Growing the innovator community Growing the stakeholder community Growing the new member states membership WP3 Dissemination Communications Road show Awards Website Management Project management Financial management Industrial Advisory board 7

7 THE HIPEAC VISION The last HiPEAC Vision Document was published in January The next version is on-going (expect printed version for beginning 2019) One of its aim is to drive the community and to help defining the next European calls in ICT The 2017 version is available at: 8

8 HiPEAC Vision 9

9 The best way to predict the future is to invent it. Alan Kay 11

10 OUTLINE Algorithm Applications Data Hardware Language 12

11 OUTLINE Algorithm Applications Data Hardware Language 13

12 Entering in Human and Machine collaboration era 14

13 ENABLED BY ARTIFICIAL INTELLIGENCE (AND DEEP LEARNING) Artificial Intelligence is changing the man-machine interaction natural interfaces, intelligent behavior Image and situation understanding Voice recognition and synthesis Direct interfacing with the world Creating the bridge between cyber and real world decision taking 15

14 ENABLING EDGE INTELLIGENCE C 2 PS: COGNITIVE ( CYBERNETIC* AND PHYSICAL ) SYSTEMS Smart sensors Enabling Intelligent data processing at the edge: Fog computing Edge computing Stream analytics Fast data New services Cyber Physical Entanglement Systems Cloud / HPC Processing, Abstracting Understanding as soon as possible Data Analytics / Cognitive computing Internet of Things Big Data Transforming data into information as early as possible True collaboration between edge devices and the HPC/cloud ensuring: - Data security / Privacy - Lower bandwidth - Better use of HPC/cloud * As defined by Norbert Wiener: how humans, animals and machines control and communicate with each other. 16

15 LOOKING FORWARD EXAMPLE OF A CPS SYSTEM Direct Brain Computer Interface (BCI) Here allowing a paraplegic to walk again One current limitation: Required processing power need supercomputer in a box From CEA-Clinatec 17

16 Embedded intelligence needs local high-end computing System should be autonomous to make good decisions in all conditions Safety will impose that basic autonomous functions should not rely on always connected or always available Cyber-physical applications will require high performance level of computing HPC in a Box. 18

17 Embedded intelligence needs local high-end computing System should be autonomous to make good decisions in all conditions Safety will impose that basic autonomous functions should not rely on always connected or always available 25 years Current embedded systems are HPC systems of few decades ago 19

18 CYBER-PHYSICAL SYSTEMS Imposes the timing Observations Environment Actions 20

19 1948: NORBERT WIENER 21

20 BUT COMPUTING SYSTEMS WERE NOT DESIGNED FOR CPS SYSTEMS In nearly all hardware and software of computing systems: Time is abstracted or even not present at all Very few programming languages can express time or timing constraints All is done to have the best average performance, not predictable performances Caches, out of order execution, branch prediction, speculative execution, (Hidden) compiler optimization, call to (time) unspecified libraries Energy is also left out of scope This can have impact on data movement, optimizations With predictability: On-Time processing Interaction with external world are second priorities vs. computation Done with interrupts (introduced as an optimization, eliminating unproductive waiting time in polling loops) which were design to be exceptional events Etc. 22

21 3 PILLARDS OF FUTURE HPC Simulation Data Machine Learning Intertwined with CPS requirements 23

22 SIMULATION Specialist Environment Algorithm Parameters Simulation Human knowledge defines the processing Large algorithmic complexity Error? High precision floating point Large set of output data Von Neumann architecture Data SIMULATION = MODEL FOR PREDICTION 24

23 FROM CPS TO DIGITAL TWIN Observations Error? Simulation Observations Environment Actions SIMULATION SHOULD BE FASTER THAN REALITY FOR PREDICTION 25

24 BIG DATA Specialist Human knowledge refines the processing Large set of input data Mappable on Von Neumann Architecture Data Analytics Big Data Observations Environment Model Specialist 26

25 MACHINE LEARNING (DEEP LEARNING) LEARNING PHASE Specialist Human defines the learning data set, not the algorithm Large set of input data for learning phase Low precision floating point Large number of operations (Stochastic) gradient descent Labelled data set Learning phase 27

26 MACHINE LEARNING (DEEP LEARNING) INFERENCE PHASE Low precision arithmetic Medium number of operations Co-location computing and storage ( computing in memory ) Should satisfy the application non-functional requirements Environment Inference phase 28

27 DEEP LEARNING AND VOICE RECOGNITION 29

28 2017: GOOGLE S CUSTOMIZED TPU HARDWARE required to increase energy efficiency with accuracy adapted to the use (e.g. float 16) Google s TPU2 : 11.5 petaflops 16 of machine learning number crunching (and guessing about 400+ KW, 100+ GFlops 16 /W) From Google Peta = = million of milliard 31

29 Goal REINFORCEMENT LEARNING: DYNAMIC PROGRAMMING + DEEP LEARNING Rewards Observations Environment Agent Actions Learns to maximize rewards Respond to action 33

30 ALPHAGO ZERO: SELF-PLAYING TO LEARN From doi: /nature24270 (Received 07 April 2017) 34

31 ALPHAZERO: SELF-PLAYING TO LEARN REINFORCEMENT LEARNING: DYNAMIC PROGRAMMING + DEEP LEARNING 35

32 ALPHAZERO: COMPUTING RESOURCES From Google Deepmind Peta = = million of milliard 36

33 REINFORCEMENT LEARNING: DYNAMIC PROGRAMMING + DEEP LEARNING Goal Mixed precision arithmetic Very high number of operations Large internal data manipulation Rewards Mainly co-location computing and storage ( computing in memory ) High level of parallelism Minimization of energy functions Observations Environment Agent Actions Learns to maximize rewards Respond to action 37

34 REINFORCEMENT LEARNING: DYNAMIC PROGRAMMING + DEEP LEARNING Goal Rewards Observations Agent Actions Learns to maximize rewards Respond to action 38

35 OUTLINE Algorithm Applications Data Hardware Language 39

36 WHAT WILL BE THE NEXT TECHNOLOGY? And after CMOS? 40

37 Technology evolution Silicon Quantum bits 22FD 12FD FDSOI Next Gen 20nm L G Si channel ISPD SiC RSD 25nm T BOX 20nm L G Si channel ISPD SiC RSD Non planar / trigate / stacked Nanowires 25nm T BOX 28nm 14nm Alternative to scaling and diversification 10nm 2017 FinFET nm Disruptive scaling Hybrid logic 5nm Steep slope devices Mechanical switches Si Quantum bits Monolithic 3D for 3D VLSI 43

38 EXPLORE NEW WAYS AS ALTERNATIVE TO SILICON New technologies Quantum computing Printed/flexible electronics Carbon nanotubes Photonics Neuro inspired (nano) technologies Reservoir computing Adiabatic computing MEMS for computing Synthetic biology, blob computing Swarm computing Symbiotic computing Analogue/physic/hybrid computing 44

39 NON VOLATILE MEMORIES PCM MRAM Magnetic effect Can change the structure of memory hierarchy? + 64/128 addressing scheme Do we still need files? Direct access of objects CBRAM GST GeTe GST + HfO 2 OXRAM Ag / GeS 2 Thermal effect TiN/HfO 2 /Ti/TiN Electronic effect oxygen vacancies Electrochemical effect 45

40 The problem: IT projected to challenge future electricity supply From Total Consumer Power Consumption Forecast, Anders S.G. Andrae, October

41 COST OF MOVING DATA -> COMPUTING IN MEMORY Source: Bill Dally, «To ExaScale and Beyond» 49

42 NEUROMORPHIC ACCELERATOR: DYNAPS-SL (INI-ZURICH) Neuram3 1 st chip IBM True North Technology 28 nm FDSOI 28nm CMOS Supply Voltage 1 V 0.7V Neuron Type Analog Digital Neurons per core Core Area 0.36 mm mm 2 Computation Parallel processing Time multiplexing Fan In/Out 2k/8k 256/256 Synaptic Operation per Second per Watt 300 GSOPS/W *1 46 GSOPS/W Energy per synaptic event <2 pj *2 10 pj Energy per spike <0.375 nj *3 3.9 nj 1 At 100Hz mean firing rate, by appending 4 local-core destinations per spike, 400 k events will be broadcast to 4 cores with 25% connectivity per event. 400 k x 1 k x 25% / 300 μ W = 300 GSOPS/W 2 In case of 25% match in each core, energy per synaptic event = energy per broadcast / (256*25%) =120pJ/64 = 2 pj 3 Energy per spike = total power consumption / spikes numbers = 300 uw/800 k = nj 50

43 OFF-CHIP PHOTONICS Photonics: cost in sending information, nearly nothing in transmission Optical Transceiver Chip D IC Chip B Chip C Fiber Ferrule PIC Driver / TIA Micropillars Si interposer or laminate substrate IC PCB S1 Off board: AOC, optical modules Off chip: Optical I/O Time 52

44 IN-PACKAGE PHOTONICS Thermal Dissipation Optical Transceiver Chip A Chip D Chip B Chip C Through Silicon Via Primary I/O Cu pillars Signal Thermal Dissipation Computing Cores Signal Digital Cu pillars & proximity lines Tx/Rx photo diode RF Cu pillars Integr. Rx/Tx Photonic Interposer Substrate modul RAM Light source Power Power Power Power Laser S1 S2 Off board: AOC, optical modules Off chip: Optical I/O Optical network in package 53

45 Polynomial transformation of NP-hard problems for Quantum annealers Adiabatic quantum computation (Farhi et al. in 2000) as an alternative quantum model for solving NP-hard optimization problems considered classically insoluble! D-Wave System Hardware The system solves only one binary optimization problem : Embedding a realistic problem instance : Physical qubits on each colored path represent one logical qubit UC-F16/presentations/D-Wave.pdf Problem: Qubit efficiency! Possible solution : Search for an efficient operating path for an adiabatic quantum computer Slide from Christian Gamrat Daniel Vert - Daniel.vert2@cea.fr 54

46 QUANTUM HARDWARE ARCHITECTURE AND SYSTEM Importance of studying the full stack system architecture to connect quantum devices with conventional computing systems Hardware level System stack The system stack from low level quantum hardware to high level algorithms Overview of a quantum computer architecture. Pink is quantum, Green is the interface and Blue parts are conventional Fu et al A Heterogeneous Quantum Computer Architecture, Proc. ACM, From work by Slide from Christian Gamrat 55

47 FUSING PARADIGMS AT HARDWARE LEVEL At the hardware level, the good old Von Neumann/ CMOS partnership can act as a computing substrate Acting as coordination / communication node Allowing Hardware / Software integration Neuro Engine Quantum Engine Qubits on Silicon Maurand et al, Nature Com., Jul Coordination Engine Von Neumann style CMOS Technology binary data Graphical Engine Decision Engine NVM Synapses on Silicon Semantical Engine Numerical Engine Numerical Neuro Quantum Graphics Engine engine engine engine Physical and logical interface layer Slide from Christian Gamrat CMOS Substrate D. Roclin et al, IEEE NanoArch,

48 COORDINATE PARADIGMS AT SOFTWARE LEVEL A sequential program (running on the coordinator) distributes tasks to engines Accelerator as services (J. Cong) Tasks are distributed to computing engines Instruction streams Supervised Learning Unsupervised Learning Quantum Engine Why would we want that? Domain specific expressiveness Run hard tasks, speedup NP problems Provide cognitive functions Stefanini et al. Frontiers Neuroinformatics August 2014 Valiron et al., Programming the Quantum Future, Commun. ACM, vol. 58, no. 8, pp , Jul Fu et al. Proc. ACM, May

49 OUTLINE Algorithm Applications Data Hardware Language 58

50 PARALLELISM AND SPECIALIZATION ARE NOT FOR FREE Frequency limit parallelism Energy efficiency heterogeneity Ease of programming

51 PARALLELISM AND SPECIALIZATION ARE NOT FOR FREE Frequency limit parallelism Energy efficiency heterogeneity Ease of programming

52 PARALLELISM AND SPECIALIZATION ARE NOT FOR FREE Frequency limit parallelism Energy efficiency heterogeneity Ease of programming

53 Managing complexity Cognitive solutions for complex computing systems: Using AI and optimization techniques for computing systems Creating new hardware Generating code Optimizing systems Similar to Generative design for mechanical engineering

54 USING AI FOR MAKING CPS SYSTEMS: GENERATIVE DESIGN APPROACH The user only states desired goals and constraints -> The complexity wall might prevent explaining the solution Autodesk Motorcycle swingarm: the piece that hinges the rear wheel to the bike s frame 64

55 EXAMPLE: DESIGN SPACE EXPLORATION FOR DESIGN MULTI-CORE PROCESSORS 1 (2010) Ne-XVP project Follow-up of the TriMedia VLIW ( -XVP ) 1,105,747,200 heterogeneous multicores in the design space 2 millions years to evaluate all design points AI inspired techniques allowed to reduce the induction time to only few days => x16 performance increase 1 M. Duranton et all., Rapid Technology-Aware Design Space Exploration for Embedded HeterogeneousMultiprocessors in Processor and System-on-Chip Simulation, Ed. R. Leupers,

56 AUTOML AND OTHER PROGRAM GENERATORS 66

57 2017: GOOGLE; USING DEEP LEARNING TO DESIGN DEEP LEARNING Neural Architecture Search, using a recurrent neural network to compose neural network architectures using reinforcement learning on CIFAR-10 (character recognition) From arxiv: v2, Barret Zoph, Quoc V. Le Google Brain 67

58 PROGRAMMING 2.0: LET THE COMPUTER DO THE JOB: Describing what the program should accomplish, rather than describing how to accomplish it as a sequence of the programming language primitives. For example, describe the concurrency of an application, not how to parallelize the code for it. (Good) compilers know better about architecture than humans, they are better at optimizing code 68

59 CONCLUSION: WE LIVE AN EXCITING TIME! 69

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61 Thank you for your attention Centre de Grenoble 17 rue des Martyrs Grenoble Cedex Centre de Saclay Nano-Innov PC Gif sur Yvette Cedex