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1 NAOSITE: Nagasaki University's Ac Title Author(s) Otimal us caacitance design for ower architecture Ae, Seiya; Hirokawa, Masahiko; Sho Citation EPE-PEMC 8, Issue Date 8-9 URL Right htt://hdl.handle.net/69/829 (c)8 IEEE. Personal use of this ermission to rerint/reulish thi uroses or for creating new collec servers or lists, or to reuse any c works must e otained from the IEE This document is downloaded htt://naosite.l.nagasaki-u.ac.j

2 Otimal Bus Caacitance Design for System Staility in On-Board Distriuted Power Architecture Seiya Ae *, Masahiko Hirokawa **, Masahito Shoyama * and Tamotsu Ninomiya *** * Kyushu University, 744, Motooka, Nishi-ku, Fukuoka, , Jaan ** TDK Cororation, , Higashi-Ohwada, Ichikawa, Chia, , Jaan *** Nagasaki University, 1-14, Bunkyo-Machi, Nagasaki, , Jaan Astract Recently, the distriuted ower system is mainly used for the ower suly system which requires the low-voltage / high-current outut. The distriuted ower system consists of us converter and POL. The most imortant factor is the system staility in us architecture design. The overla etween the outut imedance of us converter and inut imedance of POL causes system instaility, and it has een an actual rolem. Increasing the us caacitor, system staility can e reduced easily. However, due to the limited sace on the system oard, increasing of us caacitors is imractical. The urgent solution of the issue is desired strongly. This aer resents the outut imedance design for on-oard distriuted ower system y means of three control schemes of us converter. The outut imedance eak of the us converter and the inut imedance of the POL are analyzed, and it is conformed y exerimentally for staility criterion. Furthermore, the otimal intermediate us caacitance design for system staility is roosed. Keywords Distriuted ower system, us converter design, outut imedance, intermediate us caacitance. I. INTRODUCTION Various LSI is used in the telecommunication alication equiments and the driving voltage is various. On the other hand, increase of load current is also remarkale y advanced function of LSI. Since the resent LSI is designed in accordance with semiconductor manufacture technology, the tolerance level of oeration voltage is very narrow. Consequently, the voltage dro y the wiring imedance of ower line causes malfunction of LSI. In order to reduce the malfunction of LSI y the voltage dro, it is roosed that the converter is arranging very close to the LSI. This converter is called POL. Thus, the ower suly system which requires the low-voltage / high-current outut has een changing from conventional centralized ower system to distriuted ower system. The distriuted ower system consists of first-stage isolated DC-DC converter as a us converter and secondstage non-isolated DC-DC converter as a POL. However, the instaility henomenon in a distriuted ower system is osing a rolem recently. This is instaility henomenon resulting from overlaing etween the outut imedance of us converter and the inut imedance of POL. Increasing the us caacitor, system staility can e reduced easily. However, due to the limited sace on the system oard, increasing of us caacitors is imractical. The urgent solution of the issue is desired strongly, and the various discussion of system staility has een reorted[1-8]. Then, we also have reorted the detailed discussion of system staility y control schemes of us converter (Un-regulated, Semiregulated and Full-regulated)[9-14]. However, so far, the detailed discussion of ractical design and the otimal intermediate us caacitance design of us converter aout on-oard distriuted ower system has not een reorted. This aer resents the otimal design of us converter for on-oard distriuted ower system y means of three control schemes of us converter. II. DISCRIMINATION OF STABILITY Figure 1 shows the distriuted ower system consisting of us converter and POL. Even if each converter has stale oeration, the instaility henomenon may occur y connecting two converters in series. Bus converter and POL have inut-to-outut voltage transfer function Gv(s) and Gv(s), resectively. The overall inut-tooutut voltage transfer function Gvv(s) is given following equation; Gv () s Gv () s Gvv () s (1) 1 Zo( s)/ Zin( s) where Zo (s) is the outut imedance of us converter, and Zin(s) is the inut imedance of POL. From Eq. (1), the inut and outut imedance is greatly concerned with the system staility. The staility of closed-loo system is decided with the characteristics equation 1+Zo(s)/Zin(s). This means relation etween Zo(s) and Zin(s) decides the system staility. This system may ecome unstale when oth imedances are overlaed, as shown in Fig. 2 (a). It is necessary to eliminate this imedance overla for system staility. However, eliminating this imedance overla for all frequency range is very difficult. 12V 1.5V/3A POL Load 48V 2.5V/A POL Load Bus Converter 3.3V/A POL Load Fig. 1. On-oard distriuted ower system /8/$25. c 8 IEEE 41

3 On the other hand, it may have stale oeration even if oth imedances are overlaed. This is ecause the hase margin ecomes large under the influence of the inut imedance. When the andwidth of POL is enough wider than the andwidth of us converter, if the eak value of outut imedance ecomes almost equal to the steady-state value of inut imedance Zin() as shown in Fig. 2 (), then this system ecomes staility limit as shown in Fig. 2 (). Moreover, this system ecomes unstale if the eak value of outut imedance exceeds Zin(). From mentioned aove consideration, the new staility criterion can e defined as follows[15]. Zin () Zo _ eak : Stale Zin () Zo _ eak : Unstale III. IMPEDANCE ANALYSIS The half-ridge converter with the most oular circuit of the ower-stage is used as a us converter, and the synchronous uck converter with the most oular circuit is used as POL. Figure 3 and 4 show the circuit diagrams, resectively. The outut imedance of us converter and the inut imedance of POL can e derived y alying the stage sace averaging method[16,17]. A. Inut Imedance At first, the low-frequency value Zin() of inut imedance is estimated. The inut imedance of POL can e derived as following equation[18]. Zin Zo Foridden Region Unstale (a) Conventional discrimination. 1 1 T () s 1 1 (2) Zin() s ZN ()1 s T () s ZD ()1 s T () s From Eq. (2), the low-frequency value of inut imedance Zin() is given y following equation. R rl Zin() log ( db ) ( db) 2 (3) D Zin() has minimum value at rated load, so the estimation of Zin() must e at rated load. Next, the outut imedance is examined. B. Outut Imendance The outut imedance of us converter can e derived as following equations. Oen loo 2 slcr c sl Crr c r Zo() s (4) 2 slc scrl r 1 c Closed loo Zo() s Zoc() s (5) 1 T ( s) where, T() s kpwm Gdv () s (6) () Vs G 1 dv s sc rc (Vs=Vin/2n) (7) P() s P s s L C sc r r (8) 2 () L 1 c k : sense gain roducts error am. gain, PWM : gain of the comarator. In oen loo case, the eak frequency is the same resonant frequency f of the loo gain T(s) as shown in Fig. 5, and the eak value of the outut imedance can e derived from Eq. (4). Vin n : 1 rl C rc + - v Zin Foridden Region Fig. 3. Bus converter. Zo Stale V Lo rl Co rc R + vo - () New discrimination. Fig. 2. Staility discrimination. Fig. 4. Point of Load th International Power Electronics and Motion Control Conference (EPE-PEMC 8)

4 Z o_ eak C r r c In closed loo case, the outut imedance eak moves to crossover frequency fc as shown in Fig. 5. In this instant the eak value of the closed loo outut imedance can e derive following equation. Zoc _ eak () C1 rc r where, T() kpwm Vs (11) Moreover, from transfer function of loo gain, the crossover frequency fc is exressed as follows y means of eak frequency f of loo gain. fc 1 f (12) From Eq. () (12), the eak value of closed loo outut imedance is exressed as follows. Zoc _ eak (13) 2 f c C rc r L f As shown in Eq. (13), if fc is equal to f, it ecomes the same as Eq(9). Therefore, the eak value of outut imedance is calculale y means of Eq. (13). IV. (9) OUTPUT IMPEDANCE SPECIFICATION The outut imedance characteristic of each control shames is different, and each us converter has different oeration. Therefore, the outut imedance design suitale for the feature of each control method is required. From now, the outut imedance design for each control shames is considered. A. Un-regulated In un-regulated case, the outut imedance is the same as oen-loo outut imedance ecause of this control method has no control loo. In order to reduce the eak value of outut imedance, it is effective to make inductance small or to enlarge caacitance. Loo Gain Zo_oen Zo_close f fc Fig. 5. Outut imedance eak. Generally, un-regulated us converter is oerated at maximum duty ratio. Therefore, the inductor of the us converter can e reduced as small as ossile to reduce the system instaility. The eak value of outut imedance is reducing with small inductor. Figure 6 shows the exerimental result of the relation etween the outut imedance and inductance. Moreover, Fig. 7 shows the analytical and exerimental results of the relation etween the eak value of outut imedance and inductance. Both results agreed well. As mentioned aove, the eak of imedance is easily otained from Eq. (13). However, this method deends on converter toology that has a doule-ended circuit at secondary side such as half-ridge or full-ridge. Moreover, there are some limits such that high accurate inut voltage or a POL with wide inut range. B. Semi-regulated Semi-regulated us converter has a control loo. However, regulation is related to variation of inut voltage, therefore the outut imedance is same as unregulated case. In this case, the duty ratio is changed, and the inductor of the us converter cannot e reduced. Therefore, very large us caacitor is needed to reduce the eak value of outut imedance. Figure 8 shows the exerimental result of the relation etween the outut imedance and caacitance. Moreover, Fig. 9 shows the analytical and exerimental results of the relation etween the eak value of outut imedance and caacitance. Both results agreed well. Outut Imedance (db) Outut Imedance (db) Inductance --> Small 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 3 Fig. 6. Inductance and outut imedance. Exeriment Theory Inductance (H) Fig. 7. Inductance and eak value of Zo th International Power Electronics and Motion Control Conference (EPE-PEMC 8) 43

5 In semi-regulated case, essentially it ecomes very unstale and we have found that the demerit is very large caacitors are needed at the intermediate us in order to e stale. However, it can e used at limited conditions such as wide inut range (36-75V) and POL with low ower (in other words, POL with very high inut imedance). C. Full-regulated Full-regulated us converter has a feedack loo, so the outut imedance characteristic is changed. Therefore, outut imedance can e made small with wide andwidth. Figure shows the exerimental result of the relation etween the outut imedance and andwidth. Moreover, Fig. 11 shows the analytical and exerimental results of the relation etween the eak value of outut imedance and andwidth. Both results agreed well. Next, the relation etween caacitance and outut imedance eak is examined in closed loo case. In closed loo case, if caacitance C changes to C+Cadd, eak frequency f of loo gain is changed as follows. 1 f ' (14) 2 C Cadd Therefore, the crossover frequency fc is changed as follows. f ' 1 f ' (15) c Moreover, frequency ratio fc /f is given as following equation. fc' fc (16) f ' f From these results, outut imedance eak can e exressed as following equation. kesrc Zoc _ eak ' Zoc _ eak (17) C Cadd where, k (1 ) rc r kesr (18) (1 ) rc ' r Figure 12 shows the exerimental result of the relation etween the outut imedance and caacitance in closed loo case. Moreover, Fig. 13 shows the analytical and exerimental results of the relation etween the eak value of outut imedance and caacitance in closed loo case. Both results agreed well. In this case, the total ESR is greatly changed y the additional caacitor. Moreover, in the case of closed loo, ESR has a great influence to the outut imedance eak. Therefore, estimation of ESR is very imortant. V. OPTIMAL DESIGN OF BUS CONVERTER In order to evaluate the erformance of this system, the exeriment circuits are imlemented using the secifications and arameters in Tale 1. Outut Imedance (db) 3 Caacitance --> Large E+1 1.E+2 1.E+3 1.E+4 1.E+5 Outut Imedance (db) Oen-loo Characteristic Bandwidth --> Wide 1.E+2 1.E+3 1.E+4 1.E+5 Outut Imedance (db) Fig. 8. Caacitance and outut imedance Exerimental Theory Caacitance (F) Fig. 9. Caacitance and eak value of Zo. Outut Imedance (db) Fig.. Bandwidth and outut imedance. 25 Exerimental Theory Frequency (khz) Fig. 11. Bandwidth and eak value of Zo th International Power Electronics and Motion Control Conference (EPE-PEMC 8)

6 Here, the case with two POLs is discussed for actual examle. The ractical design rocess is shown elow. A. Inut imedance estimation The low-frequency value Zin() of inut imedance is given y Eq. (3). The duty ratio is D=.275 and outut resistance is R=.66() from the relation inut and outut. In this case, the Zin() is.6(db). When two POLs of same condition are connecting in arallel, Zin() is 14.6(dB). Figure 14 shows the exerimental result of inut imedance. The lowfrequency value Zin() is around 15(dB) as shown in Fig. 14. The exerimental results and analytical results are agreed well. If the staility margin is set to 6(dB), then the eak value of outut imedance must e set to 8.6(dB). B. Outut imedance design Figure 15 shows the outut imedance characteristic of the asic case using the arameter of Tale 1. As shown in Fig. 15, the eak value of the outut imedance is around 18(dB. From mentioned aove calculation, the eak value of the outut imedance needs to set around 8.6(dB) for sufficient system staility. Outut Imedance (db ) Outut Imedance (db) Additional Ca. --> Large 1.E+1 1.E+2 1.E+3 1.E+4 1.E Fig. 12. Additional caacitance and outut imedance Theory Exerimental Additional Caacitance (F) Fig. 13. Additional caacitance and eak value of Zo Bus Converter POL Vo/Io TABLE I. CIRCUIT PARAMETERS Symol Descrition Value Vin Inut Volotage 48V V Bus Volotage 12V Outut Inductor of Bus Converter 27H C Outut Caacitor of Bus Converter F rl Registance of 3m rc ESR of C 25m k Feedack gain (with sence gain).9 Lo Co rl rc Outut Condition Outut inductor Outut caacitor Registance of Lo ESR of Co 3.3V/5A 2.8H 8F 25m m In un-regulated case, the otimal inductance value is considered ecause the staility is imroved y small inductance. From Eq. (13), the otimal inductance value can e derived as following equation. L C r r Z (19) _ otimal C o _ eak where, the unit of Zo_eak is. Since the outut imedance must e set to 8.6(dB), the inductance value is set to around 87(H) from Eq. (19). Figure 16 shows the exerimental result of the outut imedance with small inductance. Imedance (db) Outut Imedance (db) Inut imedance Low-frequency value of inut imedance 1.E+2 1.E+3 1.E+4 1.E Fig. 14. Inut imedance characteristic. 18dB 1.E+2 1.E+3 1.E+4 1.E+5 Fig. 15. Outut imedance (Basic arameters) th International Power Electronics and Motion Control Conference (EPE-PEMC 8) 45

7 The inductance value is around 9 (H), and the eak value of outut imedance is around 8.5 (db). The exerimental results and analytical results are agreed well. Moreover, in oen loo case, since the rl is generally larger than rc, the outut imedance does not ecome smaller than rl as shown in Fig. 6. Therefore, the inductance value has minimum value. From Eq. (19), the minimum value of the inductance is given y following equation. L C _min r r C r () In this case, the minimum value of inductance is around (H). In semi-regulated case, the otimal caacitance value is considered ecause the staility is imroved y large caacitance. From Eq. (13), the otimal caacitance value can e derived as following equation. C _ otimal (21) r r C Z o_ eak where, the unit of Zo_eak is. Since the outut imedance must e set to 8.6(dB), the caacitance value is set to around 3(F) from Eq. (16). In this case, the influence of ESR is considered. Because the ESR ecomes small when the caacitor is connected in arallel. Figure 17 shows the exerimental result of outut imedance with large caacitance. The caacitance value is 3 (F), and the eak value of outut imedance is around 8 (db). The exerimental results and analytical results are agreed well. Outut Imedance (db) Outut Imedance (db) H, 18dB 9H, 8.5dB 1.E+2 1.E+3 1.E+4 1.E Fig. 16. Outut imedance with small inductor. F, 18dB 3F, 8dB 1.E+2 1.E+3 1.E+4 1.E+5 Fig. 17. Outut imedance with large caacitor. Moreover, the outut imedance does not ecome smaller than rl as shown in Fig. 8. Therefore, the caacitance value has maximum value. From Eq. (21), the maximum value of the caacitance is given y following equation. C _max r r C r (22) In this case, the maximum value of caacitance is around 2.8 (mf). In full-regulated case, the otimal andwidth is considered ecause the staility is imroved y wide andwidth. From Eq. (13), the otimal andwidth can e derived as following equation. L r CZ oc_ eak fc_ otimal f (23) rc where, the unit of Zo_eak is. Since the outut imedance must e set to 8.6(dB), the andwidth is set to around 5.1kHz from Eq. (23). Figure 18 shows the exerimental result of the outut imedance with wide andwidth. The andwidth is around4.7khz, and the eak value of outut imedance is around 8.5 (db). The exerimental results and analytical results are agreed well. Next, the otimal caacitance is considered in closed loo case. From Eq. (17), the otimal additional caacitance can e derived as following equation. kesrz oc _ eak Cadd _ otimal 1C (24) Zoc _ eak ' The asic arameters case, the closed loo outut imedance eak is around 14.5(dB). Since the outut imedance must e set to 8.6(dB), the additional caacitance is set to around 15F from Eq. (24). Figure 19 shows the exerimental result of the outut imedance with additional caacitance. The caacitance is around 15F, and the eak value of outut imedance is around 9 (db). The exerimental results and analytical results are agreed well. Outut Imedance (db) Hz, 18dB 4.7kHz, 8.5dB 1.E+2 1.E+3 1.E+4 1.E+5 Fig. 18. Outut imedance with wide andwidth th International Power Electronics and Motion Control Conference (EPE-PEMC 8)

8 VI. CONCLUSIONS This aer resents the outut imedance design for onoard distriuted ower system y means of three control methods of us converter. The outut imedance eak of the us converter and the inut imedance of the POL were analyzed, and it was conformed y exerimentally for staility criterion. As a result, the standard of the discrimination of staility on a frequency resonse of inut and outut imedance was clarified. Furthermore, the design rocess of each control method for system staility was roosed. Outut Imedance (db ) Without Cadd, 14.5dB 15uF, 9dB 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 Fig. 19. Outut imedance with additional caacitance REFERENCES [1] C. M. Wildrick, F. C. Lee, B. H. Cho, B. Choi, A Method of Defining the Load Imedance Secification for A Stale Distriuted Power System, IEEE Transactions on Power Electronics Vol.. No. 3. May 1995, [2] X. Feng, Z. Ye, K. Xing, F. C. Lee, D. Borojevic, Individual Load Imedance Secification for a Stale DC Distriuted Power System, IEEE Alied Power Electronics Conference (APEC) 1999, [3] X. Feng, F. C. Lee, On-line Measurement on Staility Margin of DC Distriuted Power System, IEEE Alied Power Electronics Conference (APEC), [4] M. P. Sayani, J. Wanes, Analyzing and Determining Otimum On-Board Power Architectures for 48V-inut Systems, IEEE Alied Power Electronics Conference (APEC) 3. [5] K. Hisanaga, K. Harada, Staility Analysis of the Distriuted Power System with Intermediate Bus Converter, IEICE Technical Reort, Vol.3, No.199,.19-24, Jul. 3 (in Jaanese). [6] K. Hisanaga, K. Harada, Staility Analysis of the Distriuted Power System with Intermediate Bus Converter (2nd Reort), IEICE Technical Reort, Vol.3, No.652,.7-12, Fe. 4 (in Jaanese). [7] Y. Ren, M. Xu, K. Yao, Y. Meng, F. C. Lee, J. Guo, Two-Stage Aroach for 12V VR, IEEE Alied Power Electronics Conference (APEC) 4. [8] J. Wei, F. C. Lee, An Outut Imedance-Based Design of Voltage Regulator Outut Caacitors for High Slew-Rate Load Current Transients, IEEE Alied Power Electronics Conference (APEC) 4. [9] B. Choi, D. Kim, D. Lee, S. Choi, J. Sun, Analysis of Inut Filter Interactions in Switching Power Converters, IEEE Transactions on Power Electronics, Vol. 22, No. 2, March 7, [] S. Ae, M. Hirokawa, T. Zaitsu, T. Ninomiya, "Staility Design of Bus Converter Following y POLs in Distriuted Power System", IASTED Circuits, Signals,and Systems (CSS), 5, [11] S. Ae, H. Nakagawa, M. Hirokawa, T. Zaitsu, T. Ninomiya, "Comarison of System Staility in Distriuted Power System Based on Control Method of Bus Converter", IASTED Energy and Power Systems (EPS) 5, [12] S. Ae, H. Nakagawa, M. Hirokawa, T. Zaitsu, T. Ninomiya, "System Staility of Full-Regulated Bus Converter in Distriuted Power System", International Telecommunications Energy Conference (INTELEC) 5, [13] S. Ae, H. Nakagawa, M. Hirokawa, T. Zaitsu, T. Ninomiya, " Staility Imrovement of Distriuted Power System y Using Full-Regulated Bus Converter ", Annual Conference of the IEEE Industrial Electronics Society (IECON) 5, [14] S. Ae, T. Ninomiya, M. Hirokawa, T. Zaitsu, "Staility Comarison of Three Control Schemes for Bus Converter in Distriuted Power System ", International Conference on Power Electronics and Drive Systems (PEDS) 5, [15] S. Ae, M. Hirokawa, T. Zaitsu, T. Ninomiya, " Staility Design Consideration for On-Board Distriuted Power System Consisting of Full-Regulated Bus Converter and POLs ", IEEE Power Electronics Secialists Conference (PESC) 6, [16] R.D. Middlerook, S. Cuk, A General Unified Aroach to Modeling Switching-Converter Power Stages, IEEE Power Electronics Secialists Conference (PESC) 1976, [17] T. Ninomiya, M. Nakahara, T. Higashi, K. Harada, A Unified Analysis of Resonant Converters, IEEE Transactions on Power Electronics Vol. 6. No. 2. Aril 1991, [18] R. D. Middlerook, Inut Filter Considerations in Design and Alication of Switching Regulators, IAS 76, 1976, th International Power Electronics and Motion Control Conference (EPE-PEMC 8) 47