Evolutionary Circuit Design: Information Theory Perspective on Signal Propagation

Transcription

1 Evolutionary Circuit Design: Theory Persective on Signal Proagation Denis Poel Deartment of Comuter Science, Baker University, P.O. 65, Baldwin City, KS 66006, Nawar Hakeem Deartment of Comuter Science, University of Wollongong (Australia), Dubai Camus, P.O. Box 208, Dubai, U.A.E., arxiv:cs/ v [cs.oh] Jul 2002 Abstract This aer resents case-study results on the alication of information theoretic aroach to gate-level evolutionary circuit design. We introduce information measures to rovide better estimates of synthesis criteria of digital circuits. For examle, the analysis of signal roagation during evolving gate-level synthesis can be imroved by using information theoretic measures that will make it ossible to find the most effective geometry and therefore redict the cost of the final design solution. The roblem is considered from the information engine oint of view. That is, the rocess of evolutionary gate-level circuit design is resented via such measures as entroy, logical work and information vitality. Some examles of geometry driven synthesis are rovided to rove the above idea. I. Introduction The imact of different design strategies on the time cycle of digital circuit creation, and the effect of erformance and ower dissiation on the final realization have increased the imortance to integrate the technology - indeendent and technology - deendent design stages. In other words, logic secification should become closer to the final toological structures and hysical imlementation of digital circuits. To move in this direction, we address the roblem of automatic synthesis imlementations using gate-level evolutionary aroach [2]. Gatelevel evolutionary design is of great interest to researchers as it outlines the major stes to synthesize the final realization []. Concets and techniques develoed for different design strategies searately can therefore be exloited simultaneously in evolutionary circuit design. Our study is based on the ioneering work of the gate-level evolutionary synthesis which exloits geometry reresentation of rectangular array of cells [2], [4]. In information networks, of which digital circuits are an integral comonent, one deals with a variety of logical oerations and comlex rocesses delivering signals before information reaches the final destination. These information systems seem to need a new basic theory which hels to understand the system in its entirety in order to rovide a basis for designing the total system. Such a theory was develoed in [8]. In accordance with the theory, the machines which deal with information can be generally referred to as information engines which model the actual information systems. In this aer, we roose such an interretation for evolutionary circuit design which considers stochastic behaviour of evolutionary synthesis in the context of information measures [], [7]. Hence, entroy is used as a comlexity characteristic in the circuit-design otimization rocess and generally in signal rocessing [5]. Altogether, we describe a new method of analysis for geometrybased evolutionary synthesis in which the main contribution is using information theoretic measures for calculating arameters of geometry in evolutionary gate-level circuit design. This aer is structured as follows. Section II exlains the background. Section III describes the information theory interretation of geometry-based gate-level circuit design. We introduce information measures and their alications to digital circuit design in Section IV and show case-study results. We conclude and oen a discussion forum in Section V. II. Preliminaries and Assumtions Consider logic reresentation of a digital circuit in the form of Boolean function f treated as

2 the maing {0,} n {0,} m over the variable set X = {x,,x n }. Here, n is the number of variables (inuts), and m is the number of functions (oututs). A. Evolutionary Circuit Design The central idea of evolutionary gate-level circuit design is to search for functionality and connectivity of an array of cells whose arameters are defined by the circuit layout called circuit geometry [4]. Possible solutions are reresented using chromosomes which are exloited by genetic algorithm with standard oerations such as mutation, crossover and selection. The length of a chromosome deends on circuit geometry. In our work, the circuit geometry can be changed, therefore a chromosome of variable length is considered. The evolution of the digital circuit design is twofold: first, 00% functionality has to be obtained; second, the comlexity of realization, i.e., number of gates, inter-connections and layout should be taken into consideration. It was shown in [] that by allowing the circuit geometry to be flexible, we can evolve circuits with the smallest number of used gates. Other circuit geometry characteristics are: number of inuts, size of the array of logic cells in the form of the number of rows and columns, degree of connectivity defined by a level-back arameter, and the functionality or the fitness function. In this aer, we consider only two asects of evolutionary circuit synthesis: determining the size of n m cellular array with n I inuts and n O oututs, and defining the library of gates needed for the rocess of evolutionary circuit design. The circuit layout is given as a rectangular array of gates which are uncommitted (Figure 2(a)). We restrict our investigation to the cell library α of basic logic functions L = {NOT,AND,OR,EXOR} with rimary and inverted inuts. We omit the stages of evolutionary synthesis and further verification of evolved circuit. The efficiency of the search rocess is indicated using the so called fitness function. The fitness function which emloys information theoretical measures was roosed in []. In our study of geometry, we utilize information theoretic notations as a tool to quantify the characteristics of geometry and cell library. B. Theoretic Notations In order to quantify the content of information for a finite field of events A = {a,a 2,,a n } with robabilities distribution {(a i )}, i =,2,,n, Shannon introduced the concet of entroy [7]: H(A) = n i= (a i ) log(a i ), where log denotes the base 2 logarithm. For two finite fields of events A and B with robability distribution {(a i )},i =,2,,n, and {(b j )}, j =,2,,m, robability of the joint occurrence of a i and b j is joint robability (a i,b j ), and there is conditional robability, (a i b j ) = (a i,b j )/(b j ). The conditional entroy of A given B is defined by H(A B) = n i= mj= (a i,b j ) log(a i b j ). In case of logic networks and signal rocessing, we assume that the sets of values of a function f and arrary variable x are two finite fields [5]. We calculate the robability f=b = k f=b /k, where k f=b is the number of assignments of values to variables for which f = b and k is the total number of assignments. Examle : For the function f = x x 2 x with truth vector [000]: H(f) = 5 / 8 log 2 ( 5 / 8 ) / 8 log 2 ( / 8 ) = 0.96, H(f x ) = / 8 log 2 ( / 4 ) / 8 log 2 ( / 4 ) 4 / 8 log 2 ( 4 / 4 ) 0 = 0.4. By the same comutations H(f x 2 ) = 0.9, H(f x ) = 0.9. III. Engine of Circuit Evolution Consider an information engine with one inut ort and one outut ort, where the initial descrition of the logic function f is converted to outut descrition, evolvable circuit. Any rocess done by the information engine can be considered as a comosition of two tyes of rocesses, isentroic rocess and entroy changing rocess. Successful (00% functionality) evolutionary design is an isentroic rocess that does not change the function itself. When we deal with an entroy changing rocess that requires the conversion of inut and outut combinations or ensembles, we call such a rocess iso-vitality. The concet of information engine of evolvable gate-level circuit design is based on the following notation. For every inut descrition of the logic function f, there exists the logical

3 NetWork (NW) which converts inut ensemble to outut ensemble. Hence, the loss of uncertainty or network information can be characterized by I NW = H loss (f X) = H(X) H(f). For each inut x i of the logical network, the value of information transmitted to the outut f is H trans (x i ) = H(f x i ). Entroy H ( X) Initial descrition of logic function Evolvable circuit Isentroic rocess Evolutionary Design of Digital Circuits A. Evolutionary Design as Isentroic Process Consider a circuit design rocess as a sequence of stes which oerate with inut variable X, and corresond to network reresentation of the function f. Let q(f;nw) be the logical work required to convert initial descrition of f to the network NW via an information engine. The concet of logical work for digital networks was also discussed in []. The circuit design rocess is reversible, i.e., it is ossible to roduce the initial function descrition from the network, which means it is an isentroic rocess: H(f) = I(f;NW) and I(X;NW) = H(X). For an isentroic rocess of circuit design, we can use the information otential measure defined next. Definition : Potential is the inferior bound of quantity of logical work q(f;nw) under all ossible NW design rocesses, Q(f;NW)= Inf[q(f;NW)] for all ossible NW This is the information otential of logic function f with resect to network NW. Another imortant information concet is, Definition 2: Vitality is the information otential of an ensemble X with resect to network N W er unit of information, T(NW) = Q(f;NW)/H(f) This is the information vitality equation. The information otential characterizes the cost of final realization of the logic function f, therefore, the search of the inferior bound of q(f;nw) reresents a search of the logic function that will minimize the cost of realization. The dynamic behaviour of an information engine of gate-level circuit design can be best described in the entroy vs. vitality diagram, so called H-T-Diagram (Figure ). The design of digital circuit is an isentroic rocess with resect to inuts and oututs. verification of circuit design is an iso-vitality ro- H ( f ) T ( Init ) Gate level information measuring Isentroic rocess 00% functionality T ( Network) measuring using network reresentation Infor mation vitality Fig. H-T-Diagram of gate-level circuit design rocess cess. We can evaluate the loss of information via construction of a logic network for the verified function. The synthesis of an information engine for evolutionary gate-level circuit design deals with all arts of H-T-Diagram in addition to information measuring which is an essential art of the synthesis rocess. B. Gate-level Measuring Let us consider simle gates and its information content in order to analyze the information transmission through each gate. The concet of logical work is crucial for information measures of Boolean networks []. We use the following notation for each gate: the inut entroy H(X), and the outut entroy of function f is H(f). Definition : The conditional entroy H(f x) between arrary variable x and the function f is a measure of transmission of information from inut x to the outut f. Definition 4: The difference between inut and outut entroies of a gate, I gate = H(X) H(f), is an information theoretic measure of the gate. Examle 2: For the function AND we obtain the following entroy measures: H(X) = / 4 log / 4 / 4 log / 4 / 4 log / 4 / 4 log / 4 = 2

4 s, H(f) = / 4 log / 4 / 4 log / 4 = 0.8 s, I gate = =.9 s, H trans (f x ) = H trans (f x 2 ) = 0.5 s. Note, the uncertainty of the outut of a digital network is never increased by knowledge of inut atterns. In other words, the digital network does not increase information carried by the inuts. IV. Circuit Layout Measuring We focus in our study on a scanning rocess for a secified geometry style to evolve digital circuits defined over a library L of gates G,..., G t, where t is a total number of gates in the library. We consider geometry q as one of the main comonents of the evolutionary design secification. Note that geometry incororates many arameters: the maximal number of levels, the maximal number q of gates in each level of the evolved network, tyes of logic gates from the standard logic library L, network architecture(ermissible interconnections between cells, levels, inuts and oututs of the circuit). In the study of gate-level evolutionary design, the desired logic function has to be imlemented through the scanning rocess, i.e. rocessing of the full circuit is accomlished by dividing it into subarts (windows) which are scanned in turn, to fulfill given restrictions on library gates and geometry structure. The runtime and the final cost of circuit realization should be minimal. It is essential to consider different geometry realizations, and various schemes of assigning logic elements to different circuit levels (see, for examle, AND OR EXOR networks in [6]). We will vary the number of levels, gates in each level, and tyes of gates, and assign gates to many circuit levels in order to otimize the evolution rocess. We investigate the fact shown in [4] that evolving some circuits is easier to do on a larger scanning window, but this has resulted in a less efficient circuit. The evolution of an q-level, n-inut, m-outut circuit, over the fixed library of cells L = {G,...,G t } is defined by the scanning window q. The structure of q-level circuit is characterized by the number of levels allowed to be connected with inuts and oututs, such arameter is called level back. So, the result of this searching rocess is a set of circuits with no more than q levels and no more than gates in each level. We estimate a scanning window size based on the information content with the final goal to otimize this window, or at least to give useful recommendations on how to choose the geometry to design a circuit in accordance with the given secification. A. Measures of Library Cells The main idea of information measuring of a geometry is to give numerical estimations and establish roositions for the scanning arameters. Here we define information caacity for a gate, a library of gates, and geometry. We select gates, for every osition of the scannedwindow, fromthecell libraryl. Theinformation equivalents of library gates are given in Table I. We consider I gate as an information caacity of the gate (Figure 2). Here, we do not take into account the information carried by inuts and oututs of the network, because such an information does not influence geometry arameters. Definition 5: caacity I L of a library L of gates G,..., G t is the entire amount of information caacities of the gates: I L = L I gate. Examle : Given the gate library L = {NOT,AND,OR}, information caacity is I L = I gate (NOT ) +I gate (AND) +I gate (OR) = 2.8. Definition 6: caacity I G of a single cell with resect to a scanning window is the maximal information caacity of all gates from the given (fixed) cell library L: I G = max{i gate } for all gates from library L. Based on these definitions, we can assume thatinformationcaacity of q geometryover a fixed library L of gates G,...,G t is a comosition of information caacities of the cells: I Geometry = q I G The information caacity of a geometry also deends on interconnections among the cells, and the level back arameter with resect to inuts and oututs of an evolving circuit. We use rough estimations of information caacities for each level of the created circuit based on information measures. Then, roceed from this as-

5 TABLE I equivalent of rimitive gates in s Library gates N OT AN D OR EX OR Function f [0] [000] [0] [00] Maximum inut information H(X) Outut information H(f) Gate information measure H(X) H(f) Transmission of information H(f x) q Cell Scanning in secified geometry over a fixed library of cells (a) 0 x x2 x x4 Com lem ents of variables... (c) IN: from the sace of ossible circuit solutions f Circuit level 2 Gate Gate Scanning (b) Gate 2 Gate 4 OUT: Evolved circuit in secified geometry Fig. 2 Evolutionary gate-level circuit synthesis realized by scanning using geometry and given library of gates sumtion and additional factors, in articular, the transmitted information through each level of the created circuit in order to estimate information caacity of the geometry of a given logic function, and analyze the gate library suitability in terms of design arameters in our evolutionary algorithm. Examle 4: Given the cell library L = {NOT,AND,OR} and a scanning window of 2 2, the information caacity of cells in the first level is I G =.9, and in the second level is I G = Theinformation caacity of the geometry is equal to I Geometry =.57 (Figure 2(c), see corresonding geometry in Figure (c)). B. Proer Selection of Geometry: Case Study We summarize the information measures for different secifications in Table II. These mea- TABLE II caacity of geometries Geometry {NOT, {NOT, {NOT,AND, AND,OR} EXOR} OR,EXOR} 2 2 I Geometry I Geometry sures allow us to make a riori decision about the efficiency of a scanning window. Examle 5: Let us estimate the scanning rocess for an evolving 4-inut, 2-outut digital circuit. For the urose of simlification, assume these secifications, Secification : geometry over the gate library L = {NOT,EXOR}. The informa-

6 q 2 2 q 2 2 q I x = 5.25 (a) I x =.50 (b) I =.57 2x2 (c) Fig. Estimations of given geometry for Examle 5 tion caacity of the given geometry a riori is I Geometry = (+ / 2 + / 4 ) = 5.25(Figure (a)). Let us assume that it is ossible to realize the circuit with a maximum of 6-inuts and -oututs, but during the design 4-inut, 2- outut circuit was created. It means that some of cells did not get utilized (Figure (b)). For this case, the information caacity of the geometry is I Geometry =.5. Secification 2: 2 2 geometry over the gate library L = {NOT,AND,OR}. The information caacity of the design style is I Geometry = 2.9 ( + / 2 ) =.57 s. Such geometry allows to evolve 4-inut, 2-outut circuits (Figure (c)). Hence, 2 2 geometry over L = {NOT,AND, OR} has greater information caacity than geometry over L = {NOT,EXOR} to evolve 4-inut, 2-outut circuit. V. Concluding Remarks It has been shown that information theory measures of the evolutionary circuit design rocess are useful and give new ossibilities to imrove the efficiency of the recently develoed evolutionary techniques. The main contribution of this aer is the inclusion of circuit information content in the evolutionary scanning rocess and signal roagation in the context of an information engine. The extension of the recently develoed technique of evolutionary circuit design includes information quantification of a cell library, and estimation of circuit geometry. Hence, results obtained with the roosed technique show that it can be useful for a riori analysis of gate-level evolutionary synthesis. References [] L. Hellerman. A measure of comutation work. IEEE Trans. Comuters, C-2(5):49 446, 972. [2] H. Iba, M. Iwata, and T. Higuchi. Machine learning aroach to gate level evolvable hardware. In Lecture Notes in Comuter Science, Sringer-Verlag, vol. 259, ages 27 9, 997. [] T. Luba, C. Moraga, S. Yanushkevich, M. Ooka, and V. Shmerko. Evolutionary multi-level network synthesis in given design style. In Proc. of the IEEE Int. Sym. on Multile Valued Logic, ages , [4] J. F. Miller, P. Thomson, and T. Fogerty. Designing Electronic Circuits Using Evolutionary Algorithms. Arithmetic Circuits: A Case Study, ages 05. John Wiley and Sons Ltd, 998. [5] D. Poel. Towards efficient calculation of information measures for reordering of binary decision diagrams. In Proc. of the IEEE Int. Sym. on Signals, Circuits and Systems, ages , 200. [6] T. Sasao. Switching Theory for Logic Synthesis. Kluwer Academic Publishers, 999. [7] C. Shannon. A mathematical theory of communication. Bell Syst. Tech. J., 27:79 42, , 948. [8] H. Watanabe. Network theory of information engine. In Proc. Euroean Conf. on Circuit Theory and Design - ECCTD 97, ages 6, 997.