(11) Bipolar Op-Amp. Op-Amp Circuits:

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1 (11) O-Am Circuits: Biolar O-Am Learning Outcome Able to: Describe and analyze the dc and ac characteristics of the classic 741 biolar o-am circuit. eference: Neamen, Chater ) 741 O-Am 11.1) Circuit Descrition The 741 o-am has been roduced since 1966 by many semiconductor device manufacturers. The 741 is still a widely used general-urose o-am although there have been many advances in o-am design. Even though the 741 is a fairly old design, it still rovides a useful case study to describe the general circuit configuration and to erform a detailed dc and small-signal analysis. From the ac analysis, usually voltage gain and frequency resonse of the circuit are determined. Figure 13.3: Equivalent circuit, 741 o-am. 11.1) Circuit Descrition (Cont) ) nut Diff-Am and Biasing The 741 consists of inut differential amlifier stage, gain stage, outut stage and searate bias circuit (which establishes the bias currents throughout the o-am). Like most o-am, the 741 is biased with both ositive and negative suly voltages. This eliminates the need for inut couling caacitors, which in turn means that the circuit is also a dc am. The dc outut voltage is zero when the alied differential inut signal is zero. Tyical suly voltages are V + 15V and V _ -15V, although inut voltages as low as 5V can be used. nut stage: Q 1 to Q 7 Biasing: Q 8 to Q 1 nut transistors Q 1 and Q : act as emitter follower high id Q 3 and Q 4 : commonbase amlifier (large voltage gain), with inut currents from Q 1 and Q Figure 13.5: Bias circuit and inut stage of 741 o-am. Lecturer: Dr Jamaludin Bin Omar 11-1

2 11.1.1) nut Diff-Am and Biasing (Cont) Q 5, Q 6 and Q 7 with 1, and 3 : form active load. Outut (single-sided) at collector of Q 4 and Q 6 The dc outut voltage at collector Q 6 is at lower otential than inuts at bases of Q 1 & Q. As signal asses through the o-am, dc voltage level shifts several times. By design, when the signal reaches outut terminal, dc voltage should be zero if a zero diff inut signal is alied. Two null terminals on inut stage are used to make aroriate adjustments to accomlish this design goal ) nut Diff-Am and Biasing (Cont) Q 1, Q 11 & 5 : dc current biasing rovides EF Q 10, Q 11 & 4 : Widlar current source for common-base transistors (Q 3 & Q 4 ) and current mirror formed by Q 8 & Q 9. Q 3 & Q 4 : are lateral n device, which refers to fabrication rocess and geometry of the transistors rovide added rotection against voltage breakdown, although the current gain is smaller than in nn devices ) nut Diff-Am and Biasing (Cont) Figure 13.4: (a) Basic common-emitter diff-air with a large differential voltage and (b) 741 inut stage, with a large differential voltage ) nut Diff-Am and Biasing (Cont) For Figure 13.4: V 1 15 V, V 0 V. Figure (a): Basic common-emitter diff-air B-E of Q is reverse biased by arox 14.3 V Since an nn B-E junction has breakdown voltage of 3 to 6 V Q would robably enter breakdown and ermanently damaged. Figure (b): B-E of Q 1 & Q 3 are forward biased Series combination of B-E junction of Q & Q 4 is reverse biased by arox 13.6 V The breakdown voltage of lateral n is tyically on order of 50 V B-E of Q 4 rovides breakdown rotection for inut diff-am stage ) Gain Stage Q 16 & Q 17 : second (gain) stage. Q 16 : emitter follower large in Q 13 : two transistors in arallel Q 13A : ¼ area of Q 1 Q 13B : ¾ area of Q 1 Q 13B : rovides bias current for Q 17, and is also the active load for high voltage gain ) Gain Stage (Cont) Q 17 : common-emitter voltage at collector of Q 17 is inut signal to outut stage signal undergoes another dc level shift in this gain stage. Caacitor C 1 : internal feedback comensation (Miller comensation) for stability connected between the outut and inut terminals of the gain stage. Figure 13.7: eference circuit and gain stage of 741 o-am. Figure 13.7: eference circuit and gain stage of 741 o-am. Lecturer: Dr Jamaludin Bin Omar 11-

3 11.1.3) Outut Stage ) Outut Stage (Cont) Figure 13.8: Basic outut stage of 741 o-am, showing currents and voltages. Q 14 & Q 0 : class-ab circuit of comlementary emitter-follower to rovide low outut resistance and current gain (for driving large load currents). Outut of gain stage is connected to the base of Q emitter follower, high inut resistance. Q 13A : rovides a bias current for Q, Q 18 & Q 19 Q 18 & Q 19 : to establish a quiescent bias current in outut transistors Q 14 & Q 0. Q 15 & Q 1 : are short-circuit rotection devices normally off. Conducting only when outut is inadvertently connected to ground, resulting in a very large outut current ) Abbreviated Data Sheet 11.) DC Analysis Table 13.1: Data for 741 at T 300 o K and suly voltage of 15V Parameters Minimum Tyical Maximum Units nut bias current na Diff-mode inut resistance M nut caacitance 1.4 F Outut short-circuit current 5 ma Oen-loo gain ( L k) 50,000 00,000 V/V Outut resistance 75 Unity-gain frequency 1 MHz Purose: To determine dc bias currents. Assumtions: Both non-inverting and inverting inut terminals are at ground otentials. dc suly voltages are V + 15V and V _ -15V. Aroximations: Assume V BE for nn V EB for n 0.6V. n most cases dc base currents are neglected. 11.) DC Analysis (Cont) 11..1) Bias Circuit and nut Stage Stes in DC Analysis: dentify the bias ortion of oam circuit. Determine the reference current. Determine the bias currents in the individual building blocks of the overall circuit. Figure 13.5: Bias circuit and inut stage of 741 o-am. The reference current established by Q 1, Q 11 & 5 : EF V + V EB1 V (13.1) Current C10 from Widlar current source (Q 11, Q 10 & 4 ): 5 BE11 V C104 VT ln( EF / C10) (13.) Lecturer: Dr Jamaludin Bin Omar 11-3

4 11..1) Bias Circuit and nut Stage (Cont) Neglecting base currents C8 C9 C10 Then, quiescent collector currents in Q 1 through Q 4 : C1 C C3 C4 C10 / (13.3) Assuming dc currents in the inut stage are exactly balanced, dc voltage at collector of Q 6 inut to the second stage dc voltage at collector of Q 5 (or V C5 ) 11..1) Bias Circuit and nut Stage (Cont) Examle 13.1 Objective: Calculate dc bias currents in the bias circuit and inut stage of the 741 o-am. The bias circuit and inut stage are shown in Figure V C6 V C5 V BE7 + V BE6 + C6 + V _ (13.4) The dc level shifts through the o-am ) Bias Circuit and nut Stage (Cont) Solution: From Equation (13.1), the reference current is EF V EF + Examle 13.1 (Cont) V EB1 V 5 BE11 V ( 15) 0.7mA 40k 11..1) Bias Circuit and nut Stage (Cont) Current C10 is found from Equation (13.), as follows: C10 V ln( 4 C10 T Examle 13.1 (Cont) EF / C10 (5k) (0.06) ln(0.7m / By trial and error, can find C10 19 µa The bias currents in the inut stage are then C1 C C3 C4 C10 / 9.5 µa ) C10 ) 11..1) Bias Circuit and nut Stage (Cont) From Equation (13.4), the voltage at the collector of Q 6 is V C6 V BE7 + V BE6 + C6 + V _ V C (9.5µ)(1k) + (-15) or V C V Examle 13.1 (Cont) 11..1) Bias Circuit and nut Stage (Cont) Figure 13.6: Exanded inut stage, 741 o-am, showing base currents. Effect of the base currents of Q 3, Q 4, Q 8 & Q 9 (n) may be small, hence not negligible. Still assume of nn negligible. C10 establishes base currents in Q 3 & Q 4 which then establish emitter currents. At collector of Q 8 : + C9 + C8 C 1 9 Lecturer: Dr Jamaludin Bin Omar 11-4

5 11..1) Bias Circuit and nut Stage (Cont) Effect of the base currents (Cont) Since Q 8 and Q 9 are matched: C8 C9. Then, C C10 C (13.6) ) Bias Circuit and nut Stage (Cont) Effect of the base currents (Cont) With aroximation C 10 Even if base currents in n are not negligible, bias current in Q 1 and Q are very nearly C10 / (13.7) Bias current is essentially the same as originally assumed in Equation (13.3). 11..) Gain Stage 11..) Gain Stage (Cont) Q 1 & Q 13 form the current mirror, Q 13B scaled to 0.75 of Q 1. Neglecting base currents: C13B 0.75 EF (13.8) Examle 13. Objective: Calculate the bias currents in the gain stage of the 741 o-am in Figure Assume bias voltages of 15 V. Collector current in Q 16 : E178 + V C16 E16 B (13.9) BE17 Figure 13.7: eference circuit and gain stage of 741 o-am. 11..) Gain Stage (Cont) 11..3) Outut Stage Examle 13. (Cont) Solution: From Examle 13.1, EF 0.7 ma. From Equation (13.8), the collector current in Q 17 is C17 C13B 0.75 EF (0.75)(0.7m) 0.54 ma Assuming 00 for the nn transistor, the collector current in Q 16 is, from Equation (13.9), C16 B17 + ( E V BE17 )/ m/00 + [(0.54m)(100) + 0.6]/50k or C µa Figure 13.8: Basic outut stage of 741 o-am, showing currents and voltages. Lecturer: Dr Jamaludin Bin Omar 11-5

6 11..3) Outut Stage (Cont) Bias is sulied by Q 13A and inut signal is alied to base of Q (emitter follower). Q 18 & Q 19 Establishes V BE dros between base terminals of Q 14 & Q 0 This V BB roduces quiescent collector currents in Q 14 & Q 0 Biasing both Q 14 & Q 0 on with no signal resent at the inut, to remove crossover distortion ) Outut Stage (Cont) Neglecting base currents, C Bias Collector current in Q 18 is C18 V BE19 / 10 (13.11) Q 13A is scaled to 0.5 of Q 1. Neglecting base currents, C13A 0.5 EF Bias (13.10) Therefore, C19 Bias - C18 (13.1) 11..3) Outut Stage (Cont) 11..3) Outut Stage (Cont) Since V BB remains almost constant: Examle 13.3 As v increases, base voltage of Q 14 increases and v O increases As v decreases, base voltage of Q 0 decreases and v O decreases The small-signal voltage gain of outut stage is essentially unity. Objective: Calculate the bias currents in the outut stage of the 741 o-am. Consider the outut stage in Figure Assume the reverse saturation currents of Q 18 and Q 19 are S A, and the reverse saturation currents of Q 14 and Q 0 are S 3 x A. Neglect base currents ) Outut Stage (Cont) Examle 13.3 (Cont) Solution: The reference current, from Examle 13.1, is EF 0.7 ma. Current C13A is then C13A 0.5 EF (0.5)(0.7m) 0.18 ma Bias f we assume V BE V, then the current in 10 is 10 V BE19 / / 50k 0.01 ma The current in Q 19 is C19 E19 C13A m m C ma 11..3) Outut Stage (Cont) Examle 13.3 (Cont) For that value of collector current, the B-E voltage of Q 19 is V BE19 V T ln( C19 / S ) V BE19 (0.06) ln(0.168m/10-14 ) 0.61 V which is close to the assumed value of 0.6 V. Assuming n 00 for the nn devices, the base current in Q 19 is B19 C19 / n 0.168m / µa Lecturer: Dr Jamaludin Bin Omar 11-6

7 11..3) Outut Stage (Cont) Examle 13.3 (Cont) The current in Q 18 is now C18 E B m µ C µa The B-E voltage of Q 18 is therefore V BE18 V T ln( C18 / S ) V BE19 (0.06) ln(1.84µ/10-14 ) V The voltage difference V BB is thus V BB V BE18 + V BE V 11..3) Outut Stage (Cont) Since the outut transistors Q 14 and Q 0 are identical, one-half of V BB is across each B-E junction. The quiescent currents in Q 14 and Q 0 are C14 C0 S ex( (V BB /) / V T ) C14 C0 (3 x ) ex( (1.157/) / 0.06) or C14 C0 138 µa Examle 13.3 (Cont) 11..4) Short-Circuit Protection Circuitry 11..4) Short-Circuit Protection Circuitry (Cont) To rotect Q 14 from burnout due to large current induced if the outut is shorted to ground during a ositive signal. Figure 13.9: Outut stage, 741 o-am with short-circuit rotection devices. 6 and Q 15 limit the current in Q 14 in the event of a short circuit. f current in Q 14 reaches 0 ma, V 6 is 540 mv Q 15 turns on, and conducts excess base current in Q 14 into its collector. Thus, base current into Q 14 is limited to a maximum value, which limits the collector current ) Short-Circuit Protection Circuitry (Cont) The maximum current in Q 0 is limited by comonents 7, Q 1 & Q 4. A large outut current results in a voltage dro across 7 (V 7 ), sufficient to turn on Q 1. Excess current in Q 0 will be shunted by Q 1 and Q 4. This rotects outut transistor Q ) Small-Signal Analysis Stes in AC Analysis: Analyze the small-signal roerties of the building blocks individually. Loading effects of follow-on stages must be taken into account in the analysis of each building block. Lecturer: Dr Jamaludin Bin Omar 11-7

8 11.3.1) nut Stage Figure 13.10: The ac equivalent circuit, inut stage of 741 o-am. Effective imedance at base of Q 3 & Q 4 is ideally infinite, i.e. oen circuit, due to constant-current biasing at base of Q 3 & Q 4 act1 is the effective resistance of active load. i is the inut resistance of gain stage ) nut Stage (Cont) The small-signal differential voltage gain is v Ad v o1 d g m CQ Ad V T ( r ) o4 ( r ) o4 act1 act1 (13.13) where CQ quiescent collector current in each of the transistors Q 1 to Q 4 and r o4 small-signal outut resistance looking into the collector of Q 4 i i ) nut Stage (Cont) Effective resistance of active load (for outut resistance of a Widlar current source): [ g ( r )] act 1 ro 6 1+ m6 π 6 nut resistance of gain stage: ( ) [ ( ) ] (13.14) ' i rπ n E (13.15) ' where r + 1+ (13.16) E 9 π17 n ) nut Stage (Cont) Examle 13.4 Objective: Determine the small-signal differential voltage gain of the 741 o-am inut stage. Assume nn transistor gains of n 00 and Early voltages of V A 50 V. is effective resistance in emitter of Q ) nut Stage (Cont) Examle 13.4 (Cont) Solution: The quiescent collector currents were determined reviously from revious examles. The inut resistance to the gain stage is found from Equation (13.15) and (13.16), as follows: r π 17 ' E ' nv E 9 T C17 (00)(0.06) 0.54m 9.63kΩ [ rπ 17 + ( 1+ n ) 8 ] 50k [ 9.63k + ( 1+ 00) (0.1k)] 18.6kΩ Also, r π 16 i r nv i C16 Consequently, ) nut Stage (Cont) π 16 Examle 13.4 (Cont) T (00)(0.06) 39kΩ 15.8 ' + (1 + ) n E 39k + (01)(18.6k) 4.07MΩ Lecturer: Dr Jamaludin Bin Omar 11-8

9 r π 6 g r m6 o ) nut Stage (Cont) nv C V V Examle 13.4 (Cont) The resistance of the active load is determined from Equation (13.14). Can be found and C6 A T C6 6 T (00)(0.06) 547kΩ mA/V 5.6MΩ Then, act1 r o4 r act1 act1 V ) nut Stage (Cont) o6 esistance r o4 is C 4 [ 1+ gm6( rπ 6 )] 5.6M[ 1+ (0.365m)( 1k 547k) ] 7.18MΩ A Examle 13.4 (Cont) MΩ ) nut Stage (Cont) 11.3.) Gain Stage CQ Ad o6 VT 9.5 Ad 0.06 A 636 d Examle 13.4 (Cont) Finally, from Equation (13.13), the small-signal voltage gain is ( r ) act1 i ( 5.6M 7.18M 4.07M) Figure 13.11: The ac equivalent circuit, gain stage of 741 o-am. act is the effective resistance of active load. i3 is inut resistance of the outut stage. Use Fig to develo small-signal voltage gain. nut base current to Q 16 is: i b16 v o1 / i (13.17) where i is the inut resistance of gain stage ) Gain Stage (Cont) Base current into Q 17 is: 9 i b17 i + r where i e16 emitter current from Q 16 The outut voltage is: e16 [ ( ) ] π 17 v i (13.18) (13.19) where i c17 ac collector current in Q 17 and o17 outut imedance looking into the collector of Q 17 n ( ) o c17 act i3 o ) Gain Stage (Cont) Combining (13.17), (13.18), and (13.19): A v v v o o1 n i ( 1+ n ) 9 ( act i 3 o 17 ) ( + [ r + ( 1 ) ]) 9 π 17 + The effective resistance of active load is the resistance looking into collector of Q 13B, or: VA act ro 13B (13.1) C13B n 8 Lecturer: Dr Jamaludin Bin Omar 11-9

10 11.3.3) Outut Stage Finding nut esistance: Use Fig 13.1 to determine the inut resistance of the outut stage, i.e. i3. Assume that n outut Q 0 is active and nn outut Q 14 is cutoff. L is included ) Outut Stage (Cont) esistance 19 is series combination of resistance looking into emitter of Q 19 and Q 18, and resistance looking into collector of Q 13A. Effective resistance of the combination of Q 18 and Q 19 is small comared to 13A ; therefore, A ro 13A VA / C13A (13.3) Figure 13.1: The ac equivalent circuit, 741 o-am outut stage, for calculating inut resistance. Since Q oerates as an emitter follower, the inut resistance i3 is: ( )[ ] i3 rπ Q 0 is also an emitter follower, therefore, 0 r + 1 π 0 + ( ) L with the assumtion that L >> 7 (13.4) ) Outut Stage (Cont) Examle ) Outut Stage (Cont) Finding Outut esistance: Use Fig to determine the outut resistance of the outut stage, i.e. o. Assume that Q 0 is conducting and Q 14 is cut-off. Same basic result is obtained when Q 14 is conducting and Q 0 is cut-off. Figure 13.13: The ac equivalent circuit, 741 o-am outut stage, for calculating outut resistance. The outut resistance o is: + o 7 e0 (13.7) ) Outut Stage (Cont) esistance e0 is: r e0 π 0 (13.8) Series resistance due to Q 18 and Q 19 is small comared to c13a, so that c19 c13a. Also, rπ + c 17 c 13B (13.9) e 1+ where c13b r o13b and + e ( 1+ ) ( ) c19 [ g ( r )] r c 17 o17 1+ m17 8 π ) Outut Stage (Cont) Examle 13.6 Lecturer: Dr Jamaludin Bin Omar 11-10

11 11.3.4) Overall Gain n calculating voltage gain of each stage, loading effect of the following stage is accounted. Therefore, the overall voltage gain is the roduct of the individual gain factors, or A A A A v d v v3 where A v3 is voltage gain of the outut stage. t is assumed that A v3 1 because outut stage is emitter follower. Tyical voltage gain values of the 741 o-am is in the range of 00,000. Larger circuits 11.1) Circuit Descrition ) nut Diff-Am and Biasing Figure 13.3: Equivalent circuit, 741 o-am. Figure 13.5: Bias circuit and inut stage of 741 o-am ) Gain Stage ) Outut Stage Figure 13.7: eference circuit and gain stage of 741 o-am. Figure 13.8: Basic outut stage of 741 o-am, showing currents and voltages. Lecturer: Dr Jamaludin Bin Omar 11-11

12 11..4) Short-Circuit Protection Circuitry Figure 13.9: Outut stage, 741 o-am with short-circuit rotection devices. Lecturer: Dr Jamaludin Bin Omar 11-1

There are two basic types of FET s: The junction field effect transistor or JFET the metal oxide FET or MOSFET.

There are two basic types of FET s: The junction field effect transistor or JFET the metal oxide FET or MOSFET. Page 61 Field Effect Transistors The Fieldeffect transistor (FET) We know that the biolar junction transistor or BJT is a current controlled device. The FET or field effect transistor is a voltage controlled