Monograph On Bipolar Junctions

Transcription

1 ISSN (ONLINE) : X ISSN (PRINT) : X Available online at International Journal of Advanced Research in Biology, Ecology, Science and Technology (IJARBEST) Vol. 1, Issue 4, July 2015 Monograh On Biolar Junctions Christo Ananth, Assistant Professor, Deartment of ECE, Francis Xavier Engineering College, Tirunelveli, India NPN - PNP - Junctions - Early effect - Current Equations - Inut and Outut characteristics of CE, CB, CC - Hybrid - π Model - h arameter model, Ebers Moll Model - Gummel Poon model - Multi Emitter Transistor. 2.1 INTRODUCTION: * BJT (BIPOLAR JUNCTION TRANSISTOR): Current through transistor is due to both majority and minority carriers. * FET (FIELD EFFECT TRANSISTOR): Current through transistor is due to majority carriers only. BJT 2.2 nn AND n n TRANSISTOR nn TRANSISTOR E n C E n n C B B Fig 2.1 nn and n TRANSISTOR * BJT is a 3 layer semiconductor device consisting of 2 n junctions. * Center layer Base (B); left layer Emitter (E) and right layer Collector (C) 28

2 ISSN (ONLINE) : X ISSN (PRINT) : X Available online at International Journal of Advancedd Research in Biology, Ecology, Science and Technology (IJARBEST) Vol. 1, Issue 4, July 2015 * EMITTER LAYER is heavily doed and it emits electrons to base if transistor is of nn tye and emits holes to base if transistor is of n tye. BASE LAYER is lightly doed and COLLECTOR LAYER is intermediate. (Collects electrons if transistor is of nn tye or collects holes if transistor is of n tye from base.). Christo Ananth et al.[1] discussed about rinciles of Semiconductors whichh forms the basis of Electronic Devices and Comonents. TRANSISTOR WITHOUTT BIAS: * In nn transistor, there are junction) Fig 2.2TRANSISTOR WITHOUT BIAS 2 junctions (Emitter base junction and Collector base * By Reulsion, free electrons on n side diffuse across Emitter base junction and recombine with holes in base. * Electrons in collector diffuse across Collector base junction. * When free electron in n-layer diffuse across junction, entavalent atoms are formed in n layer and make it ositive ion. * After diffusion, it combines with arent trivalent atom in -region making it negative. So, layer of deleted carriers is formed at the junction. This layer of deletion without free charge carriers is called deletion layer.

3 ISSN (ONLINE) : X ISSN (PRINT) : X Available online at International Journal of Advanced Research in Biology, Ecology, Science and Technology (IJARBEST) Vol. 1, Issue 4, July 2015 * Beyond a certain oint, deletion layer acts like a barrier to diffusion of free electron across junction. Difference of otential across diffusion layer is called BARRIER POTENTIAL * EMITTER HEAVILY DOPED Deletion layer enetrates lightly into emitter region. * BASE LIGHTLY DOPED Deletion layer enetrates deely into base. * COLLECTOR MODERATELY DOPED Deletion layer enetrates moderately into collector * Deletion layer width in Collector base junction > Deletion layer width in Emitter base junction. TRANSISTOR WITH BIAS (May /June Marks) a) TRANSISTOR WITH EMITTER BASE & COLLECTOR BASE JUNCTIONS FORWARD BIASED: Fig.2.3 TRANSISTOR WITH EB & CB JUNCTIONS FORWARD BIASED b) TRANSISTOR WITH EMITTER BASE & COLLECTOR BASE JUNCTION REVERSE BIASED:

4 ISSN (ONLINE) : X ISSN (PRINT) : X Available online at International Journal of Advancedd Research in Biology, Ecology, Science and Technology (IJARBEST) Vol. 1, Issue 4, July 2015 c) TRANSISTOR WITH EMITTER BASE JUNCTION FORWARD BIASED AND COLLECTOR BASE JUNCTION REVERSE BIASED Fig. 2.5 TRANSISTOR WITH EB JUNCTION FORWARD BIASED AND CB JUNCTION REVERSE BIASED 2 n junctions must be correctly biased with external dc voltages. In Fig. 2.3, Both EB and CB junctions are forward biased Emitter and Collector currents are large. In Fig. 2.4, Both EB and CB junctions are reversed biased Emitter and Collect tor currents are due to thermally generated minority carriers. In Fig. 2.5, Emitter base junction is forward biased and Collector base junctionn is reverse biased OPERATION OF nnn TRANSISTOR a) TRANSISTOR WITH JUNCTION. X FORWARD BIASED EB JUNCTION AND CB

5 ISSN (ONLINE) : X ISSN (PRINT) : X Available online at International Journal of Advanced Research in Biology, Ecology, Science and Technology (IJARBEST) Vol. 1, Issue 4, July 2015 b) TRANSISTOR WITH EB JUNCTION AND CB JUNCTION REVERSE BIASED c) TRANSISTOR WITH EB JUNCTION FORWARD BIASED AND CB JUNCTION REVERSE BIASED Fig 2.8 TRANSISTOR WITH EB JUNCTION FORWARD BIASED AND CB JUNCTION REVERSE BIASED

6 ISSN (ONLINE) : X ISSN (PRINT) : X Available online at International Journal of Advanced Research in Biology, Ecology, Science and Technology (IJARBEST) Vol. 1, Issue 4, July 2015 * In Fig 2.6, EB & CB junctions are forward biased Barrier otential at EB junction and CB junction reduces Electrons flow from n-tye to - tye. * In Fig 2.7, EB & CB junctions are reverse biased Emitter and collector currents are due to thermally generated minority carriers. * In Fig 2.8, when EB junction is forward biased, Barrier otential reduces Electrons flow from n- tye emitter to -tye base. Since Base is thin and lightly doed, small ortion of base electrons recombines with holes and constitutes base current. X OPERATION OF PNP TRANSISTOR a) n TRANSISTOR WITH EB JUNCTION & CB JUNCTION FORWARD BIASED: n V EE V CC b) n TRANSISTOR WITH EB JUNCTION & CB JUNCTION REVERSE BIASED: E C V EB B V CB V EE V CC C) n TRANSISTOR WITH EB JUNCTION FORWARD BIASED & CB

7 ISSN (ONLINE) : X ISSN (PRINT) : X Available online at International Journal of Advanced Research in Biology, Ecology, Science and Technology (IJARBEST) Vol. 1, Issue 4, July 2015 JUNCTION REVERSE BIASED E C V EB + - V CB + - Fig n TRANSISTOR WITH EB JUNCTION FORWARD BIASED & CB JUNCTION REVERSE BIASED * In Fig 2.9, Both EB and CB junctions are forward biased Emitter and and Collector currents are large. * In Fig 2.10, Emitter Base junction and Collector Base junction are reverse biased Emitter and Collector currents are small due to thermally generated minority carriers. * In Fig 2.11, Emitter base junction is forward biased Lot of holes cross from emitter region to collector region. Since base is thin and lightly doed, small ortion of base electrons recombines with holes and constitutes small base current. X

8 UNIT - II 2.3 CURRENT EQUATIONS BIPOLAR JUNCTIONS CURRENTS IN TRANSISTOR: V EB V CB Fig 2.12 CURRENTS IN TRANSISTOR * EB junction is forward biased and CB junction is reverse biased. CURRENTS IN TRANSISTOR EMITTER CURRENT BASE CURRENT COLLECTOR CURRENT COLLECTOR CURRENT: I c = dc I E + I CBO 1 Current which leaves Collector base junction = dc I E Collector base junction is reverse biased

9 Minority carriers in base move across junction and constitutes small reverse saturation current called as COLLECTOR TO BASE LEAKAGE CURRENT (I CBO ) From 1, = I c I CBO dc I E QI CBO << I C, COMMON BASE CURRENT GAIN, dc I C I E 2 Common base current gain ( dc ) is defined as the ratio of Collector current to Emitter current. Collector current I is controlled by base emitter voltage. c I = I ex V BE c sc V T (I sc Source current in collector side) EMITTER CURRENT Current due to flow of holes from Emitter to base when EB junction is forward biased. I E =I C + I B Emitter current I E = I SE ex V BE V T

10 I SE Source current in emitter side BASE CURRENT: I C = dc I B +I CEO 3 I CEO << I C, = I C I CEO dc I B dc I C I B 4 Common Emitter current gain ( dc )is defined as the ratio of Collector current to Base current. Base current I is controlled by base emitter voltage. I = I ex V BE B SB B V T CURRENT EQUATIONS: ; I SB Source current in base. X * Current Equations of BJT can be derived from current equations in a junction diode. * Consider forward biased n junction. By alied voltage, holes are injected into n-side and electrons into -side of diode. Let n ' (x) increase in minority carrier concentration above equilibrium n0 hole concentration in n-side at equilibrium. decrease in hole concentration due to recombination. n ' (x) = - n n n0 Continuity equation states that Rate of change of hole concentration = Sum of all increase in hole concentration For steady state, d = n 0 n 1 dj dt q dx d = 0 dt 0 =

11 n 0 n 1 dj q dx 1 dj = q dx n 0 n dj dx = q( n 0 n ) 1 Hole diffusion current density d J dx J = q D d dx (D diffusion constant for holes)

12 Hole diffusion current density Subs2 in 1 J = q D d n dx 2 d qd d n = q n 0 n dx dx 2 d qd n q ( = n 0 n ) 2 dx 2 n = n n 0 2 dx D P d 2 n n n 0 = L dx 2 2 d 2 n = ( n 0 n ) dx D Diffusion length for holes (L ), (Average distance travelled by hole before recombination) Since d 2 L = (D ) 1 2 n ' = n n0 d 2 ' ( x) n n = dx 2 L 2 Solution of this equation is given by ' ( x ) = k e x / L P + k e x / L P To find k 1 and k 2 : ' At x =, (x) n = 0 n (where k, k constants) At x = 0, Diffusion current, 0 = 0 + k 2 k 2 = 0 ' n (0) = k 1 k 1 = n (0) ' ( x) = ' (0)e x / L + 0 n n = ' (0)e x / L n x / L = ( n ( x) n 0 )e 3 '

13 I n (x) = AJ = A( qd d n ) dxx d = qad ( ) dx n 4 We have n ' (x) = n - n0 n = n ' (x)+ n0 d n = d n '(x) dx dx d ' n(x) ) 4 I n (x) = qad dx d = qad [( (x) )e ] x / LP dx n n0 (Q from 3) n = qad '(0)e x/ / L P LP I n (x) = qad L ' (0)e n x/l P I n (x) = AqD L ( n (0) n0 )e x/l P Minority diffusion current crossing junction at x = 0 is I n (0) = AqD L ( n (0) n0 ) I n (0) = AqD L ' n (0)

14 And total current density for hole is J =Drift current + Diffusion current density for holes d J = qµ E - qd dx Einstein s relation states that Drift current density + Diffusion current Density for holes for holes d J = q E qd dx At fixed temerature, Ratio of diffusion constant to mobility is constant D D = n = kt n where T Temerature in ºK k Boltzmann constant in ev/ºk Voltage equivalent temerature Junction otential Electric field intensity, V T = KT V j =V 0 -V E = V T d dv = dx dx

15 d = dv n (0) d P 0 V T Vj dv = V 0 T ln n (0) = 1 (V ) j V 0 T ln n (0) = 1 (V V) 0 V o T n (0) = 0 e (V 0 V ) /V T 5 By Law of Junction, V 0 = V T ln 0 n 0 V 0 = ln V T 0 n 0 e V0 / VT = 0 n 0 V0 /VT 0 = n0 e 6 Subs 6in5, (0) = e V 0 /V T n We know that = n0 e (V 0 V )/V T e (V 0 V 0 +V )/V T n0 n(0) = n0 e V /V T I n (0) = AqD L n '(0)

16 = AqD L ( n (0) n 0 ) = AqD L ( V / V e T ) n 0 n 0 I (0) = AqD n0 n L (e I (0) = AqD n 0 n L I = I n (0) + I n (0) n V /VT 1) (e V /V T 1) = AqD L n0 (e V /V T 1) + AqD n L n n 0 (e V /V T 1) I = I V /V 0 ( T e -1) where I 0 = AqD n0 + AqD n n 0 L L n REVERSE SATURATION CURRENT: I = Aq D n0 + D n n 0 0 L L n n 2 n 2 n0 = i and n 0 N D 2 I = Aq D n i 0 L N D i = N A 2 + D n n i L n N A D I = Aq D + n 0 n 2 L N L N D n A i

17 Diode current Equation: Alied Voltage and current are related by where I 0 = reverse saturation current V = alied voltage I = diode current V T = Volt equivalent temerature V /V I = I T 0 (e 1) = KT q At any temerature T T V T = = ,600 At room temerature, 300 V T = 11,600 = 26mV η = 1 for Germanium η = 2 for Silicon For forward bias voltage, Current Equation is I = I 0 (e V /V T ) For reverse bias voltage Current Equation is -V/ηV I = I 0 (e T 1)

18 Note : V / VT I = I 0 ( e 1) D I = Aq D n n 2 V / VT ( e 1) i L N L D n N A I D D J = = qn 2 n i L N (e V / VT 1) A D L n N A = qn 2 D D i D N + n (e V / V T D D n n N 1) A J = qn 2 D 1 D n 1 i + (e V / V T n N 1) N D A 2.4 INPUT AND OUTPUT CHARACTERISTICS OF CE, CB AND CC CONFIGURATION (May /June Marks) X TYPES OF CONFIGURATION COMMON EMITTER(CE) COMMON BASE CONFIGURATION: Fig 2.13 n TRANSISTOR

19 Fig 2.14 nn TRANSISTOR Base is common to both inut and outut terminals. Base is close to ground otential. Inut and Outut characteristics exlains the behaviour of transistor. A) CIRCUIT ARRANGEMENT: I B Fig 2.15 CIRCUIT ARRANGEMENT B) INPUT CHARACTERISTICS * Relates i/ current (I E )to i/ voltage(v BE ) for different values of o/ voltage (V CB ) * Outut voltage (V CB )is ket fixed and inut voltage (V BE )is varied in stes and corresonding inut current (I E )is recorded.

20 Fig 2.16 Inut Characterstics * When outut voltage is 0, Emitter base junction is forward biased and so inut characteristics are closed to forward biased n junction diode. I F V F * When V CB is increased, distance between Emitter - base and Collector base deletion region reduces which reduces resistance between 2 regions. So V CE increases. C) OUTPUT CHARACTERISTICS: Plot between Collector to base voltage and Collector current for various levels of Emitter current.

21 }IE Fig 2.17 OUTPUT CHARACTERISTICS OUTPUT CHARACTERISTICS 1. ACTIVE REGION: CUTOFF REGION * Used for oerating transistor as an amlifier * Emitter-base junction is forward biased and Collector base junction is reverse biased. As I E increases, I C increases I C ~ I E (if dc 1) 2. SATURATION REGION: * Emitter base and Collector base junctions are forward biased. * Region that lies to left of V CB =0

22 * When CB junction is forward biased, flow of charge carriers is reduced I C reduces to CUT OFF REGION * Emitter base and collector base junctions are reverse biased. * Region where I C = COMMON EMITTER CONFIGURATION: Emitter current is common to both inut and outut terminals. X nn TRANSISTOR n TRANSISTOR Fig (a) nn TRANSISTOR (b) n TRANSISTOR

23 a) CIRCUIT ARRANGEMENT: V CC b) INPUT CHARACTERISTICS: Fig 2.19 CIRCUIT ARRANGEMENT * Plot between inut current (I B ) and inut voltage (V BE ) for various values of outut voltage (V CE ) * Till cutin voltage, Base current is zero and increases exonentially as V BE increases. * When V CE increases, Width for constant V BE. c) OUTPUT CHARACTERISTICS: of deletion region increases Base current decreases Plot of Collector to Emitter voltage (V CE ) to Collector current (I C )for constant base current(i B ) Fig 2.20 a) Inut charactertics b) Outut characteristics

24 1. Active Region: Base Emitter junction is forward biased and Collector base junction is reverse biased. When V CE = 0, I c is small. 2. Saturation Region: Emitter base junction and collector base junctions are forward biased. Increase in base current I B roduces increase in I C. V CE in saturation region (V CE,sat ~ 0.2V) 3. Cut off Region: Emitter base junction and Collector base junctions are reverse biased. I C = α dc I E + I CB0 1 I C = β dc I B + I CE0 2 When I E = 0, I C = I CBO When I B = 0, I C = I CEO and I CBO are related by I CEO I CBO I = CEO 1 α dc β = dc α dc 1 α dc X

25 COMMON COLLECTOR CONFIGURATION: * Collector terminal is common to both inut and outut terminals. * It has high inut imedanc ce and low outut imedance. Fig 2.21a) n TRANSISTOR b) nn TR ANSISTOR A) CIRCUIT ARRANGEMENT R E R B Fig 2.22 CIRCUIT ARRANGEMENT

26 B) INPUT CHARACTERISTICS: Plot of Base current (I B )and Collector to Base Voltage (V CB ) When V CB increases, base current I B decreases and reduces to 0. C ) OUTPUT CHARACTERISTICS: Plot between I E and V CE I B (A) I C I E ( Common collector outut characteristics similar to Common emitter outut) I E (ma) V CB (V) Fig 2.23 a) INPUT CHARACTERISTICS b) OUTPUT CHARACTERISTICS X DEFINITION OF,, : A) LARGE SIGNAL CURRENT GAIN ( ) [CURRENT AMPLIFICATION FACTOR]: Ratio of change in Collector current constant V CB ( I C ) to change in emitter current ( I E ) at α = V CB = Constant B) TRANSPORT FACTOR ( ): I C I E Ratio of change in Collector current ( I c ) to change in base current ( I B ) at constant V CE = I C I B V CE = Constant

27 C) EMITTER EFFICIENCY ( ): Ratio of change in Emitter current constant V CE ( I E ) to change in base current ( I B ) at = I E I B V CE = Constant X RELATIONSHIP BETWEEN(,, ) A) REL ATION BETWEEN α AND γ: I E = I B + I C I B = I E I C I B = I E I C by I C, I B = I E I C I C I C I C We know that = I C I E and = I C I B 1 1 = 1 1 = = 2 ( in terms of ) From 1, 1 1 = + 1

28 = 1+ B) RELATION BETWEEN AND γ: We have We know that I E = I B +I C I B = I E -I C I B = I E I C 1 = I E I C by I B, I B I B = I E I B and = I C I B 1 = 3 ( in terms of ) = 1+ 4 ( in terms of ) We know that = 1 = 1+ ( Qfrom 4) 1 1 = 1 ( in terms of ) COMPARISON BETWEEN CE, CC AND CB CONFIGURATIONS X COMMON BASE(CB) COMMON EMITTER (CE) COMMON COLLECTOR CONFIGURATION CONFIGURATION (CC) CONFIGURATION I/P resistance- Low I/ resistance - MODERATE I/P resistance- HIGH O/P resistance- HIGH O/ resistance - MODERATE O/ resistance- LOW CURRENT GAIN CURRENT GAIN HIGH CURRENT GAIN HIGH UNITY Voltage gain is low Voltage gain is high Voltage gain is almost unity X

29 PROBLEM :1 Determine the value of base current of common base configuration whose current amlification factor is Emitter current is 1mA. Solution: Given : -3 I E = 1 10 A = 0.92 = I C 0.92 = I E I C I C = I E = I B + I C I B = I E I C = ( ) ( ) = I B = 0.08mA 3 X PROBLEM :2 At V CE =7.5V, change in collector current is 1.2mA for change in base current of 20 A. Find of transistor. Solution: Given : At V CE = 7.5V 3 I C = A 6 I B = A = I C I V B CE = = 60 X

30 2.5 EARLY EFFECT OR BASE WIDTH MODULATION If actual Base width is W B and width of deletion region is W, ' Effective electrical base width W = W -W B B Deendency of Base width on Collector Reverse bias is known as EARLY EFFECT Base width varies with increase in reverse Collector voltage, so early effect is also known as BASE WIDTH MODULATION Early effect can be seen in current voltage characteristics. x = 0 x = x B Fig 2.24 Change in base width and Change in Minority carrier Gradient with Change in B-C sace Charge width Reduction in base width Increase in Gradient in minority carrier concentration Increase in diffusion current. (Early Voltage) Fig 2.25 I C Vs V CE showing Early Effect and Early Voltage

31 Early effect roduces non zero sloe finite outut conductance (g 0 ) If Collector current is 0, curves interest voltage axis at a oint called as EARLY VOLTAGE di C dv CE I = C VCE A = g0 V I C = g 0 (V CE + V A ) EFFECTS OF BASE WIDTH MODULATION: * As Base Width decreases No.of Majority carriers that recombine with minority carriers decreases Base current decreases. * As Base width decreases, concentration gradient of minority carriers increases. * For large reverse bias, Base width may be reduced to zero Voltage breakdown in transistor. This is called PUNCH THROUGH 2.6 BREAKDOWN IN TRANSISTORS: 1) AVALANCHE MULTIPLICATION: * Base - Collector junction is reverse biased Breakdown occurs called as Avalanche Breakdown. * Avalanche Breakdown is caused by imact ionization. * Because of High Kinetic energy, electron hole air is generated in collector. * By Electric field, holes are forced to base which induces electron current MI C * When M>1 avalanche (unlimited increase in collector current without external control 2) REACH THROUGH (PUNCH THROUGH) : * Increase in reverse bias Increase in deletion region. * Since base is lightly doed, deletion region enetrates deeer into base and undeleted art of base becomes narrower. * Further increase in reverse bias Deletion region sreads comletely to reach emitter junction. This is known as REACH THROUGH or PUNCH THROUGH

32 * Decrease in Emitter base Voltage Emitter current increases Transistor Breakdown. X 2.7. HYBRID MODEL OR h- PARAMER MODEL (May /June Marks) TWO PORT NETWORK: v 1 v 2 Fig 2.26 TWO PORT NETWORK If two - ort device is an ideal transformer, and if it is linear 1 = h 11 i 1 + h 12 V 2 1 i 2 = h 21 i 1 + h 22 V 2 2 h 11,h 12,h 21,h 22 h arameters or hybrid arameters. h 11 = v 1 i 1 V 2 = 0 h 21 = i 2 i 1 V 2 = 0 h 12 = v 1 v 2 i 1 = 0 h 22 = i 2 v 2 i 1 = 0 h 11 = inut resistance h 21 = short circuit current gain h 12 =Reverse oen circuit voltage amlification h 22 = Outut conductance v,v, i i are functions of time.

33 h i 21 1 Fig 2.27 HYBRID MODEL FOR TWO -PORT NETWORK Aly KVL to first loo, V 1 = h 11 i 1 + h 12 V 2 3 Aly KCL to second loo, i 2 = h 21 i 1 +h 22 V 2 1=3 and 2=4 4 Hybrid model is verified. Christo Ananth et al. [2] discussed about Imroved Particle Swarm Otimization. The fuzzy filter based on article swarm otimization is used to remove the high density image imulse noise, which occur during the transmission, data acquisition and rocessing. The roosed system has a fuzzy filter which has the arallel fuzzy inference mechanism, fuzzy mean rocess, and a fuzzy comosition rocess. In articular, by using no-reference Q metric, the article swarm otimization learning is sufficient to otimize the arameter necessitated by the article swarm otimization based fuzzy filter, therefore the roosed fuzzy filter can coe with article situation where the assumtion of existence of ground-truth reference does not hold. The merging of the article swarm otimization with the fuzzy filter hels to build an auto tuning mechanism for the fuzzy filter without any rior knowledge regarding the noise and the true image. Thus the reference measures are not need for removing the noise and in restoring the image. The final outut image (Restored image) confirm that the fuzzy filter based on article swarm otimization attain the excellent quality of restored images in term of eak signal-to-noise ratio, mean absolute error and mean square error even when the noise rate is above 0.5 and without having any reference measures. TRANSISTOR HYBRID MODEL: * h arameters can be obtained from transistor static characteristic curves i C i B v c v B

34 i B, i C instantaneous currents V B,V C instantaneous voltages V B = f 1 (i B,V C ) i c = f 2 (i B,V C ) 5 [V is a function of i and V ] B B C 6 [i is another function of i and V ] C B C Taking Taylor s series exansion of 5and6 f 1 f V B = i B + 1 i B V C V C I B V C 7 f 2 i C = i B + i B V C f 1 V C I B V C 8 V B, V C small signal base and Collector voltages. i B, i C small signal base and Collector currents. 7and8 can be rewritten as: V b =h ie i b +h re V C i C = h fe i b + h oe V C where f h ie = 1 i B V C f h re = 1 V C I B f 2 h fe = ib V C 9 10 } h- arameters of Common connection Emitter f h oe = 2 V C I B

35 f h 1 ie = = i B V C V B i B V C f h 1 re = = V C I B V B V C I B h fe = f 2 I B V C = i C i B V C h oe = f 2 V C I B = i C V C I B

36 h- PARAMETER MODEL FOR CE, CB, CC CONFIGURATION i B +i C +i E = 0 Fig 2.29 h- PARAMETER MODEL FOR CE, CB, CC CONFIGURATION (May /June Marks)

37 DETERMINATION OF h PARAMETERS FROM CHARACTERISTICS: * h fe DETERMINATION: We know that h fe = i c i B i C i B V C I C(mA) V BE (V) i C2 I i C C1 i B2 B i = I B B V B2 VB Q i B1 V b1 V C2 V C1 V CE = V C V C V CE(V) I B i B (m A) Fig 2.30 (a) CE = OUTPUT CHARACTERISTICS (b) CE = INPUT CHARACTERISTICS * Base currents are taken around quiescent oint Q (i B =I B ) and to collector voltage V CE =V C around quiescent oint Q. h = i C 2 i C 1 * fe i B 2 i B1 A) h oe DETERMINATION: h oe i = V C C i C V C I B * h oe at quiescent oint Q is given by sloe of outut characteristic curve at that oint. * Sloe can be evaluated by drawing line AB tangential to characteristic curve at oint Q. Christo Ananth et al.[3] resented a brief outline on Electronic Devices and Circuits which forms the basis of the Clamers and Diodes.

38 B) h ie DETERMINATION: h ie = V B i B V B i B V C * h ie at quiescent oint Q is given by sloe of inut characteristic curve at that oint. * Sloe can be evaluated by drawing line EF tangential to characteristic curve at oint Q C) h re DETERMINATION: h re V B = V C V B V C I B * Vertical line on inut characteristics reresents constant base current. h = V V B 2 B1 re VC 2 V C1 2.8 EBERS -MOLL MODEL X * Based on interacting diode junctions. * Alicable to any transistor oerating modes. E n n I E -V BE + V BC I C C I B B Fig 2.31 EBERS - MOLL - MODEL I E +I B +I C =0 1

39 Collector current I C =α F I F - I R 2 where α common base current gain in forward active mode F Here I C = α F I F + I CS 3 where I CS reverse bias B-C junction current. qv BE I F = I ES ex kt 1 I = I R CS ex qv BC kt 1 Fig 2.32 EBERS - MOLL EQUIVALENT CIRCUIT I = I ex BE FORWARD CURRENT, F ES qv 1 KT 4 When B-C junction becomes forward biased, I = I ex BC REVERSE CURRENT, R CS qv 1 KT 5 Substitute 4and 5 in 2, I C = F I ES ex qv BE KT 1 I ex qv BC CS KT 1 6

40 Similar to2, Emitter current can be written as : I E = R I R I F 7 substitute 4and 5 in 7 I = I E R CS qvbc ex KT 1 I ES ex qv BE KT 1 8 By recirocity relation, F I ES = R I CS 9 * In saturation mode, BE and BC junctions are forward biased V BE >0and V BC >0 V CE (sat) = V BE -V BC 10 Substitute8 in1 qv BC qv BE I + I = I ex 1 I ex 1 B C R CS KT ES KT (I B I qv C ) = R I CS ex BC qv BE 1 I ex 1 ES KT KT V (sat) V V V ln I (1 ) + I I = = c R B CS CE BE BC t ( F I B (1 F )I C ) I ES I CS I ES F R

41 UNIT - II V ( sat) = V ln I C (1 α R ) + I B α F CE t (α I (1 α )I F B F C α R 2.9 GUMMEL POON MODEL X BIPOLAR JUNCTIONS * This model is used if there is non uniform doing concentration in base. Electron current density in base of nn transistor, J n = q n n( x)e + qd n dn( x) dx 1 Electric field, E =V T 1 (x) d(x) dx E = KT q 1 (x) d(x) dx 2 where (x) majority carrier hole concentration in base Substitute 2in1 J = q n(x) KT 1 d(x) dn(x) + qd n n q (x) dx n dx 3 By Einstein s relation, 4can be rewritten as J qd = n d(x) dn(x) n(x) + (x) (Q KT = D ) n ( x) dx dx n n q J n = qd d ( n n ) ( x) dx 4

42 J n ( x) d ( = n ) qd n dx 5 Integrating 5, J n x B qd n 0 x B ( x)dx = o = ( (x B )n(x B ) (0)n(0) 6 We can assume B-E junction is forward biased and B-C junction is reverse biased n(0) = n B 0 ex(v BE / V t ) n(x B ) = 0 n B0 = n i d ( x) n dx dx 2 6 J = n 2 qd n n i ex (V BE /V t ) x B (x)dx 0 7 * Integral in denominato or Total majority carrier charge in base Base Gummel number (Q B ) 2 qd n ex(v / V ) i BE t Similarly J = x E n(x')dx' o * Integral in denominato or Total majoritycarrier charge in emitter Emitter Gummel Number (Q ) E

43 2.9.1 EARLY EFFECT AND HIGH - LEVEL INJECTION: * When CB voltage changes Neutral base width changes Base Gummel number Q B changes Electron density - a function of CB voltage. This is called Base width modulation or Early effect. * When B-E Voltage becomes very large, high level injection is alied Total hole concentration in base increases Base Gummel number Q B changes Electron current density J n changes. This is called high level injection HYBRID - PI MODEL X Small signal equivalent circuit of BJT using small - signal admittance arameters of n junction. B + V be I b I c + C V ce E Fig 2.33 COMMON EMITTER nn BJT

44 E B C Fig 2.34 nn BIPOLAR TRANSISTOR FOR HYBRID - PI MODEL * C,B,E terminals external connections to transistor C ',B ',E ' terminals idealized internal connections to transistor. B r b B ' V C C je b'e' π r π V b ' e ' r ex Fig 2.35 a) Hybrid -PI Equivalent circuit Between Base and Emitter C ' r c g m V b 'e ' r o C s E ' b) Hybrid -PI Equivalent Circuit Between Collector and Emitter

45 Fig 2.35 (c) Hybrid - PI Equivalent circuit between Base and Collector * In Fig (a), r b series resistance in base between external base terminal B and internal base region B '. * B ' - E ' junction is forward biased C Junction diffusion caacitance r Junction diffusion resistance C = C d r = r d * C and r is arallel to junction caacitance C je * r ex series resistance between external emitter terminal E and internal emitter region E'. * In Fig 2.35(b), r c series resistance between external collector terminal C and internal collector region C '. C S junction caacitance of reverse biased Collector - substrate junction. g m V ' ' Collector current controlled by internal base emitter voltage. b e 1 r 0 = due to early effect g 0 where g 0 outut conductance * In Fig 2.35 (c), C = reverse biased junction caacitance r = reverse biased diffusion resistance.

46 C << C Miller caacitance Equivalent caacitance between B ' and E ' due to C and feedback effect. Fig 2.36 HYBRID - PI EQUIVALENT CIRCUIT HYBRID - PI MODEL PARAMETERS IN TERMS OF h-parameters 1) TRANSISTOR TRANSCONDUCTANCE, g m : g m 0 I = E V T g m ~ I C V T Transconductance is directly roortional to collector current and inversely roortional to Volt equivalent temerature. 2) INPUT CONDUCTANCE g : b ' e Inut resistance r ' = b e h g h fe m

47 = h fe = ( I C / V T ) h fe V T I C r ' b e = h fe g m Inut conductance g ' b e g m = h fe 3) FEEDBACK CONDUCTANCE g ' : b c r ' b c = h r ' re b e g b 'c = h re g b 'e 4) BASE SPREADING RESISTANCE ( r bb' ) We know that r bb' = h ie r b'e inut resistance h r = fe b'e g m h fe h V = I /V = I fe T C T C r bb ' = h h V fe ie I C T

48 5) OUTPUT CONDUCTANCE (g ce ) h oe = I C V ce = 1 + r ce 1 r b 'c g m h re h oe = g ce + g b ' c + g mh re = g ce + g b'c + g b' e h fe h re (Q g b'e = g m ) h fe h oe = g ce g b' c g b ' e h fe g ' g b c b ' e (Q g b ' c = h reg b ' e ) = g ce + g b'c + h fe g b ' c = g ce + g b'c (1 + h fe ) g ce = h oe (1 + h fe )g b'c X 2.11 MULTI - EMITTER TRANSISTOR INTRODUCTION: Secialized BJT used at inut of TTL NAND logic gates. Inut signals are alied to emitters Collector current stos flowing only if all emitters are driven by LOGIC HIGH VOLTAGE. Relace diodes of DTL and allows reduction of switching time and ower dissiation.

49 Fig 2.37 SYMBOL OF MULTI EMITTER TRANSISTOR STRUCTURE: * Multi emitter transistor consists of a wafer of semiconductor material having discrete emitter regions surrounded by base region. * Base electrode consists of grid of solder connected to base region. * A searate button of solder is connected to each emitter region. * Emitter electrode consistss of metal late connected to each solder buttons and saced from base electrode. 76

50 Fig 2.38 STRUCTURES OF MET 77

51 * Body of material consists of wafer of crystalline semiconductor material and N tye semiconductor material. * Wafer Mono crystalline silicon which is heavily doed with donor imurity (Phoshorus)to give N + conductivity. * Eitaxial layer of N tye silicon is deosited on wafer surface by a technique called SEMICONDUCTOR ART * The layer is formed by assing mixture of hydrogen and silicon chloride over heated wafer. * Base layer is formed in collector layer by diffusing imurity through collector layer surface through diffusion technique called as TRANSISTOR ART. * Base layer (P layer) is diffused in N layer to form PN junction. (Figure (a)) * Electrically insulating coating is deosited on diffused base layer by SEMI CONDUCTOR ART. Insulating coating consists of Silicon dioxide which is formed by thermal oxidation of Base layer. * In figure (b), Oenings are etched in insulated coating with etchant using hotolithograhic technique known as SEMI CONDUCTOR ART. Here hotoresist coating is alied to oxide coating which is exosed to attern of light to harden selected areas. Remaining areas are removed by solvent. * Emitter regions are diffused in Base layer by heating base layer in ambient including N tye imurity (PHOSPHORUS PENTOXIDE) (FIGURE (b)) * Silicon dioxide coating is combined with insulating coating. Insulating coating is thicker in base region and thinner in emitter regions.(figure (c)) * Silicon dioxide insulating coating is etched using hotolithograhic masking and Etching techniques to rovide searate oenings over each emitter regions. Communicating grooves are formed outside the oenings. * Major surface exosed by oenings and grooves are coated by evaoration or lating with metal (Nickel)by electroless lating to roduce thin nickel coating over exosed ortions of major surface.(figure (d)) * Coating is exosed to molten solder by diing and searate button of lead is formed over coating on emitter regions. Metallic base contact is also formed over nickel coating in each of the grooves.(figure(e)) 78

52 * All emitter regions are connected. Emitter contact of metal (coer)is disosed over base contact and in contact with emitter buttons. * Emitter contact is electrically connected to each of emitter buttons by heating transistor structure and emitter contact to a temerature at which emitter buttons fuse to emitter contact.(figure(f)) * A stri of metal (coer) consists of square loo ortion connected to stra ortion. * Embodiment of transistor is mounted in casing of metal. * Casing is used as heat sink and rotection mechanism. * N + Silicon wafer is soldered to casing. Stri is connected to one side of casing and insulated by electrical insulator. * External lead (not shown) is soldered to stri for external circuit connections. Christo Ananth et al. [4] discussed about PN junction diode, Current equations, Diffusion and drift current densities, forward and reverse bias characteristics and Switching Characteristics of Semiconductor Diodes. X REFERENCES [1] Christo Ananth, S.Esakki Rajavel, S.Allwin Devaraj, P.Kannan. "Electronic Devices.", ACES Publishers, Tirunelveli, India, ISBN: , Volume 2,December 2014, : [2] Christo Ananth, Vivek.T, Selvakumar.S., Sakthi Kannan.S., Sankara Narayanan.D, Imulse Noise Removal using Imroved Particle Swarm Otimization, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), Volume 3, Issue 4, Aril 2014, [3] Christo Ananth, W.Stalin Jacob, P.Jenifer Darling Rosita. "A Brief Outline On ELECTRONIC DEVICES & CIRCUITS., ACES Publishers, Tirunelveli, India, ISBN: , Volume 3,Aril 2016, : [4] Christo Ananth, Monograh On Semi Conductor Diodes, International Journal of Advanced Research in Biology, Ecology, Science and Technology (IJARBEST), Volume 1,Issue 3,June 2015, :