CMOS RE-CONFIGURABLE MULTI-STANDARD RADIO RECEIVERS BIASING ANALYSIS

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1 Électronique et transmission de l information CMOS RE-CONFIGURABLE MULTI-STANDARD RADIO RECEIVERS BIASING ANALYSIS SILVIAN SPIRIDON, FLORENTINA SPIRIDON, CLAUDIUS DAN, MIRCEA BODEA Key words: Software defined radio, Direct conversion receiver, Low noise amplifier, Negative feedback amplifier, Constant-g m biasing. This paper presents the analysis of CMOS re-configurable multi-standard radio receivers biasing targeting the bias circuit optimum design taking into account the RF design specifics, in order to immunize the receiver s building blocks key parameters to process and temperature variation effects. A constant g m R current reference accomplishes the task by generating a bias current that tracks with process and temperature. The biasing block circuit implementation is described for both the high frequency and the baseband parts of a multi-standard receiver and an analysis on the tracking accuracy is presented. 1. INTRODUCTION The homodyne quadrature down-converter architecture provides the optimum solution for the implementation of CMOS Re-Configurable Multi-Standard Radio Receivers [1]. In [] the multi-standard receiver architecture has been presented and the receiver building blocks have been introduced. Basically, the receiver chain is split into a high frequency part (HF), comprised by the Low Noise Amplifier (LNA) and the g m stage of the quadrature down-converter mixer (MIX) and a remaining baseband, low-frequency (LF) part, following the mixer s switching stage. After mixing, the signal is conditioned by a channel selection Low Pass Filter (LPF) and a Variable Gain Amplifier (VGA), before its conversion to digital by an analog-to-digital converter (ADC). The receiver design is a result of noise / linearity trade-offs under power consumption constraints. The receiver s HF part is shaped mainly by noise requirements, while its baseband blocks must implement a linear channel selection to prevent the RF signal distortion. The wireless receivers noise and linearity performance figures of merit for the HF part are the noise figure (NF) and the input referred third order intermodulation intercept point (IIP3) and, respectively, for the LF part, the signal to noise ratio (SNR) and third order intermodulation (IM3). Politehnica University of Bucharest, Electronics, Telecommunication and Information Technology Faculty, Romania; silvian.spiridon@gmail.com Rev. Roum. Sci. Techn. Électrotechn. et Énerg., 57, 3, p. 81 9, Bucarest, 1

2 8 Silvian Spiridon et al. Table 1 Preferred bias for the re-configurable multi-standard receiver building blocks Block Parameter Equation Preferred Bias LNA MIX LPF, VGA GAIN A v g m R L constant g m R NOISE NF ~ 1 / ( 1 + g m R L ) constant g m R INPUT IMPEDANCE Z in ~ const / ( 1 + g m R L ) constant g m R GAIN A v ~ const g m R L constant g m R LINEARITY IIP3 ~ 1 / g m R L constant g m R NOISE SNR 1 +const / g m R L constant g m R LINEARITY IM3 ~ 1 / g m constant g m Table 1 summarises the key parameters related to receiver noise-linearity performance and emphasizes the preferred bias, []. All key receiver s parameters depend either on the product between their input stage g m and their load resistor, R L, or just on their input stage g m. Given the information Table 1 provides the main requirements for the bias circuit become clear: it must ensure minimal process and temperature related variations of the receiver noise and linearity performance. A constant g m R current reference 3 accomplishes the task, by generating a bias current that tracks with process and temperature. The proposed biasing technique is analyzed in Section, while Section 3 calculates the impact of process and temperature variations on the key parameters of the receiver employing a constant g m biasing. Section 4 concludes the paper by showing the proposed bias confirms the initial suppositions.. PROPOSED BIASING TECHNIQUE Constant g m R CMOS biasing circuits are inspired by Proportional-To- Absolute Temperature (PTAT) bipolar current source [3]. The biasing circuit idea is illustrated by the basic schematic presented in Fig. 1. Making transistor M1 larger than transistor M, I REF current is generated over R, as the current mirror, represented by equally sized devices M3 and M4, force equal currents to flow through M1 and M. The final implementation of this biasing circuit require start-up circuitry to avoid transistors zero current circuit s stable state. The output current, mirrored by M5, is given by I OUT = NI REF, (1) where N represents the ratio between the output current source M5 size and diode connected M3 size.

3 3 CMOS re-configurable multi-standard radio receivers biasing 83 Fig. 1 Constant g m R biasing current source. The I REF current is given by VOV1 I REF = ( R P 1), () where P =(W 1 /L 1 )/(W /L ) is M1 and M transistors sizes ratio, M1 being the largest device, and V OV1 is the overdrive voltage of M1. The overdrive voltage, V OV, of a MOS transistor operating in strong inversion and in saturation is K' W I D VOV = VGS VT = I D =, (3) L gm where V GS is the bias point gate-to-source voltage, V T the transistor s threshold voltage, I D the drain current, K = µcox µ being the channel charge carriers mobility and C ox the gate oxide specific capacitance, and W/L the transistor s aspect ratio. From equations () and (3) results that Fig. 1 current source provides a temperature independent g m R product: ( ) g m R = P 1. (4) This characteristic is realized at the expense of the reference current dependency on temperature, since equation () can also be written as: ( T ) 1 1 µ 1 ( ) P Cox W REF T = R, (5) L1 I where the channel charge carrier mobility depends on absolute temperature [4]:

4 84 Silvian Spiridon et al ( ) = K T µ T. (6) Given the temperature coefficient small value (a few ppm/ C) of the poly resistors implementing bias resistor R, the circuit of Fig. 1 can also be viewed as a constant g m biasing with temperature. The dependency of the reference current, I REF, versus M1, M transistors size ratio, P, with the ratio V OV1 /R as parameter calculated using equation () is presented in Fig. a. To optimize power consumption, the bias current value is typically smaller than 5 µa. A good practice is to keep I REF higher than 1 µa to maintain the mirroring ratio to the load circuit to reasonable values. The bias resistor, R, value is chosen such as the nominal I REF value is within the aforementioned range. The overdrive voltage V OV1 and size ratio, P, values are locked by matching requirements between the bias transistor M1 and its load counterpart, as is explained later. Based on equation (6), and neglecting resistor R weak temperature dependency, [5], the relative variation of I REF current with temperature,, results T as µ 1.5 ( T ) I REF ( T ) T = 1. 5 I ( T ) T 1.5 I REF T I REF T I =, (7) REF REF where I REF (T ) is the I REF nominal value at room temperature. Basically, within the commercial application temperature range ( 7 C), the I REF variation, relative to its nominal value at room temperature of 7 C, is about 35% as shown in Fig. b I REF [ma] V OV1 /R BIAS =1mA V OV1 /R BIAS =.5mA V OV1 /R BIAS =.ma V OV1 /R BIAS =.1mA V OV1 /R BIAS =.5m P I T REF [%] Temp [ C] a. b. Fig. a) I REF nominal value at room temperature versus M1, M size ratio; b) relative variation of I REF with temperature (resistor R is supposed temperature independent).

5 5 CMOS re-configurable multi-standard radio receivers biasing 85 Second order effects errors. To derive () and (5) some second order effects regarding the transistors M1, M were neglected, the most important being (a) threshold voltages mismatch (the threshold voltages were supposed to be identical) and (b) channel length modulation (supposed to be zero). Their impact on the overall value of the g m R product is to a great extent negligible, as the temperature dependency is not affected. In the presence of these second order effects (5) becomes ( g R) m k P 1 =, (8) 1 V T ( RI ) where V T is the M1, M threshold voltages mismatch and k factor describes the channel length modulation of M1, M effects, k 1+ λv REF DS1 =, (9) 1+ λvds where V DS is the transistors drain-to-source voltage and λ is the MOS device finite output conductance model parameter, g ds = λi D. The g m R product error, relative to its nominal value, results from (8) and (9): g ( ) m R g m R 1 k P 1 ε g m R = = 1. (1) g m R 1 VT ( RI REF ) P 1 Table presents λ parameter values versus transistor channel length evaluation for a generic 13 nm CMOS process, [, 6]. From Table results that the channel length modulation effect becomes negligible if M1 channel length is larger than.5 µm. Also as V DS = V GS, having a typical values of.5 1 V, the k factor values results very close to unity. Therefore equation (1) can be approximated as: ε gmr 1 VT 1. (11) 1 V T ( RI REF ) RI REF Channel length [µm] Table Channel length modulation vs. channel length for a.13 µm CMOS process Estimated λ [V 1 ] k k P P = V DS1 =.5 V, V DS = 1 V P

6 86 Silvian Spiridon et al V T mismatch due to different multiplicity [%] 1 P P V T mismatch due to process spread [%] L=.1µm L=.4µm L=.4µm L=1µm Overall V T mismatch [%] MP a) b) c) Fig. 3 V T mismatch vs. M1 M size ratio due to a) different multiplicity; b) process spread, 3σ VTp ; c) overall error; M is the smaller transistor and W /L = 5. The resulting mismatch for various channel length transistor presented in Fig. 3a confirms the expectations: for longer channel transistors the threshold mismatch is below 1%, regardless the size ratio; for nano-scale transistors V T increases with the size ratio increase, as V T absolute value becomes smaller. The process V T mismatch standard deviation of a MOS transistor pair is [8] σ WL, (1) VTp A VT where A VT is a process dependent parameter, measured in mv µm; A VT parameter has a value of about.5 mv µm for a.13 µm CMOS process. Equation (1) shows that transistor matching is better as the process minimum feature scales down and transistors area is larger, see Fig.3b and c presents the 3σ process V T mismatch and, respectively, the calculated overall V T mismatch. The plots show that for larger channel length of the CMOS pairs the matching is better, due to their overall much larger area for the same g m /I D ratio as opposed to smaller channel length devices. The error of g m R nominal value, ε gmr, was calculated based on Fig. 3 and Table data (Fig. 4) ε gmr [%] L [µm] Fig. 4 Relative error of the nominal value of g m R product versus M1 M channel length for I REF R = mv and a size ratio P =

7 7 CMOS re-configurable multi-standard radio receivers biasing 87 Hence, the proposed constant g m R current reference from Fig. 1 can track process spread over the targeted temperature range with a tolerance better than 5% for channel lengths larger than.4 µm. Given the relative large error of the of g m R nominal value, the analysis has neglected the effect of imperfect current mirroring of M3 and M4. There are a few simple and effective methods to realize precise current mirror, by trading off voltage headroom for precision, [9]. 3. THE IMPACT ON THE RECEIVER BLOCKS PARAMETERS The building blocks of RF and baseband receiver parts act as the load of the biasing circuit. The transconductance, g m, of their active devices is given by g m I BIAS NI REF P 1 VOV1 P 1 = = = N N, (13) V V R V R OV OV where I BIAS represents the bias current of a particular active device (e.g. LNA input stage transistor), N = I BIAS /I REF, and V OV is the load transistor overdrive voltage. Due to power efficiency constraints N is usually larger than 1, thus reducing the amount of current wasted in the biasing circuitry. The equation (1) approximation is valid within the assumptions the biasing circuit is placed in the vicinity of it s load; this way both circuits operate at the same temperature and the biasing transistors are an accurate, N times scaled, replica of their load. Most importantly their channel length should be identical and large enough to reduce the channel length modulation effect. The main purpose of the bias circuit is to provide a process and temperature independent g m R L, as all key RF circuit parameters depend on it (Table 1). RL gmrl N( P 1). (14) R Second order effects errors. There are three major sources of error that distance the g m R L product from equation (14) approximation: the mismatches in (a) threshold voltage, in (b) drain-to-source voltage of the bias reference transistor M1 and its load equivalent, and (c) between R L and R. These errors are the ones of main interest with respect to the practical implementation, rather than the errors in the nominal value of the g m R product. The designer main goal is to reduce process and temperature induced variations of the receiver key parameters, rather than biasing the circuits with extreme accuracy. The assumptions upon the approximation (13) was derived, are more appropriate for the baseband chain circuits. Their active devices channel length have to be much larger than the process minimum channel length in order to reduce DC offset and 1/f noise [1, 11]. OV

8 88 Silvian Spiridon et al. 8 a. b. Fig. 5 a) g m R L ; b) g m maximum relative error due to process mismatch. Oppositely, the high frequency amplifying transistors require a minimum channel length to allow operation at the highest cut-off frequency, thus maximizing the noise-power efficiency trade-off. In the presence of second order imperfections equation (14) becomes: L ( g R ) = N ( P 1) 1 + ε k ( 1 + ε ) m L R VT R, (15) R where ε VT, is the relative error in the threshold voltages of M1 and its load, ε R the relative error in matching between the load resistor and the bias resistor and k ' is a measure of channel length modulation of M1 and its load effects, given by 1+ λvds k =. (16) 1+ λv DS1 The relative error in the nominal value of g m R L is given by: g m R L ( g mrl ) ε gmr = = 1 k 1 + ε VT ( R ) L 1 + ε. (17) g R m L The estimated relative error of threshold voltage matching between two transistors is presented in Fig. 5. In Fig. 5a the maximum relative error of g m R L product versus channel length is depicted. Fig. 5b presents the maximum relative variation of g m of equation (13) with process spread, assuming the poly resistors have a tolerance of %. Depending on the transistors channel length values and on the multiplicity difference between them, the mismatch induced error can be as high as 13%. Typically the ratio between two poly resistors matches within 3%. Hence, the designer can assume ε R 3%.

9 9 CMOS re-configurable multi-standard radio receivers biasing 89 Table 3 Key receiver parameters vs. process variations Block Parameter Dependency LNA MIX LPF, VGA Maximum Variations [%] [db] GAIN A V NOISE NF 17.8 INPUT IMPEDANCE Z in g m R L 17 GAIN A V LINEARITY NOISE LINEARITY IM3 NF IM g m 7.7 For k ' factor the Table data points that for a channel length larger than.4 µm the channel length modulation cause a smaller than 5% systematic error if the DC drain-to-source voltages of M1 and its load are mismatched by.5 V. 4. CONCLUSIONS This paper presented the analysis of the best biasing technique for a re-configurable multi-standard wireless receiver. The proposed solution ensures minimal variation of the receiver s building blocks key parameters with process and temperature. A constant g m R current reference accomplishes the task, by generating a bias current that tracks with process and temperature. An analysis on the tracking accuracy of the g m R product was presented. Based on this paper analyses, Table 3 summarizes the expected variations with process of the key receiver parameters. It becomes obvious that at the expense of about one quarter of the total receiver power, this biasing technique can provide, with sufficient accuracy, a fairly constant multi-standard receiver performance, in terms of noise, linearity and gain, over the commercial temperature range and over the inherent process variations of a CMOS implementation. ACKNOWLEDGMENTS The authors would like to express their acknowledgment to dr. Frank Op t Eynde for triggering this analysis and for the fruitful discussions on the topic. Received on October 19, 1

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