20. Electromagnetic Compatibility for Integrated Circuits

Transcription

1 20. Electromagnetic Compatibility for Integrated Circuits E. Sicard 1, C. Marot 2, J. Y. Fourniols 3, and M. Ramdani 4 1 INSA/DGEI, 135 Av de Rangueil Toulouse - France etienne.sicard@insa-tlse.fr 2 Siemens VDO, Toulouse - France christian.marot@at.siemens.com 3 LAAS/CNRS, Avenue Roche, Toulouse - France fourniols@laas.fr 4 ESEO, Angers, France mohamed.ramdani@eseo.fr 1. ABSTRACT The electromagnetic compatibility (EMC) community, usually concerned with noise and interference at the electronic-system level, has recently focused more attention on integrated circuits (ICs). This review concentrates upon the recent advances in microelectronics technology, the understanding of internal couplings within ICs, parasitic emission, and susceptibility to radiofrequency interference. Highlights of measurement techniques, modeling, and design approaches are also proposed in this paper. 2. INTRODUCTION The increased complexity and the speed of ultra-large-scale integrated (ULSI) circuits, together with the push for decreasing the physical interconnection and device sizes, has dramatically increased parasitic effects inside integrated circuits, as well as noise and interference due to the integrated circuit. Microprocessors have long been the driving force behind size reduction. Over the past five years, the scaling-down of technology (Figure 1) has mainly affected the minimum dimensions of the active devices on the chip, called lithography. In 2002, the lithography commonly used in industry for high-performance integrated circuits should be around 0.12 µm, with research being done on µm scale devices. The maximum complexity of integrated circuits is approaching 1 billion transistors. The semiconductor roadmap for the next 10 years is described in [ with numerous details on the technological challenges and industrial issues. From the point of view of EMC issues within the integrated circuit, increased interconnection length, resistance, and shorter signal rise times lead to a variety of parasitic behaviors and coupling phenomenon. Part 3 reviews those effects, illustrated with the scaling-down of technology. From an external point of view, the integrated circuit is one of the major sources of 453

2 454 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani noise in electronic systems. Consequently, Section 4 is dedicated to parasitic emission of integrated circuits, with emphasis on microprocessors and programmable devices. In Section 5, the susceptibility of integrated analog and logic circuits is discussed. Lithography (µm) bit 16MHz 16 bit 33MHz 16 bits 66MHz 32 bits 300MHz 32 bits 120MHz 64 bits 1GHz Industry 0.1 Research Year Figure 1. The scaling-down of technology, illustrated with high-performance microprocessors. 3. SIGNAL INTEGRITY WITHIN INTEGRATED CIRCUITS Continuous improvements in integrated-circuit technology enable complex functions to be integrated at increasingly large operating frequencies. The benefits of the very high level of integration reached in state-of-the art technologies are jeopardized by the very hard problems of signal integrity. Figure 2 shows a simulated view of a very small portion of an integrated circuit, fabricated using 0.12 µm technology [Caignet et al., 2001]. Inter-layer oxides are removed for clarity. Up to eight layers of metal interconnects may be fabricated. The interconnect section is continuously reduced with the scale-down, leading to increased resistance and propagation delay. Aluminum has been used, until recently, to manufacture interconnects. To limit the increase in propagation delay, aluminum ( ρ al = Ω/µm) has been replaced by copper ( ρ cu = Ω/µm) [ A key parameter that has an immediate impact on the electromagnetic compatibility of integrated circuits is the voltage supply, as illustrated in Figure 3. A continuous reduction of the voltage supply is observed: 5 V down to 0.5 µm, 3.3 V down to 0.35 µm, 2.5 V down to 0.25 µm, etc. The main issue is the gate oxide breakdown within MOS devices. Recently, the concept of a multiple supply has been introduced. The internal part of the integrated circuit is supplied at low voltage (around 2 V in 0.18 µm technology), while the interface structures operate with a higher standard voltage supply, 2.5 V, to keep the circuit compatible with a wide variety of peripherals.

3 20. Electromagnetic Compatibility for Integrated Circuits 455 Therefore, three standard external supply voltages exist: 5 V, 3.3 V, and 2.5 V, while on-chip regulators produce lower voltage references for internal logic. Figure 2. A three-dimensional cross-sectional view of a 0.12 µm CMOS technology with seven metal layers. Figure 3. The decrease of supply voltage with the technology scale-down. Interconnects are routed very close to their neighbors, increasing lateral parasitic coupling. Consequently, the interconnects become the main limiting factor for improved performance and reliability [Grabinski, 1998]. The two most important aspects of signal integrity within interconnects are the crosstalk effect and the delay losses. In our review, we investigate the crosstalk effect, as it is closely related to electromagnetic-compatibility issues. We review the formulations and existing measurement methods, either external or directly on-chip, to characterize this effect.

4 456 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani 3.1 CROSSTALK COUPLING 1µm 1µm Figure 4. The coupling effects between interconnects in 0.25 µm (left) and 0.12 µm (right) ICs. Crosstalk coupling represents the parasitic transient voltage induced on a victim trace from a given transient disturbance injected on an aggressor trace. Over recent years, the crosstalk effect has been the focus of active research, from an analytical, experimental, and computer-aided prediction point of view. The main reason for this interest is illustrated in Figure 4. The aspect ratio of interconnects has dramatically changed with the technology scale-down. When comparing a 0.6 µm technology and a 0.12 µm technology, we clearly observe stronger coupling effects between adjacent interconnects, due to reduced spacing, larger lateral surfaces with respect to vertical surfaces, and the proportionality to the derivative of the disturbance, which switches much faster. Far end of the victim line Aggressor Victim Aggressor Minium spacing Minium spacing L = 2000 µm Receiver Voltage (V) Aggressor Signals Far end of the Victim line Crosstalk effect Time (ns) Figure 5. The crosstalk effect in a configuration with three coupled interconnects, for a 0.12 µm CMOS technology. The consequences in terms of cross-coupling waveform are illustrated in Figure 5. When the aggressors are switching, the coupling is strong enough to increase the voltage at the far end of the victim line, up to a switching threshold of the receiver gate connected at the far end of the victim line, which may provoke a permanent logic fault.

5 20. Electromagnetic Compatibility for Integrated Circuits 457 Aggressor Victim Technology 0.70µm 0.50µm 0.35µm Alu SiO2 Probable Fault Fault 0.25µm 0.18µm 0.12µm 0 25% 50% 75% Cu Low K Crosstalk/VDD (%) 100% Low K dielectric Figure 6. The evolution of crosstalk effects with the technology generation. Other conductor When investigating the maximum crosstalk amplitude versus the technology for a given interconnect length (2 mm, in the case of Figure 6), we observe a severe increase of the coupling effect as a direct consequence of the improvements in lithography. In ultra-deep sub-micron technologies (lithography lower than 0.18 µm), the permittivity of the lateral oxide that fills the spacing between adjacent interconnects is reduced (low K), while the oxide that separates vertical layers is kept with a high permittivity. The main effect is the decrease of lateral coupling effects. The introduction of low K materials may reduce the coupling effects up to a certain limit, as illustrated in Figure 5 for 0.18 µm generation, but future technologies should again suffer from this signal-integrity issue. 3.2 CROSSTALK MODELING As the signal switching moves to operating in less than 100 ps, it becomes especially crucial to obtain accurate values for the parasitic capacitance, resistance, and inductance of interconnects. Isolated wires over a conducting plane are the easiest to consider [Sakurai, 1993], but, in reality, interconnects consist of multiple wires, sandwiched between non-regular perpendicular traces. The geometrical dimensions of interconnects have drastically changed with the technology scale-down, as reported in Table 1. The lateral capacitance may represent 70% of the global capacitance to ground. Most of the early formulations were not accurate in deep sub-micron technology. Updated estimations of the two-dimensional capacitance-to-ground, the coupling capacitance, and the inductance have been proposed by [Delorme et al., 1996], using finite-element solvers as a reference. This approach is based on numerical approaches, where the capacitance and inductance matrices between conductors are computed. The method usually consists of the discretization of conductors and space into elementary elements, and the application of specific algorithms to solve electrical or electromagnetic equations (Maxwell s, Laplace s). An illustration of the twodimensional approach for extraction of coupling parameters in a three-conductor configuration, with a complex structure of low-k and high-k dielectrics, is reported in Figure 7.

6 458 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani Table 1. Physical dimensions of interconnects versus the technology scale-down [ Technology Interconnect Width Interconnect Thickness Aspect ratio tw Interconnects Material 0.7 µm 1.6 µm 1.1 µm Al 0.35 µm 0.8 µm 0.8 µm 1 5 Al 0.25 µm 0.5 µm 0.7 µm Al 0.18 µm 0.4 µm 0.6 µm Al & Cu 0.12 µm 0.3 µm 0.5 µm Cu 0.10 µm 0.2 µm 0.4 µm 2 7 Cu 0.07 µm 0.15 µm 0.35 µm Cu Figure 7. A two-dimensional finite-element method, applied to three coupled conductors to compute the [C] capacitance and [L] inductance matrices. The two-dimensional approach is not accurate for ultra-deep sub-micron technologies, since several couplings linked to the three-dimensional structure of the interconnect network should be considered. A set of analytical formulations were introduced by [Toulouse et al., 1999] for threedimensional modeling of inter-layer capacitances. Efficiency and accuracy were guaranteed by the process-characterization approach. Alternatively, experimental approaches have been used by [Chen et al., 1998; Nouet, 1997; Soumyanath, 1998] to measure the interconnect capacitance with 15 a precision better than 1fF (10 farad). From those measurements, the authors proposed models for capacitance-to-ground and coupling capacitance. Analytical formulations of the crosstalk amplitude in deep sub-micron technology were published by [Kuhlmann et al., 1999; Tang and Friedman, 1999], based on closed-form expressions for interconnection delay, coupling, and crosstalk proposed by [Sakurai, 1993] for older technologies. These analytic formulations are useful for rapidly extracting the R, L, C values for each net and the coupling matrix between interconnect, for circuits including millions of such interconnects. Prospective approaches for modeling interconnects within deep sub-micron ICs may be found in [Walker, 2000], as well as in the special issue on interconnects [Caignet et al., 2001].

7 20. Electromagnetic Compatibility for Integrated Circuits SIGNAL INTEGRITY MEASUREMENT The measurement of deep sub-micron parasitic effects linked to signal integrity has proven difficult to perform accurately. Although the measurement of the capacitive coupling has been performed successfully by several scientists [Chen et al., 1998; Nouet, 1997; Soumyanath, 1998], the dynamic aspects of the crosstalk and delay effects could not be characterized using such methods. To characterize the signal integrity within interconnects at ultra-high frequencies, two approaches have given satisfactory results: the [S] parameter technique [Williams et al., 1998], and the on-chip sampling technique [Delmas et al., 1999; Soumyanath, 1999; Caignet et al., 2001]. On-chip sampling circuits, also called on-chip oscilloscopes, are able to precisely measure the voltage waveform of signals, from which interconnect delays and coupling effects are characterized. As the technology is scaled down, the on-chip circuit performances are improved with the same trend as for the parasitic signals being measured, which is not the case for off-chip techniques. In 0.12 µm technology, the estimated bandwidth of the on-chip system is around 50 GHz. An example of crosstalk-waveform measurement on 0.18 µm technology is reported in Figure 8 [Caignet et al., 2001]. The near ends of the 3 mm aggressors rapidly reaches logic-level 1 (around 2 V). After a certain delay (mainly due to the combination of the resistance and capacitance of the line), the far ends of the aggressor lines also rise to logic-level 1. The victim line suffers a crosstalk fluctuation of close to half the supply voltage of the circuit. The on-chip sampling gives very precise estimates of both the amplitude and duration of this effect [Steinecke, 2000]. 0.25V/div Far end of aggressor Near end of aggressor Far end of victim line 0.2ns/div Figure 8. A measurement of the crosstalk effect with an on-chip sampling oscilloscope in 0.18 µm technology. Based on the [S]-parameter techniques, the response of single or coupled lines may be characterized up to 100 GHz [Williams, 1999]. The models extracted with this method are usually based on R, L, C, G elements, as reported in Figure 9. A detailed set of conditions and error levels

8 460 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani R( f ) ( ) for the usability of, L f, RLC, or RC circuits for crosstalk modeling is given in [Deutch et al., 1999]. The values of these basic elements are usually not constant, as they start to depend upon frequency above 1 GHz. 1 R I 1 L Vz 1() L C C G Vz 1( + dz) 2 R L C C y x Vz 2( ) I 2 C G Vz 2 ( + dz ) z dz Figure 9. The modeling of a portion of a conductor using R, L, C, G elements, at very high frequencies. 4. PARASITIC EMISSIONS OF INTEGRATED CIRCUITS Low emissions are becoming a major requirement for integrated circuits, to insure electromagnetic compatibility of electronic systems. With the technology scale-down [ the supply voltage is reduced, which tends to decrease the parasitic emissions. However, the current flowing within each elementary gate does not decrease significantly, but it flows much faster. As the number of gates tends to increase, due to progress in integration, stronger values of di dt are observed, leading to increased parasitic emissions. In [Robinson et al., 1998], experimental results provided quantitative evidence that digital circuits with faster logic give higher parasitic emissions. Two main concepts are introduced: conducted emission and radiated emission. Conducted emission refers to the parasitic disturbance created by the integrated circuit that propagates through the supply lines and input/output wires. Radiated emission refers to the parasitic electromagnetic energy emitted by the integrated circuit, which propagates through the air and may couple to other circuits without any common wires. The interference noise caused by integrated circuits has three distinct origins [Hayashi and Yamada, 2000]. The first effect is the direct radiation from the die, mainly due to long supply lines with strong current flows, and due to the voltage fluctuation of the whole die, which acts as a patch antenna. In [De Smedt et al., 2000], the effect of the radiation due to the component itself was clearly distinguished from the whole emission of the printed-circuit board. The second effect is the conduction noise, due to signal transitions occurring at I/O interfaces of the chip. The third effect is the internal switching noise, mainly conducted by power and ground-supply rails and pins.

9 20. Electromagnetic Compatibility for Integrated Circuits 461 Parasitic emission level (dbµv) Supplier A FM RF GSM Not EMC compliant 60 40dB 20 10dB Supplier B Probably EMC compliant Ultimate target Frequency (MHz) Figure 10. Two integrated circuits with identical functionality and a 1 Ω conducted-mode test setup may have very different parasitic emission spectra. The characterization of the electromagnetic emission is usually presented in the frequency domain, log/log, with the frequency along the x axis, and the emission level in dbµv on the y axis. The measuring conditions, for the case in Figure 10, consist of probing the current flowing through the ground pins of the integrated circuit, using a 1 Ω serial resistance added to the ground path (see Section 4.1 for more details on the setup). For automotive applications, three frequency bands are worthy of interest: the FM band, near 100 MHz; the short-distance radio links, near 400 MHz; and the GSM mobile phone lower band, near 900 MHz (GSM also operates at 1800 MHz). In Figure 10, one microcontroller exhibits a very high level of harmonics in the three sensitive bands. Electronic systems using this component would hardly comply with EMC regulations. The same component from another supplier, pin-to-pin compatible, features a significantly lower level of emission. The role of the IC package in parasitic emission is critical. The inductance of the packaging, combined with the on-chip capacitance, create an LC resonator that explains the main harmonics within the bandwidth of MHz [Hayashi and Yamada, 2000]. The LC resonance may be observed in both the radiated and conducted modes, at approximately the same frequency. The evolution of the maximum peak of the emission for a family of microprocessors is reported in Figure 11. The measurement setup again uses the 1 Ω serial resistance to probe an image of the conducted current flowing to the ground. From the measured spectrum (in dbµv), we only keep the harmonic with the maximum peak. The global trend corresponds to an increase of the peak energy, mainly due to higher internal clock speeds, an increased number of package leads, larger chip dies, and interconnect loops.

10 462 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani Maximum peak of conducted emission (dbµv) 90dB 1.0µm 0.7µm 0.35µm 0.18µm 70dB 20 db 50dB 30dB Microcontrolers Emission reduction techniques Research 10dB Figure 11. The evolution of the maximum peak of parasitic emission with the technological evolution toward small dimensions. 4.1 METHODS FOR MEASURING PARASITIC EMISSION Recently [International Electro-Technical Commission, 1999a; 1999b], standards for measuring the emissions of integrated circuits have been proposed, based on methods developed by IC designers, IC users, and research institutes. A review and comparative study of these proposals can be found in [Lubineau et al., 1999]. Figure 12. The TEM-cell method, used to capture radiated parasitic emission from 100 KHz to 1 GHz. The TEM-cell method, used by [Muccioli et al., 1996], measures the radiated emission of the integrated circuit. This method was issued by the Society of Automotive Engineers [Society of

11 20. Electromagnetic Compatibility for Integrated Circuits 463 Automotive Engineers 1752/3, 1995] in the USA. As illustrated in Figure 12, the chip is mounted alone on the inner side of a four-layer printed-circuit board (approximately cm). Most of the surface of the board is a ground plane, except at the location of the integrated circuit. Differential-mode electromagnetic emission from a component under test is received by the septum of the TEM cell (an isolated metallic plane inside the chamber), which is connected via a coaxial cable to a spectrum analyzer. The frequency range is typically 100 khz to 1 GHz. The comparative measurement of parasitic emission of a family of integrated circuits may be conducted easily, rapidly, and at a low cost. The investigations of the theoretical basis for using this TEM cell have been published in [Muccioli et al., 1997]. In the future, the GTEM cell could be used to investigate higher frequency ranges, up to 18 GHz. A conducted-mode method [Pfaff, 1998], issued by the German group VDE, is based on a 1 Ω serial resistance added to the ground path, and 150 Ω loads on the outputs [International Electro-Technical Commission, 1999a]. The frequency range is from dc up to 1 GHz. This method provides attractive insight into all pins of the component. In the case of a very large circuit, with numerous I/O pads, the method becomes heavy and slow to conduct. Moreover, signaldegradation effects may be introduced by the test setup itself, requiring careful calibration. 2 cm 50 Ω cable Probe Frequency analyser 2 cm 7 cm Integrated circuit under test Shileding interruption 1mm Figure 13. A magnetic probe for near-field scanning close to the surface of the integrated circuit. Other methods may be found in literature. A method for scanning the near electrical fields at the surface of integrated circuits has been described in [Slatery et al., 1999]. This method has a 500 µm resolution, in order to build a detailed scan of the field emission near the surface of the die, which is intended to help IC designers improve their design strategy at the IC layout and packaging levels. A magnetic-probe method, issued by the SAE, is also part of the international standard [International Electro-Technical Commission, 1999a]. It measures the magnetic field within the range 1 MHz - 1 GHz. The probe is 20 mm in diameter, with an electrostatic screen to avoid the electrical field (Figure 13). The Workbench Faraday Cage method, also proposed in [International Electro-Technical Commission, 1999a], consists of placing the IC and its test board in a small Faraday cage, with all inputs/outputs fed through the box via coaxial connectors, and loaded with 150 Ω resistance to ground, representing the average common-mode load in the final application. 4.2 MODELING OF PARASITIC EMISSION The first step in the modeling of parasitic emission has been the input/output-buffer specification [ also called IBIS, used to specify and predict the parasitic

12 464 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani fluctuations provoked by the switching of on-chip buffers. The IBIS description includes active devices, represented by tabulated IV sources, and a description of the packaging based on R, L, and C parameters. Unfortunately, the supply lines are not considered in IBIS, which jeopardizes its use for parasitic-emission modeling. An alternative approach, proposed by [Canavero et al., 2001], consists of modeling the behavior of switching I/Os using so-called black boxes, which reproduce, in a very accurate way, the non-linear characteristics of the signals issued from the integrated circuit. The Electronic Industry Association of Japan (EIAJ) proposed [ a more physical approach for IC modeling, including the supply network that was ignored by IBIS. Despite these improvements, IMIC fails to describe internal-current sources that are responsible for core noise. The modeling of conducted emission requires a precise knowledge of the core switching. It is necessary to perform a circuit simulation to obtain current waveforms outgoing from the chip to the power and ground-supply pins [Hayashi and Yamada, 2000]. Several approaches are applicable to obtaining the time-domain current waveforms for the main current sources of integrated circuits, focusing mainly on high-frequency clocked signals. For small blocks (phaselocked loop, clock tree), a SPICE simulation may be conducted. However, for large blocks, such as control-process units or signal-processing units, the amount of physical data is so large that specific algorithms are mandatory. Some tools, like POWERMILL, use tabulated MOS characteristics and simple RC models to speed up the simulation, neglecting coupling and ground-bounce. The current estimation for blocks with a complexity up to one million devices may be obtained using this tool. For very complex integrated circuits, the combination of a logic simulator and a current-peak library may produce reliable switching-current waveforms. The switching current is characterized for each logic cell of the library, with typical control slew-rates and load conditions. The methodology for power-network and switching-current modeling [Hayashi and Yamada, 2000] seems very promising for conducted-emission prediction,. The suggested approach focuses on the extraction and simplification of the switching current to periodic triangular waveforms, combined with the on-chip decoupling capacitance and package inductance. Predicted spectra are nicely correlated with experimental data for a set of complex integrated circuits. In contrast, research efforts are still mandatory to accurately predict the radiated emission of integrated circuits. The coupling between the device under test and the TEM cell remains unclear. However, methods for electromagnetic-interference prediction in the radiated mode should appear in the near future. 4.3 REDUCTION TECHNIQUE FOR LOW PARASITIC EMISSION As a low parasitic emission can represent a significant commercial argument for choosing an integrated circuit, several approaches for reducing parasitic emission at the chip level have recently been discussed [John et al., 2000; Mardiguian, 2001]. A promising approach is the use of absorbent materials at the package level [Kim et al., 2000], under the condition of covering the die region and both sides of the package lead frame, with an expected gain of up to 20 db.

13 20. Electromagnetic Compatibility for Integrated Circuits 465 Various design strategies have proven efficient for reducing the parasitic emission by several db for microcontrollers [Steinecke, 2000; Hayashi and Yamada, 2000] and specific test chips [Van Wershoven, 2000]. Effective techniques are concerned with the on-chip decoupling capacitance, the current-limiting choke resistance, and supply-network optimization. Distributing decoupling capacitors close to main current sources (CPU, clock drivers, PLLs), in combination with currentlimiting resistors in series on the supply lines, turned out to reduce the peak harmonics by db. Other techniques for reducing the parasitic emission, as suggested in [De Smedt et al., 2000] concerned the use of low-swing clock signals, non-simultaneous buffer switching by the addition of small RC delays, and careful cancellation of currents by parallel routing of supply and ground lines inside the chip. 5. SUSCEPTIBILITY OF INTEGRATED CIRCUITS Susceptibility to radio-frequency (RF) interference is becoming a major concern for integrated circuits, with the proliferation of powerful parasitic sources such as mobile phones, high-speed networks, and wireless systems. Meanwhile, the noise margin of integrated circuits tends to be reduced as a consequence of lower supply voltages. The devices may receive interference that is superimposed on the intentional signals, causing rectification, intermodulation, cross-modulation, or other disturbances. The external wires, cables, and even the printed-circuit-board traces may work as antennae, and propagate the captured radio-frequency noise to the integrated circuit. Susceptibility relates both to analog and digital components. However, most of the research work in the past three years has concerned analog devices. We detail, in the following paragraphs, the approaches for the characterization of susceptibility at the single device, analog block, and digital circuit levels. 5.1 SINGLE DEVICE SUSCEPTIBILITY TO RF Studies of the distortion due to radio-frequency interference (RFI) in elementary MOS and bipolar devices have been conducted by [Sansen, 1999] and [Fiori and Pozzolo, 2000]. A radiofrequency voltage, applied to one termination of the device, induces a variation in its characteristics, as illustrated in Figure 14. The normal dependence of the drain current,, on the drain-to-source voltage, V, for varying gate voltage, V, is represented in the upper-left part of ds Figure 14. The measurement is purely static. When adding a RF voltage to the normal polarization voltage, V, we observe a significant change in the I V characteristics. One reason for this gs parasitic effect is the nonlinear dependence of V on the current. In [Hayashi et al., 1998], the technique of harmonic balance was proposed for analyzing the undesired dc shift under large RF injection. A modified version of the Gummel-Poon bipolar device was also proposed by [Fiori and Pozzolo, 2000], to achieve the same goal. gs ds gs ds I d 5.2 SUSCEPTIBILITY OF ANALOG BLOCKS Good reference voltages and high-performance operational amplifiers are required in most integrated circuits, for on-chip voltage regulation, analog-to-digital and digital-to-analog

14 466 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani conversion, filtering, and amplification. Therefore, the operating-point upset induced by radiofrequency interference should be minimal. The bandgap voltage reference has been analyzed by [Fiori et al., 2000], showing an important dc offset the amplitude of which increases with interference amplitude and frequency. The main contribution to the parasitic offset was the input stage of the differential amplifier, driven simultaneously by common- and differential-mode noise, acting as a mixer. Similar behavior was observed by [Baudet et al., 1998], with offset voltages generated at the output ports due to a combination of two mechanisms: the feedback loop falling effect and the unbalanced behavior of the differential stage of the amplifier, when excited by an RF source above the cutoff frequency of the circuit. Ids Normal Vgs Ids With radio-frequency interference Vgs Vds Vds RF source Supply 1 Coupler Inductor Vgs Vds Device under test Supply 2 Load Figure 14. Susceptibility analysis for a single device, and the observed shift in static characteristics. 5.3 DIGITAL CIRCUIT SUSCEPTIBILITY TO RF Programmable-processor-based circuits, like microcontrollers, are prone to corruption by fast transients, resulting in erroneous logic states that may lead to embedded software errors and, ultimately, a loss of functionality. In the previous sections, microcontrollers have been regarded as parasitic-emission sources. Some authors also consider these devices as potential victims of electromagnetic disturbances, within a large range of frequencies (100 khz up to 1 GHz). The susceptibility of 8-bit and 16-bit microcontrollers has been evaluated [Kucinski and Kolodziejski, 2000] and [Habiger and Vick, 2000]. The device-immunity threshold was determined for each frequency within the range 100 khz to 1 GHz. Susceptibility against electromagnetic disturbances proved to be a time-variant phenomenon, since the threshold changed significantly depending on the operational function of the microcontroller. In other words, the susceptibility depended on the micro-instructions, and the activity on the system bus. Evidence of coupling between the injection port and the supply was also observed. When the injected RF signal was connected to the input ports, a correlated noise appeared in the supplyspectrum characteristics and at the circuit output.

15 20. Electromagnetic Compatibility for Integrated Circuits MEASUREMENT OF SUSCEPTIBILITY When starting to design an item of equipment, information about the susceptibility threshold of its components is essential to ensure that appropriate components have been selected and that electromagnetic compatibility is guaranteed. In order to ascertain these thresholds, reliable and simple measurement methods are mandatory. Although no EMI regulation is defined for integrated circuits alone, measurement methods are under standardization within the International Electro-technical Commission (IEC), Committee 47A, Working Group 9, in charge of proposing standards for measuring emission and susceptibility of integrated circuits. The susceptibility standards are referenced under Project Number IEC [International Electro-Technical Commission, 1999b]. The parameters, the general setup, and the conditions for the different tests are described in Part 1. Part 2 defines a method to measure the IC susceptibility level with capacitance coupling, directly on the integrated circuit. The test setup uses a specific printedcircuit board, on which the device under test is placed. The injection is performed through a coupling capacitance, operating within the frequency band of 10 khz to 1 GHz. This method has already been applied to the characterization of susceptibility of a microcontroller by [Fiori, 2000]. In Part 3 of the standard, a method for measuring the IC susceptibility level in common mode is detailed. The test setup is based on a workbench Faraday cage (WBFC), inside which the integrated circuit under test is placed. The printed-circuit board is also inside the cage. The WBFC method considers that ICs are principally reached from interference collected by cables that are directly connected to the PCB. The RF energy is communicated via a 150 Ω resistance. The susceptibility is measured by checking the state of I/Os, outside the cage. The measurement test setup operates within the frequency range 150 khz to 1 GHz. According to [Fiori, 2000], the WBFC method may not reveal functional errors during the susceptibility test if the test board inside the cage has been designed to reduce common-mode noise. By pass filter injection and measurement probes Peripherial components I device under test Optical interface 20cm ground plane Shielded room H.F Voltmeter Control tool fiber optic link H.F Ampli H.F Generator Figure 15. The setup for susceptibility analysis using the bulk-current-injection method.

16 468 E. Sicard, C. Marot, J. Y. Fourniols, and M. Ramdani Finally, a method to measure the IC susceptibility level with inductive coupling on wires connected directly to the integrated circuit was proposed in Part 4. The measurement is valid within the frequency range of 15 khz to 400 MHz. The method consists of injecting a current using a magnetic probe on the input or output of the integrated circuit (Figure 15). A fiber-optic link is used to monitor the output signals. In the event of defects on these signals, the reading of the injected current provides the susceptibility threshold. i RF RF Decoupling 12V protection 100nF L 4949 VIN VOUT SI SO Vx RESET Ct GND Optical control 5V Decoupling Typical load Electrical ground I RF (dbma) Frequency MHz Figure 16. Experimental results of the susceptibility of a voltage regulator with RF injection on the supply line, from 10 to 400 MHz. The measurement reported in Figure 16 shows the value of the current, i RF, injected on the supply pin of the regulator, which provokes an undesired activity on the reset, with a frequency varying from 15 khz to 400 MHz. The result reported in Figure 16 shows a decrease of the injected current, i RF, up to 350 MHz. This means that the device is particularly sensitive to RF noise around 350 MHz. The link with the physical characteristics of the device is still not clearly established. 6. CONCLUSION Current research in electromagnetic compatibility for integrated circuits is probing the numerous issues linked to the progresses in the technology scale-down and increased radio

17 20. Electromagnetic Compatibility for Integrated Circuits 469 interference. This review has addressed some of the recent advances in the measurement and modeling of parasitic emissions and susceptibility to radio-frequency noise. However, all topics related to EMC for integrated circuits were not covered. The main EMC conferences regularly propose special sessions on devices and circuits, providing a continuous source of research advances and improvements. Measurement methods for both emission and susceptibility are in the standardization phase. From the point of view of emission, complete design flows including current-source characterization, internal-supply modeling, and package modeling represent a major step forward for the prediction of parasitic emission from integrated circuits during the design phase, before fabrication. Simple and standard models should be proposed for and should be capable of simulating the conducted and radiated emission, similar to what already exists regarding input/output description and behavior. The research on susceptibility has mainly been carried out for single devices or smallcomplexity analog blocks. Expertise on large-logic or mixed integrated circuits is needed, and it is to be expected that novel design guidelines, hardware, and software techniques will be developed to reduce the susceptibility to radio-frequency interference in the near future. With the expansion of wireless communications, and continuous advances in microelectronic circuit performance, an improvement in the knowledge of high-frequency modeling, circuit, and package-complexity reduction, as well as radiation mechanisms is needed to achieve the electromagnetic compatibility of integrated circuits in the future. 7. ACKNOWLEDGEMENTS The authors wish to thank Marc Lubineau, Sebastien Calvet, and colleagues from the IERSET EMC for ICs project, as well as the MEDEA A-408 partners for their significant contribution and helpful comments. They would also like to thank the reviewers for their helpful comments and suggestions. 8. REFERENCES J. Baudet, O. Druant, and B. Demoulin [1998], Effects of Electromagnetic Interference of High Amplitude on FET-Differential Amplifier in the Frequency Range of 100 MHz-1 GHz, in International Symposium on Electromagnetic Compatibility EMC 98 ROMA, pp F. G. Canavero, I.A. Maio, and I. S. Stievano [2001], Black Box Models of Digital IC Ports for EMC Simulation, in International Symposium on EMC, Zurich, pp J. C. Chen, D. Sylvester, and C. Hu [1998], An On-Chip Interconnect Capacitance Characterization Method with Sub-Femto Farad Resolution, IEEE Transactions on Semiconductor Manufacturing, 40, pp F. Caignet, S. Delmas, and E. Sicard [2001], The Challenge of Signal Integrity in Deep Sub- Micron CMOS Technology, Proceedings of the IEEE, 86, 4, pp S. Delmas, E. Sicard, and F. Caignet [1999], A Novel Technique for the Dynamic Measurements

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