Visible Light Photon R&D in the US. A. Bross KEK ISS Meeting January 25, 2006

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1 Visible Light Photon R&D in the US A. Bross KEK ISS Meeting January 25, 2006

2 Some History First

3 VLPC History In 1987, a paper was published by Rockwell detailing the performance of Solid State PhotoMultipliers (SSPMs). These solid state devices detected both visible and infrared light. Infrared detection technology is regulated under international treaty so Fermilab proposed a device which maintained the visible light response, but reduced the infrared response. This device is called a Visible Light Photon Counter (VLPC). With the successful demonstration of VLPC technology, the High-Resolution Scintillating Fiber Tracking Experiment (HiSTE) proposal detailed using scintillating fiber technology combined with VLPCs to track particles from high energy particle collisions. There have been six models of HiSTE chips, with HiSTE-VI being used in the DØ experiment.

4 VLPC Operational Principles Photon is converted the intrinsic region, creating an electron-hole pair. Hole drifts into the drift region, where it knocks an electron out from an atom. Electron accelerates back through gain region, knocking electrons from atoms as it goes. Spacer region and substrate are for mechanical support and field shaping. Thus each photon generates a pulse of many electrons. Gains of 20,000 60,000 are achievable. Photon Intrinsic Region + e Top Contact (+) Gain Region h E field Undoped Silicon (Blocking) Layer Gain Region Drift Region Drift Region D + flow Doped Silicon Layer Substrate Spacer Region - Bottom Contact (-)

5 VLPC Timeline Initial SSPM Publication Fermilab Approaches Rockwell About HEP Applications VLPCs Differentiated From SSPMs HiSTE Proposal Submitted HiSTE IV Manufactured 3000 Channel Scintillating Fiber Test at Fermilab Large Scale Testing of HiSTE VI Begins 140,000 VLPC Pixels DØ Data Taking Commences The Hunt Is On!! Experiments By Rockwell And Fermilab/UCLA Using Scintillating Fibers and SSPMs VLPCs Successfully Demonstrated HiSTE I, HiSTE II, HiSTE III DØ Scintillating Fiber Tracker Proposed HiSTE VI Wafers Grown Final VLPC Design DØ Scintillating Fiber Tracker Installed Commissioning Begins

6 HiSTE VI Solid state photon detectors Operate at a few degrees Kelvin (~ F) Bias voltage 6-8 Volts Detects single photons Can work in a high rate environment Visible

7 DØ Scintillating Fiber Tracker: Charged particles cross a scintillating fiber, where it causes a blink of light. Operational Principles The light is transported via optical fiber over a distance of 8-11 meters to a device called a VLPC which converts light into electricity. VLPC are solid state devices which run at cryogenic temperatures. A cassette of VLPC devices contains 1024 channels and is housed in a cryostat, which carefully regulates the operating temperature. Mirror Scintillating Fiber Photodetector Cassette Cryostat Optical Connector Waveguide Fiber Electrical Signal Out

8 VLPC History The Visible light Photon Counter is an impurity band avalanche photodiode that operates in the range of 6-10K Parameters (from D0 program) QE = 85% Gain = 35k-65k Noise = khz (@1 pe threshold) Most-Importantly: COST For the D0 program (approximately 120k pixels (1mm) the per channel cost for the VLPC system (packaged, tested, delivered) was $60/Ch

9 Silicon Wafer Processing Conventional silicon processing at >µm resolution 3-inch wafers for D0 176 VLPC arrays 1408 VLPCs Future production 6-inch wafers About 5000 to VLPCs/wafer Array format(s) TBD

10 VLPC Hybrid A B A Face photo of assembled hybrid C A B A = VLPC die B = AlN substrate B Edge view of assembled hybrid C = Indium solder preform

11 Uniformity Issue

12 Hybrid Assembly Process Holes for weights Top View Bottom Boat Substrate Holder Dice Holder Top Boat Weights Top Boat Side View Dice Holder Bottom Boat Substrate Holder Vacuum Sealer

13 Improved Gain Uniformity Number of VLPCs Gain (10 3 electrons/photon) D0 VLPC gain varied by material group (~20 wafers) Smaller variations across wafers and from wafer to wafer Causes: ca 1980 growth reactors with insufficient control of gas flows/growth temperature Multi-wafer growth geometry Solution for D0: Sort Solution for next generation: Utilization of modern,

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16 New R&D

17 HISTE VII Lawrence Semiconductor Research Laboratory (LSRL) won Phase I SBIR to develop new VLPC material Boeing DRS Technologies consulted Henry Hogue/Dutch Stapelbroek Reactors at Boeing/DRS decommissioned after D0 work Since then LSRL has been growing BIB epi material for all of DRS s projects EKV Star Wars Lite Phase I objectives Reproduce HISTE VI and SSPM material Scan target parameters with various splits Measure bulk properties Spreading Resistance Profile Cryo C-V 4 Point probe FTIR infrared spectroscopy Defect density Goal Better Uniformity (gain) and lower defect density

18 HISTE VII 80 5 wafers were grown Note: LSRL reactors can go up to 8 Limited to 6 by processing at DRS Used 5 followed BIB work 8 Splits of 10 wafers each Note: based on HISTE VI geometry this represents 300k potential pixels Used highly doped (As) substrates in order to go to large wafer size D0 used antimony Layer IV (undoped) L ay er III (A s an d B ) L ayer II (A s an d B ) Layer I (A s and B ) H ighly doped substrate (A s)

19 HISTE VII Spreading Resistance Profiling (SRP) Determines layer thicknesses and Ar concentration in doped layers Four point probe (4PP) and Fourier transform Infrared Spectroscopy Sheet resistance and thickness Single layer Cryogenic C-V Characterize acceptor background and boron doping levels in gain region. T L C R Samples taken from select group of wafers (8X5) for analysis B flat

20 HISTE VII FTIR and 4PP Results Uniformity 5 to 10X more uniform than D0 material Target thickness 18 µm

21 HISTE VII SRP results V L P C S p r e a d i n g R e s i s t a n c e P r o f i l e - S a m p l e J E E E E L a y e r 4 L a y e r 3 L a y e r 2 L a y e r E E Concentration (at/cc) T o p C e n t e r B o t t o m L e f t R i g h t S p e c S u b s t r a t e E E E T h i c k n e s s ( m i c r o n s ) Target As concentrations: Layers 1&2: 9X10 17 cm X10 17 cm -3 for layer 3

22 HISTE VII Cryo C-V Measures Boron doping in gain region Average: 3.0X10 13 cm -3 Target 3.5X10 13 cm -3 16% low. RMS 12% consistent with measurement precision

23 HISTE VII Epitaxial layer defects Scanned with bright light inspection and verified with microscope Average defect count less than 5 per 5 wafer Corresponds to 0.08 defects per cm 2 D0 material: 4 defects per cm 2 X50! VLPC Pulses? Since processing was not part of Phase I HH made detector from epi using In contacts Saw pulses

24 HISTE VII Phase II ($750k) Fabricate and test detectors using the epitaxial layers grown in Phase I. Refine the detector design based on the test results, and revise the epitaxial layer specifications accordingly. Grow a second round of epitaxial layers. Extend the design work to include an integrated package. Fabricate, test and package detectors in a form that will be offered for sale in sample quantities to end users. Iterate the design, growth and packaging into a successful commercial product. So we can expect Packaged devices (HISTE VI geometry) HISTE VI, VII, VIII? + SSPM High Density geometry will likely be tried also 16 X mm pixel? Potential for many pixels

25 Improvements to VLPC Wafer Processing AR Coating D0 VLPCs used quarter wave SiO 2 AR coating 5-10% reflection loss Silicon nitride and silicon monoxide are better matched coating materials now available Should improve VLPC QE from ~85% to >90% Scratch Coating D0 VLPCs had exposed AL traces Resulted in minor die losses due to handling Over coating traces will eliminate this loss

26 Process Lot split Lot started with two 5 wafers from each of 8 epitaxy groups grown by LSRL in SBIR Ph 1 Plus 2 wafers each of 7 old 3 VLPC epitaxy groups grown after DZERO product runs Plan: Process 1 wafer of each type through standard process and evaluate Dice, package (not hybrids), and performance test at DRS Based on test results, provide epitaxy parameters to LSRL for new material run on SBIR Put remaining wafers through improved AR coating process Etch oxide from detector area Apply silicon nitride AR coating thickness over entire wafer Improved AR coat plus scratch coat over aluminum leads Open coating for gold deposition on pads as before Prepare hybrids from best epitaxy groups for testing at Fermilab

27 3 X 3 (3mm X 3mm) 4X8 (.5mm) 2X4 (1 mm) [D0] 1 cm 2 single pixel 16X16 (.5mm)

28 32 Channel array (.5 mm pixel) Mask Design

29 16 X 16 (.5 mm pixel) Mask Design

30 R&D production Devices SiN AR coating Expect QE 98%

31 HISTE VII Conclusions on SBIR R&D Program Phase I and II work went very well LSRL is a very competent/professional organization Grew 80 wafers can be fabricated for about $150k! This is the epitaxial growth step: $0.1/1 mm pixel Note D0 cost was $2/pixel We estimate that the epitaxial wafers can be processed for about $2-3k/wafer About $0.3/1 mm pixel We expect yields of 90% (to be determined in upcoming tests) D0 Yield was 70% New material is 5 to 10X more uniform than the D0 material and the defect density is 50X smaller 1 mm pixel cost at wafer level <$0.5/pixel!

32 Next Steps Integration/packaging Cryo This represented about ½ the cost in D0 ($25/pixel) Going to larger array and 0.5 mm pixel improves this situation tremendously This R&D has not started, no funding in sight presently Going to 16 X mm pixel array See over a factor 10 reduction in cost in packaging Expensive for D0 Convention LHe plant MICE has made progress Developed system using commercial cryo-coolers Tested at Fermilab and KEK Has worked extremely well

33 VLPC Readout System Using 1024 channel D0 VLPC cassette design 8-1mm element array However, will use a cryocooler system to reach 9K operating temperature Sumitomo SRDK-451D

34 MICE VLPC Cryo-System The new system has been built, commissioned, and now operated for a period of 2 months at Fermilab and 3 months in Japan

35 Cryo Operation System Stability has been impressive! ± 10 mk over a period of months Just running cryo-cooler no Cassette control

36 VLPC Integration R&D can yield a device with >95% QE, gain on the order of 50K at less than $1USD per 1 mm pixel Use of Cryo-coolers has been demonstrated Allows for straightforward way to produce large distributed system Performance of latest devices we be studied in the coming months Currently assembling 1024 channel system with devices from the R&D run Verify QE, gain uniformity and noise Integration/packaging R&D at ground zero Need to readout many more channels per cryo-cooler Now 2k Need 20k ($2/ch) 2 X 4 1mm array 16 X 16 (0.5mm) array Integrated Front-end electronics (cold) $10/ch is possible But Requires dedicated and aggressive R&D

37 Segmented Magnetic Detector The optimization for a highly segmented detector is clearly critically dependent on the signal strength (light yield) from the basic cell High light yield active component implies Small WLS fibers can be used if high QE PD is available Small WLS fibers allow for small PD Small PD allow for high-level integration High-level integration reduces cost This is possible with a properly designed R&D program with appropriate funding